Uboot SERDES configuration for PCIEx4 on mvebu 38x

[Tyler S]

Hi,

I am trying to create a pcie x4 interface using a standard SERDES map on a
Marvell 38x chip (MV88F6828) in Uboot 2019.01. However lane verification
prevents me from enabling the pcie x4 configuration.

The closest example I can find is this slm1363 board from this file:
https://github.com/u-boot/u-boot/blob/3d4825446e4258192e1f2302d691a8c0c82a0975/arch/arm/mach-mvebu/serdes/a38x/high_speed_topology_spec-38x.c
:

struct serdes_map db_config_slm1363_d[MAX_SERDES_LANES] = {
    {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
    {PEX1, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
    {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
    {PEX3, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X4, 0, 0},
    {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
    {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
}

This is exactly the config I want. However that board was patched out in
this commit
https://github.com/u-boot/u-boot/commit/544acb07ecebc096c9449e675481ba280311fb0b
due to it being an unsupported topology?

If I configure uboot for my board using the example above, I get the
following output:

board SerDes lanes topology details:
 | Lane #  | Speed |  Type       |
 --------------------------------
 |   0    |  5   |  PCIe0       |
 |   1    |  5   |  PCIe1       |
 |   2    |  5   |  PCIe2       |
 |   3    |  5   |  PCIe3       |
 |   4    |  5   |  USB3 HOST0  |
 |   5    |  5   |  USB3 HOST1  |
 --------------------------------
hws_serdes_topology_verify: Warning: serdes lane 2 is set to type PCIe2.
hws_serdes_topology_verify: Maximum supported lanes are already set to this
type (limit = 4)
hws_update_serdes_phy_selectors: SerDes lane #2 is  disabled
hws_serdes_topology_verify: Warning: serdes lane 3 is set to type PCIe3.
hws_serdes_topology_verify: Maximum supported lanes are already set to this
type (limit = 4)
hws_update_serdes_phy_selectors: SerDes lane #3 is  disabled
board SerDes lanes topology details:
 | Lane #  | Speed |  Type       |
 --------------------------------
 |   0    |  5   |  PCIe0       |
 |   1    |  5   |  PCIe1       |
 |   4    |  5   |  USB3 HOST0  |
 |   5    |  5   |  USB3 HOST1  |
 --------------------------------


If I comment out the SERDES lane verification in
arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c, it seems I can
configure the x4 link successfully and recognize the drive that is
connected.

Can anyone shed some light on the proper way to configure the serdes map
for pcie x4?

Thanks!
Tyler