[PATCH] riscv: fix the wrong swap value register

[Lukas Auer]

On Fri, 2020-11-13 at 20:47 +0900, Brad Kim wrote:

> Not s2 register, t1 register is correct
> Fortunately, it works because t1 register has a garbage value
> 
> Signed-off-by: Brad Kim <brad.kim at semifive.com>
> ---
>  arch/riscv/cpu/start.S | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Thanks for catching this issue!

Reviewed-by: Lukas Auer <lukas at auer.io>