[RESEND v2 10/22] drivers: clk: dm: Add clock driver for Diamond Mesa
Tan, Ley Foon
ley.foon.tan at intel.com
Fri Nov 20 10:24:05 CET 2020
> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim at intel.com>
> Sent: Tuesday, November 10, 2020 2:44 PM
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex at denx.de>; Tan, Ley Foon
> <ley.foon.tan at intel.com>; See, Chin Liang <chin.liang.see at intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>; Westergreen, Dalon
> <dalon.westergreen at intel.com>; Simon Glass <sjg at chromium.org>; Gan,
> Yau Wai <yau.wai.gan at intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim at intel.com>
> Subject: [RESEND v2 10/22] drivers: clk: dm: Add clock driver for Diamond
> Mesa
>
> Add clock manager driver for Diamond Mesa. Provides clock initialization and
> get_rate functions.
>
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim at intel.com>
> ---
> drivers/clk/altera/Makefile | 3 +-
> drivers/clk/altera/clk-dm.c | 504
> +++++++++++++++++++++++++++++++++++
> drivers/clk/altera/clk-dm.h | 213 +++++++++++++++
> include/dt-bindings/clock/dm-clock.h | 71 +++++
> 4 files changed, 790 insertions(+), 1 deletion(-) create mode 100644
> drivers/clk/altera/clk-dm.c create mode 100644 drivers/clk/altera/clk-dm.h
> create mode 100644 include/dt-bindings/clock/dm-clock.h
>
> diff --git a/drivers/clk/altera/Makefile b/drivers/clk/altera/Makefile index
> 96215ad5c4..08f16fd7cd 100644
> --- a/drivers/clk/altera/Makefile
> +++ b/drivers/clk/altera/Makefile
> @@ -1,7 +1,8 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
> -# Copyright (C) 2018 Marek Vasut <marex at denx.de>
> +# Copyright (C) 2018-2020 Marek Vasut <marex at denx.de>
> #
>
> obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
> obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
> +obj-$(CONFIG_TARGET_SOCFPGA_DM) += clk-dm.o
> diff --git a/drivers/clk/altera/clk-dm.c b/drivers/clk/altera/clk-dm.c new file
> mode 100644 index 0000000000..c8421ed20b
> --- /dev/null
> +++ b/drivers/clk/altera/clk-dm.c
> @@ -0,0 +1,504 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation <www.intel.com> */
> +
> +#include <common.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/io.h>
> +#include <clk-uclass.h>
> +#include <dm.h>
> +#include <dm/lists.h>
> +#include <dm/util.h>
> +#include <dt-bindings/clock/dm-clock.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +struct socfpga_clk_platdata {
> + void __iomem *regs;
> +};
> +
> +/*
> + * function to write the bypass register which requires a poll of the
> + * busy bit
> + */
> +static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat,
> +u32 val) {
> + CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS);
> + cm_wait_for_fsm();
> +}
> +
> +static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat,
> +u32 val) {
> + CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS);
> + cm_wait_for_fsm();
> +}
> +
> +#ifndef CONFIG_TARGET_SOCFPGA_DM
> +/* function to write the ctrl register which requires a poll of the
> +busy bit */ static void clk_write_ctrl(struct socfpga_clk_platdata
> +*plat, u32 val) {
> + CM_REG_WRITEL(plat, val, CLKMGR_CTRL);
> + cm_wait_for_fsm();
> +}
> +#endif
This .c file only get compiled when CONFIG_TARGET_SOCFPGA_DM is enabled. This code will never get compiled.
Same for the similar #ifndef in this file.
[....]
> +static u64 clk_get_pll_output_hz(struct socfpga_clk_platdata *plat,
> + u32 pllglob_reg, u32 plldiv_reg)
> +{
> + u64 clock = 0;
> + u32 clklsrc, divf, divr, divq, power = 1;
> +
> + /* Get input clock frequency */
> + clklsrc = (CM_REG_READL(plat, pllglob_reg) &
> + CLKMGR_PLLGLOB_VCO_PSRC_MASK) >>
> + CLKMGR_PLLGLOB_VCO_PSRC_OFFSET;
> +
> + switch (clklsrc) {
> + case CLKMGR_VCO_PSRC_EOSC1:
> + clock = cm_get_osc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_INTOSC:
> + clock = cm_get_intosc_clk_hz();
> + break;
> + case CLKMGR_VCO_PSRC_F2S:
> + clock = cm_get_fpga_clk_hz();
> + break;
> + }
> +
> + /* Calculate pll out clock frequency */
> + divf = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_FDIV_MASK) >>
> + CLKMGR_PLLDIV_FDIV_OFFSET;
> +
> + divr = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_REFCLKDIV_MASK) >>
> + CLKMGR_PLLDIV_REFCLKDIV_OFFSET;
> +
> + divq = (CM_REG_READL(plat, plldiv_reg) &
> + CLKMGR_PLLDIV_OUTDIV_QDIV_MASK) >>
> + CLKMGR_PLLDIV_OUTDIV_QDIV_OFFSET;
> +
> + while (divq) {
> + power *= 2;
> + divq--;
> + }
> +
> + return ((clock * 2 * (divf + 1)) / ((divr + 1) * power)); }
> +
> +static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32
> clksrc_reg,
> + u32 main_div, u32 per_div)
> +{
> + u64 clock = 0;
> + u32 clklsrc = clk_get_5_1_clk_src(plat, clksrc_reg);
> +
> + switch (clklsrc) {
> + case CLKMGR_CLKSRC_MAIN:
> + clock = clk_get_pll_output_hz(plat,
> + CLKMGR_MAINPLL_PLLGLOB,
> + CLKMGR_MAINPLL_PLLDIV);
> + clock /= 1 + main_div;
> + break;
> +
Remove extra empty line. Same for the rest.
[...]
> +
> +#endif /* _CLK_DM_ */
> diff --git a/include/dt-bindings/clock/dm-clock.h b/include/dt-
> bindings/clock/dm-clock.h
Check we use same file from Linux, and also macro names.
> new file mode 100644
> index 0000000000..d624ac723c
> --- /dev/null
> +++ b/include/dt-bindings/clock/dm-clock.h
> @@ -0,0 +1,71 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020, Intel Corporation */
> +
> +#ifndef __DM_CLOCK_H
> +#define __DM_CLOCK_H
> +
> +/* fixed rate clocks */
> +#define DM_OSC1 0
> +#define DM_CB_INTOSC_HS_DIV2_CLK 1
> +#define DM_CB_INTOSC_LS_CLK 2
> +#define DM_L4_SYS_FREE_CLK 3
> +#define DM_F2S_FREE_CLK 4
> +
> +/* PLL clocks */
> +#define DM_MAIN_PLL_CLK 5
> +#define DM_MAIN_PLL_C0_CLK 6
> +#define DM_MAIN_PLL_C1_CLK 7
> +#define DM_MAIN_PLL_C2_CLK 8
> +#define DM_MAIN_PLL_C3_CLK 9
> +#define DM_PERIPH_PLL_CLK 10
> +#define DM_PERIPH_PLL_C0_CLK 11
> +#define DM_PERIPH_PLL_C1_CLK 12
> +#define DM_PERIPH_PLL_C2_CLK 13
> +#define DM_PERIPH_PLL_C3_CLK 14
> +#define DM_MPU_FREE_CLK 15
> +#define DM_MPU_CCU_CLK 16
> +#define DM_BOOT_CLK 17
> +
> +/* fixed factor clocks */
> +#define DM_L3_MAIN_FREE_CLK 18
> +#define DM_NOC_FREE_CLK 19
> +#define DM_S2F_USR0_CLK 20
> +#define DM_NOC_CLK 21
> +#define DM_EMAC_A_FREE_CLK 22
> +#define DM_EMAC_B_FREE_CLK 23
> +#define DM_EMAC_PTP_FREE_CLK 24
> +#define DM_GPIO_DB_FREE_CLK 25
> +#define DM_SDMMC_FREE_CLK 26
> +#define DM_S2F_USER0_FREE_CLK 27
> +#define DM_S2F_USER1_FREE_CLK 28
> +#define DM_PSI_REF_FREE_CLK 29
> +
> +/* Gate clocks */
> +#define DM_MPU_CLK 30
> +#define DM_MPU_PERIPH_CLK 31
> +#define DM_L4_MAIN_CLK 32
> +#define DM_L4_MP_CLK 33
> +#define DM_L4_SP_CLK 34
> +#define DM_CS_AT_CLK 35
> +#define DM_CS_TRACE_CLK 36
> +#define DM_CS_PDBG_CLK 37
> +#define DM_CS_TIMER_CLK 38
> +#define DM_S2F_USER0_CLK 39
> +#define DM_EMAC0_CLK 40
> +#define DM_EMAC1_CLK 41
> +#define DM_EMAC2_CLK 42
> +#define DM_EMAC_PTP_CLK 43
> +#define DM_GPIO_DB_CLK 44
> +#define DM_NAND_CLK 45
> +#define DM_PSI_REF_CLK 46
> +#define DM_S2F_USER1_CLK 47
> +#define DM_SDMMC_CLK 48
> +#define DM_SPI_M_CLK 49
> +#define DM_USB_CLK 50
> +#define DM_NAND_X_CLK 51
> +#define DM_NAND_ECC_CLK 52
> +#define DM_NUM_CLKS 53
> +
> +#endif /* __DM_CLOCK_H */
> --
> 2.13.0
Regards
Ley Foon
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