[PATCH 1/3] board: ti: am65x: Set SERDES0 mux to PCIe to use USB 2.0 interface

[Aswath Govindraju]

It has been observed that setting SERDES0 lane mux to USB prevents USB 2.0
operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is used in
USB 2.0 only mode solves this issue. However, for USB3.0+2.0 operation this
issue is not present.

Implement this workaround by writing 1 to LANE_FUNC_SEL field in
CTRLMMR_SERDES0_CTRL register.

Signed-off-by: Aswath Govindraju <a-govindraju at ti.com>
---
 board/ti/am65x/evm.c | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 36063b11383d..4438f14e4ff1 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -38,6 +38,10 @@ enum {
 /* Max number of MAC addresses that are parsed/processed per daughter card */
 #define DAUGHTER_CARD_NO_OF_MAC_ADDR	8
 
+/* Regiter that controls the SERDES0 lane and clock assignment */
+#define CTRLMMR_SERDES0_CTRL    0x00104080
+#define PCIE_LANE0              0x1
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
@@ -312,6 +316,18 @@ static int probe_daughtercards(void)
 						      (uchar *)mac_addr[j]);
 		}
 
+		/*
+		 * It has been observed that setting SERDES0 lane mux to USB prevents USB
+		 * 2.0 operation on USB0. Setting SERDES0 lane mux to non-USB when USB0 is
+		 * used in USB 2.0 only mode solves this issue. For USB3.0+2.0 operation
+		 * this issue is not present.
+		 *
+		 * Implement this workaround by writing 1 to LANE_FUNC_SEL field in
+		 * CTRLMMR_SERDES0_CTRL register.
+		 */
+		if (!strncmp(ep.name, "SER-PCIE2LEVM", sizeof(ep.name)))
+			writel(PCIE_LANE0, CTRLMMR_SERDES0_CTRL);
+
 		/* Skip if no overlays are to be added */
 		if (!strlen(cards[i].dtbo_name))
 			continue;
-- 
2.17.1