[RESEND v2 15/22] arm: socfpga: dm: Add clock manager for Diamond Mesa

[Tan, Ley Foon]

> -----Original Message-----
> From: Lim, Elly Siew Chin <elly.siew.chin.lim at intel.com>
> Sent: Tuesday, November 10, 2020 2:45 PM
> To: u-boot at lists.denx.de
> Cc: Marek Vasut <marex at denx.de>; Tan, Ley Foon
> <ley.foon.tan at intel.com>; See, Chin Liang <chin.liang.see at intel.com>;
> Simon Goldschmidt <simon.k.r.goldschmidt at gmail.com>; Chee, Tien Fong
> <tien.fong.chee at intel.com>; Westergreen, Dalon
> <dalon.westergreen at intel.com>; Simon Glass <sjg at chromium.org>; Gan,
> Yau Wai <yau.wai.gan at intel.com>; Lim, Elly Siew Chin
> <elly.siew.chin.lim at intel.com>
> Subject: [RESEND v2 15/22] arm: socfpga: dm: Add clock manager for
> Diamond Mesa
> 
> Add clock manager for Diamond Mesa.
> 
> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim at intel.com>
> ---
>  arch/arm/mach-socfpga/clock_manager_dm.c           | 79
> ++++++++++++++++++++++
>  arch/arm/mach-socfpga/include/mach/clock_manager.h |  2 +
>  .../mach-socfpga/include/mach/clock_manager_dm.h   | 14 ++++
>  3 files changed, 95 insertions(+)
>  create mode 100644 arch/arm/mach-socfpga/clock_manager_dm.c
>  create mode 100644 arch/arm/mach-
> socfpga/include/mach/clock_manager_dm.h
> 
> diff --git a/arch/arm/mach-socfpga/clock_manager_dm.c
> b/arch/arm/mach-socfpga/clock_manager_dm.c
> new file mode 100644
> index 0000000000..cdf096cd8b
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/clock_manager_dm.c
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2020 Intel Corporation <www.intel.com>
> + *
> + */
> +
> +#include <clk.h>
> +#include <common.h>
> +#include <dm.h>
> +#include <malloc.h>
> +#include <asm/arch/clock_manager.h>
> +#include <asm/arch/system_manager.h>
> +#include <asm/io.h>
> +#include <dt-bindings/clock/dm-clock.h>
Try to sort alphanumerical order.


[...]

> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> index 0f0cb230fa..a164f47bda 100644
> --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
> @@ -26,6 +26,8 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
>  #include <asm/arch/clock_manager_s10.h>  #elif
> defined(CONFIG_TARGET_SOCFPGA_AGILEX)
>  #include <asm/arch/clock_manager_agilex.h>
> +#elif defined(CONFIG_TARGET_SOCFPGA_DM) #include
> +<asm/arch/clock_manager_dm.h>
>  #endif
> 
>  #endif /* _CLOCK_MANAGER_H_ */
> diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
> b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
> new file mode 100644
> index 0000000000..a355fda692
> --- /dev/null
> +++ b/arch/arm/mach-socfpga/include/mach/clock_manager_dm.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2020 Intel Corporation <www.intel.com>  */
> +
> +#ifndef _CLOCK_MANAGER_DM_
> +#define _CLOCK_MANAGER_DM_
> +
> +unsigned long cm_get_mpu_clk_hz(void);
This can move to clock_manager.h, since all devices have this.


Regards
Ley Foon