[PATCH 39/40] WIP: Bring in some header files from tianocore
Simon Glass
sjg at chromium.org
Wed Dec 1 17:03:13 CET 2021
These header files presumably duplicate things already in the U-Boot
devicetree. For now, bring them in to get the ASL code to build.
This needs to be sorted out.
Signed-off-by: Simon Glass <sjg at chromium.org>
---
.../mach-bcm283x/include/mach/acpi/bcm2711.h | 93 ++++++++
.../mach-bcm283x/include/mach/acpi/bcm2836.h | 124 +++++++++++
.../include/mach/acpi/bcm2836_gpio.h | 85 ++++++++
.../include/mach/acpi/bcm2836_gpu.h | 48 +++++
.../include/mach/acpi/bcm2836_pwm.h | 34 +++
.../include/mach/acpi/bcm2836_sdhost.h | 90 ++++++++
.../include/mach/acpi/bcm2836_sdio.h | 203 ++++++++++++++++++
7 files changed, 677 insertions(+)
create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h
create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h
create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h
create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h
create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h
create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h
create mode 100644 arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h
new file mode 100644
index 00000000000..dd0874280ef
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2711.h
@@ -0,0 +1,93 @@
+/** @file
+ *
+ * Copyright (c) 2019, Jeremy Linton
+ * Copyright (c) 2019, Pete Batard <pete at akeo.ie>.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef BCM2711_H__
+#define BCM2711_H__
+
+#define BCM2711_SOC_REGISTERS (FixedPcdGet64 (PcdBcm27xxRegistersAddress))
+#define BCM2711_SOC_REGISTER_LENGTH 0x02000000
+
+/* Generic PCI addresses */
+#define PCIE_TOP_OF_MEM_WIN (FixedPcdGet64 (PcdBcm27xxPciBusMmioAdr))
+#define PCIE_CPU_MMIO_WINDOW (FixedPcdGet64 (PcdBcm27xxPciCpuMmioAdr))
+#define PCIE_BRIDGE_MMIO_LEN (FixedPcdGet32 (PcdBcm27xxPciBusMmioLen))
+
+/* PCI root bridge control registers location */
+#define PCIE_REG_BASE (FixedPcdGet32 (PcdBcm27xxPciRegBase))
+#define PCIE_REG_LIMIT 0x9310
+
+/* PCI root bridge control registers */
+#define BRCM_PCIE_CAP_REGS 0x00ac /* Offset to ecam like range for root port */
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
+#define BRCM_PCIE_CLASS 0x043c
+#define PCIE_MISC_MISC_CTRL 0x4008
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
+#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
+#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
+#define PCIE_MISC_PCIE_STATUS 0x4068
+#define PCIE_MISC_REVISION 0x406c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
+
+#define PCIE_INTR2_CPU_STATUS 0x4300
+#define PCIE_INTR2_CPU_SET 0x4304
+#define PCIE_INTR2_CPU_CLR 0x4308
+#define PCIE_INTR2_CPU_MASK_STATUS 0x430c
+#define PCIE_INTR2_CPU_MASK_SET 0x4310
+#define PCIE_INTR2_CPU_MASK_CLR 0x4314
+
+#define PCIE_RGR1_SW_INIT_1 0x9210
+#define PCIE_EXT_CFG_INDEX 0x9000
+/* A small window pointing at the ECAM of the device selected by CFG_INDEX */
+#define PCIE_EXT_CFG_DATA 0x8000
+
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
+#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
+#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_RGR1_SW_INIT_1_INIT_MASK 0x2
+#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
+
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_MASK_BITS 0xc
+
+
+#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
+
+#define BURST_SIZE_128 0
+#define BURST_SIZE_256 1
+#define BURST_SIZE_512 2
+
+#define GENET_BASE_ADDRESS FixedPcdGet64 (PcdBcmGenetRegistersAddress)
+#define GENET_LENGTH 0x00010000
+
+#define THERM_SENSOR 0xfd5d2200
+
+#define ID_CHIPREV 0xfc404000
+
+#endif /* BCM2711_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h
new file mode 100644
index 00000000000..db0fe0262a6
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836.h
@@ -0,0 +1,124 @@
+/** @file
+ *
+ * Copyright (c) 2019, ARM Limited. All rights reserved.
+ * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin at gmail.com>
+ * Copyright (c) 2016, Linaro Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#ifndef __BCM2836_H__
+#define __BCM2836_H__
+
+/*
+ * Both "core" and SoC perpherals (1M each).
+ */
+#define BCM2836_SOC_REGISTERS (FixedPcdGet64 (PcdBcm283xRegistersAddress))
+#define BCM2836_SOC_REGISTER_LENGTH 0x02000000
+
+/*
+ * Offset between the CPU's view and the VC's view of system memory.
+ */
+#define BCM2836_DMA_DEVICE_OFFSET 0xc0000000
+
+/* watchdog constants */
+#define BCM2836_WDOG_OFFSET 0x00100000
+#define BCM2836_WDOG_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_WDOG_OFFSET)
+#define BCM2836_WDOG_PASSWORD 0x5a000000
+#define BCM2836_WDOG_RSTC_OFFSET 0x0000001c
+#define BCM2836_WDOG_WDOG_OFFSET 0x00000024
+#define BCM2836_WDOG_RSTC_WRCFG_MASK 0x00000030
+#define BCM2836_WDOG_RSTC_WRCFG_FULL_RESET 0x00000020
+
+/* clock manager constants */
+#define BCM2836_CM_OFFSET 0x00101000
+#define BCM2836_CM_BASE (BCM2836_SOC_REGISTERS + BCM2836_CM_OFFSET)
+#define BCM2836_CM_GEN_CLOCK_CONTROL 0x0000
+#define BCM2836_CM_GEN_CLOCK_DIVISOR 0x0004
+#define BCM2836_CM_VPU_CLOCK_CONTROL 0x0008
+#define BCM2836_CM_VPU_CLOCK_DIVISOR 0x000c
+#define BCM2836_CM_SYSTEM_CLOCK_CONTROL 0x0010
+#define BCM2836_CM_SYSTEM_CLOCK_DIVISOR 0x0014
+#define BCM2836_CM_H264_CLOCK_CONTROL 0x0028
+#define BCM2836_CM_H264_CLOCK_DIVISOR 0x002c
+#define BCM2836_CM_PWM_CLOCK_CONTROL 0x00a0
+#define BCM2836_CM_PWM_CLOCK_DIVISOR 0x00a4
+#define BCM2836_CM_UART_CLOCK_CONTROL 0x00f0
+#define BCM2836_CM_UART_CLOCK_DIVISOR 0x00f4
+#define BCM2836_CM_SDC_CLOCK_CONTROL 0x01a8
+#define BCM2836_CM_SDC_CLOCK_DIVISOR 0x01ac
+#define BCM2836_CM_ARM_CLOCK_CONTROL 0x01b0
+#define BCM2836_CM_ARM_CLOCK_DIVISOR 0x01b4
+#define BCM2836_CM_EMMC_CLOCK_CONTROL 0x01c0
+#define BCM2836_CM_EMMC_CLOCK_DIVISOR 0x01c4
+
+/* mailbox interface constants */
+#define BCM2836_MBOX_OFFSET 0x0000b880
+#define BCM2836_MBOX_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MBOX_OFFSET)
+#define BCM2836_MBOX_LENGTH 0x00000024
+#define BCM2836_MBOX_READ_OFFSET 0x00000000
+#define BCM2836_MBOX_STATUS_OFFSET 0x00000018
+#define BCM2836_MBOX_CONFIG_OFFSET 0x0000001c
+#define BCM2836_MBOX_WRITE_OFFSET 0x00000020
+
+#define BCM2836_MBOX_STATUS_FULL 0x1f
+#define BCM2836_MBOX_STATUS_EMPTY 0x1e
+
+#define BCM2836_MBOX_NUM_CHANNELS 16
+
+/* interrupt controller constants */
+#define BCM2836_INTC_TIMER_CONTROL_OFFSET 0x00000040
+#define BCM2836_INTC_TIMER_PENDING_OFFSET 0x00000060
+
+/* usb constants */
+#define BCM2836_USB_OFFSET 0x00980000
+#define BCM2836_USB_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_USB_OFFSET)
+#define BCM2836_USB_LENGTH 0x00010000
+
+/* serial based protocol constants */
+#define BCM2836_PL011_UART_OFFSET 0x00201000
+#define BCM2836_PL011_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PL011_UART_OFFSET)
+#define BCM2836_PL011_UART_LENGTH 0x00001000
+
+#define BCM2836_MINI_UART_OFFSET 0x00215000
+#define BCM2836_MINI_UART_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_MINI_UART_OFFSET)
+#define BCM2836_MINI_UART_LENGTH 0x00000070
+
+#define BCM2836_I2C0_OFFSET 0x00205000
+#define BCM2836_I2C0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C0_OFFSET)
+#define BCM2836_I2C0_LENGTH 0x00000020
+
+#define BCM2836_I2C1_OFFSET 0x00804000
+#define BCM2836_I2C1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C1_OFFSET)
+#define BCM2836_I2C1_LENGTH 0x00000020
+
+#define BCM2836_I2C2_OFFSET 0x00805000
+#define BCM2836_I2C2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_I2C2_OFFSET)
+#define BCM2836_I2C2_LENGTH 0x00000020
+
+#define BCM2836_SPI0_OFFSET 0x00204000
+#define BCM2836_SPI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI0_OFFSET)
+#define BCM2836_SPI0_LENGTH 0x00000020
+
+#define BCM2836_SPI1_OFFSET 0x00215080
+#define BCM2836_SPI1_LENGTH 0x00000040
+#define BCM2836_SPI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI1_OFFSET)
+
+#define BCM2836_SPI2_OFFSET 0x002150C0
+#define BCM2836_SPI2_LENGTH 0x00000040
+#define BCM2836_SPI2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_SPI2_OFFSET)
+
+/* dma constants */
+#define BCM2836_DMA0_OFFSET 0x00007000
+#define BCM2836_DMA0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA0_OFFSET)
+
+#define BCM2836_DMA15_OFFSET 0x00E05000
+#define BCM2836_DMA15_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA15_OFFSET)
+
+#define BCM2836_DMA_CTRL_OFFSET 0x00007FE0
+#define BCM2836_DMA_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_DMA_CTRL_OFFSET)
+
+#define BCM2836_DMA_CHANNEL_LENGTH 0x00000100
+
+#endif /*__BCM2836_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h
new file mode 100644
index 00000000000..a64cecaef3a
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpio.h
@@ -0,0 +1,85 @@
+/** @file
+ *
+ * Copyright (c) 2020, Pete Batard <pete at akeo.ie>
+ * Copyright (c) 2018, Andrei Warkentin <andrey.warkentin at gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_GPIO_H__
+#define __BCM2836_GPIO_H__
+
+#define GPIO_OFFSET 0x00200000
+#define GPIO_BASE_ADDRESS (BCM2836_SOC_REGISTERS + GPIO_OFFSET)
+#define GPIO_LENGTH 0x000000B4
+
+#define GPIO_GPFSEL0 (GPIO_BASE_ADDRESS + 0x00)
+#define GPIO_GPFSEL1 (GPIO_BASE_ADDRESS + 0x04)
+#define GPIO_GPFSEL2 (GPIO_BASE_ADDRESS + 0x08)
+#define GPIO_GPFSEL3 (GPIO_BASE_ADDRESS + 0x0C)
+#define GPIO_GPFSEL4 (GPIO_BASE_ADDRESS + 0x10)
+#define GPIO_GPFSEL5 (GPIO_BASE_ADDRESS + 0x14)
+
+#define GPIO_GPSET0 (GPIO_BASE_ADDRESS + 0x1C)
+#define GPIO_GPSET1 (GPIO_BASE_ADDRESS + 0x20)
+
+#define GPIO_GPCLR0 (GPIO_BASE_ADDRESS + 0x28)
+#define GPIO_GPCLR1 (GPIO_BASE_ADDRESS + 0x2C)
+
+#define GPIO_GPLEV0 (GPIO_BASE_ADDRESS + 0x34)
+#define GPIO_GPLEV1 (GPIO_BASE_ADDRESS + 0x38)
+
+#define GPIO_GPEDS0 (GPIO_BASE_ADDRESS + 0x40)
+#define GPIO_GPEDS1 (GPIO_BASE_ADDRESS + 0x44)
+
+#define GPIO_GPREN0 (GPIO_BASE_ADDRESS + 0x4C)
+#define GPIO_GPREN1 (GPIO_BASE_ADDRESS + 0x50)
+
+#define GPIO_GPFEN0 (GPIO_BASE_ADDRESS + 0x58)
+#define GPIO_GPFEN1 (GPIO_BASE_ADDRESS + 0x5C)
+
+#define GPIO_GPHEN0 (GPIO_BASE_ADDRESS + 0x64)
+#define GPIO_GPHEN1 (GPIO_BASE_ADDRESS + 0x68)
+
+#define GPIO_GPLEN0 (GPIO_BASE_ADDRESS + 0x70)
+#define GPIO_GPLEN1 (GPIO_BASE_ADDRESS + 0x74)
+
+#define GPIO_GPAREN0 (GPIO_BASE_ADDRESS + 0x7C)
+#define GPIO_GPAREN1 (GPIO_BASE_ADDRESS + 0x80)
+
+#define GPIO_GPAFEN0 (GPIO_BASE_ADDRESS + 0x88)
+#define GPIO_GPAFEN1 (GPIO_BASE_ADDRESS + 0x8C)
+
+#define GPIO_GPPUD (GPIO_BASE_ADDRESS + 0x94)
+#define GPIO_GPPUDCLK0 (GPIO_BASE_ADDRESS + 0x98)
+#define GPIO_GPPUDCLK1 (GPIO_BASE_ADDRESS + 0x9C)
+
+#define GPIO_GPPUPPDN0 (GPIO_BASE_ADDRESS + 0xE4)
+#define GPIO_GPPUPPDN1 (GPIO_BASE_ADDRESS + 0xE8)
+#define GPIO_GPPUPPDN2 (GPIO_BASE_ADDRESS + 0xEC)
+#define GPIO_GPPUPPDN3 (GPIO_BASE_ADDRESS + 0xF0)
+
+#define GPIO_FSEL_INPUT 0x0
+#define GPIO_FSEL_OUTPUT 0x1
+#define GPIO_FSEL_ALT0 0x4
+#define GPIO_FSEL_ALT1 0x5
+#define GPIO_FSEL_ALT2 0x6
+#define GPIO_FSEL_ALT3 0x7
+#define GPIO_FSEL_ALT4 0x3
+#define GPIO_FSEL_ALT5 0x2
+
+#define GPIO_FSEL_PINS_PER_REGISTER 10
+#define GPIO_FSEL_BITS_PER_PIN 3
+#define GPIO_FSEL_MASK ((1 << GPIO_FSEL_BITS_PER_PIN) - 1)
+
+#define GPIO_PINS 54
+
+#define GPIO_PULL_NONE 0x00
+#define GPIO_PULL_DOWN 0x01
+#define GPIO_PULL_UP 0x02
+
+#endif /* __BCM2836_GPIO_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h
new file mode 100644
index 00000000000..49be0206d40
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_gpu.h
@@ -0,0 +1,48 @@
+/** @file
+ *
+ * Copyright (c) 2020, Pete Batard <pete at akeo.ie>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_GPU_H__
+#define __BCM2836_GPU_H__
+
+/* VideoCore constants */
+
+#define BCM2836_VCHIQ_OFFSET 0x0000B840
+#define BCM2836_VCHIQ_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_VCHIQ_OFFSET)
+#define BCM2836_VCHIQ_LENGTH 0x00000010
+
+#define BCM2836_V3D_BUS_OFFSET 0x00C00000
+#define BCM2836_V3D_BUS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_V3D_BUS_OFFSET)
+#define BCM2836_V3D_BUS_LENGTH 0x00001000
+
+#define BCM2836_HVS_OFFSET 0x00400000
+#define BCM2836_HVS_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HVS_OFFSET)
+#define BCM2836_HVS_LENGTH 0x00006000
+
+#define BCM2836_PV0_OFFSET 0x00206000
+#define BCM2836_PV0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV0_OFFSET)
+#define BCM2836_PV0_LENGTH 0x00000100
+
+#define BCM2836_PV1_OFFSET 0x00207000
+#define BCM2836_PV1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV1_OFFSET)
+#define BCM2836_PV1_LENGTH 0x00000100
+
+#define BCM2836_PV2_OFFSET 0x00807000
+#define BCM2836_PV2_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PV2_OFFSET)
+#define BCM2836_PV2_LENGTH 0x00000100
+
+#define BCM2836_HDMI0_OFFSET 0x00902000
+#define BCM2836_HDMI0_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI0_OFFSET)
+#define BCM2836_HDMI0_LENGTH 0x00000600
+
+#define BCM2836_HDMI1_OFFSET 0x00808000
+#define BCM2836_HDMI1_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_HDMI1_OFFSET)
+#define BCM2836_HDMI1_LENGTH 0x00000100
+
+#endif /* __BCM2836_MISC_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h
new file mode 100644
index 00000000000..12050f34b17
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_pwm.h
@@ -0,0 +1,34 @@
+/** @file
+ *
+ * Copyright (c) 2020, Pete Batard <pete at akeo.ie>
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_PWM_H__
+#define __BCM2836_PWM_H__
+
+/* PWM controller constants */
+
+#define BCM2836_PWM_DMA_OFFSET 0x00007B00
+#define BCM2836_PWM_DMA_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_DMA_OFFSET)
+#define BCM2836_PWM_DMA_LENGTH 0x00000100
+
+#define BCM2836_PWM_CLK_OFFSET 0x001010A0
+#define BCM2836_PWM_CLK_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CLK_OFFSET)
+#define BCM2836_PWM_CLK_LENGTH 0x00000008
+
+#define BCM2836_PWM_CTRL_OFFSET 0x0020C000
+#define BCM2836_PWM_CTRL_BASE_ADDRESS (BCM2836_SOC_REGISTERS + BCM2836_PWM_CTRL_OFFSET)
+#define BCM2836_PWM_CTRL_LENGTH 0x00000028
+
+#define BCM2836_PWM_BUS_BASE_ADDRESS 0x7E20C000
+#define BCM2836_PWM_BUS_LENGTH 0x00000028
+
+#define BCM2836_PWM_CTRL_UNCACHED_BASE_ADDRESS 0xFF20C000
+#define BCM2836_PWM_CTRL_UNCACHED_LENGTH 0x00000028
+
+#endif /* __BCM2836_PWM_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h
new file mode 100644
index 00000000000..1c62d668a48
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdhost.h
@@ -0,0 +1,90 @@
+/** @file
+ *
+ * Copyright (c) 2017, Andrei Warkentin <andrey.warkentin at gmail.com>
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_SDHOST_H__
+#define __BCM2836_SDHOST_H__
+
+#define SDHOST_OFFSET 0x00202000
+#define SDHOST_BASE_ADDRESS (BCM2836_SOC_REGISTERS + SDHOST_OFFSET)
+#define SDHOST_LENGTH 0x00000100
+#define SDHOST_REG(X) (SDHOST_BASE_ADDRESS + (X))
+#define SDHOST_CMD SDHOST_REG(0x0)
+#define SDHOST_ARG SDHOST_REG(0x4)
+#define SDHOST_TOUT SDHOST_REG(0x8)
+#define SDHOST_CDIV SDHOST_REG(0xC)
+#define SDHOST_RSP0 SDHOST_REG(0x10) // [31:0]
+#define SDHOST_RSP1 SDHOST_REG(0x14) // [63:32]
+#define SDHOST_RSP2 SDHOST_REG(0x18) // [95:64]
+#define SDHOST_RSP3 SDHOST_REG(0x1C) // [127:96]
+#define SDHOST_HSTS SDHOST_REG(0x20)
+#define SDHOST_VDD SDHOST_REG(0x30)
+#define SDHOST_EDM SDHOST_REG(0x34)
+#define SDHOST_HCFG SDHOST_REG(0x38)
+#define SDHOST_HBCT SDHOST_REG(0x3C)
+#define SDHOST_DATA SDHOST_REG(0x40)
+#define SDHOST_HBLC SDHOST_REG(0x50)
+
+//
+// CMD
+//
+#define SDHOST_CMD_READ_CMD BIT6
+#define SDHOST_CMD_WRITE_CMD BIT7
+#define SDHOST_CMD_RESPONSE_CMD_LONG_RESP BIT9
+#define SDHOST_CMD_RESPONSE_CMD_NO_RESP BIT10
+#define SDHOST_CMD_BUSY_CMD BIT11
+#define SDHOST_CMD_FAIL_FLAG BIT14
+#define SDHOST_CMD_NEW_FLAG BIT15
+
+//
+// VDD
+//
+#define SDHOST_VDD_POWER_ON BIT0
+
+//
+// HSTS
+//
+#define SDHOST_HSTS_CLEAR 0x7F8
+#define SDHOST_HSTS_BLOCK_IRPT BIT9
+#define SDHOST_HSTS_REW_TIME_OUT BIT7
+#define SDHOST_HSTS_CMD_TIME_OUT BIT6
+#define SDHOST_HSTS_CRC16_ERROR BIT5
+#define SDHOST_HSTS_CRC7_ERROR BIT4
+#define SDHOST_HSTS_FIFO_ERROR BIT3
+#define SDHOST_HSTS_DATA_FLAG BIT0
+
+#define SDHOST_HSTS_TIMOUT_ERROR (SDHOST_HSTS_CMD_TIME_OUT | SDHOST_HSTS_REW_TIME_OUT)
+#define SDHOST_HSTS_TRANSFER_ERROR (SDHOST_HSTS_FIFO_ERROR | SDHOST_HSTS_CRC7_ERROR | SDHOST_HSTS_CRC16_ERROR)
+#define SDHOST_HSTS_ERROR (SDHOST_HSTS_TIMOUT_ERROR | SDHOST_HSTS_TRANSFER_ERROR)
+
+//
+// HCFG
+//
+#define SDHOST_HCFG_SLOW_CARD BIT3
+#define SDHOST_HCFG_WIDE_EXT_BUS BIT2
+#define SDHOST_HCFG_WIDE_INT_BUS BIT1
+#define SDHOST_HCFG_DATA_IRPT_EN BIT4
+#define SDHOST_HCFG_BLOCK_IRPT_EN BIT8
+#define SDHOST_HCFG_BUSY_IRPT_EN BIT10
+
+//
+// EDM
+//
+#define SDHOST_EDM_FIFO_CLEAR BIT21
+#define SDHOST_EDM_WRITE_THRESHOLD_SHIFT 9
+#define SDHOST_EDM_READ_THRESHOLD_SHIFT 14
+#define SDHOST_EDM_THRESHOLD_MASK 0x1F
+#define SDHOST_EDM_READ_THRESHOLD(X) ((X) << SDHOST_EDM_READ_THRESHOLD_SHIFT)
+#define SDHOST_EDM_WRITE_THRESHOLD(X) ((X) << SDHOST_EDM_WRITE_THRESHOLD_SHIFT)
+
+#define CMD8_SD_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
+#define CMD8_MMC_ARG (0)
+
+#endif /*__BCM2836_SDHOST_H__ */
diff --git a/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h
new file mode 100644
index 00000000000..aba422b9751
--- /dev/null
+++ b/arch/arm/mach-bcm283x/include/mach/acpi/bcm2836_sdio.h
@@ -0,0 +1,203 @@
+/** @file
+ *
+ * Copyright (c) Microsoft Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <asm/arch/acpi/bcm2836.h>
+
+#ifndef __BCM2836_SDIO_H__
+#define __BCM2836_SDIO_H__
+
+// MMC/SD/SDIO1 register definitions.
+#define MMCHS1_OFFSET 0x00300000
+#define MMCHS2_OFFSET 0x00340000
+#define MMCHS1_BASE (BCM2836_SOC_REGISTERS + MMCHS1_OFFSET)
+#define MMCHS2_BASE (BCM2836_SOC_REGISTERS + MMCHS2_OFFSET)
+#define MMCHS1_LENGTH 0x00000100
+#define MMCHS2_LENGTH 0x00000100
+
+#define MMCHS_BLK (mMmcHsBase + 0x4)
+#define BLEN_512BYTES (0x200UL << 0)
+
+#define MMCHS_ARG (mMmcHsBase + 0x8)
+
+#define MMCHS_CMD (mMmcHsBase + 0xC)
+#define BCE_ENABLE BIT1
+#define DDIR_READ BIT4
+#define DDIR_WRITE (0x0UL << 4)
+#define MSBS_SGLEBLK (0x0UL << 5)
+#define MSBS_MULTBLK BIT5
+#define RSP_TYPE_MASK (0x3UL << 16)
+#define RSP_TYPE_136BITS BIT16
+#define RSP_TYPE_48BITS (0x2UL << 16)
+#define RSP_TYPE_48BUSY (0x3UL << 16)
+#define CCCE_ENABLE BIT19
+#define CICE_ENABLE BIT20
+#define DP_ENABLE BIT21
+
+#define CMD_TYPE_NORMAL 0
+#define CMD_TYPE_ABORT 3
+#define TYPE(CMD_TYPE) (((CMD_TYPE) & 0x3) << 22)
+#define _INDX(CMD_INDX) ((CMD_INDX & 0x3F) << 24)
+#define MMC_CMD_NUM(CMD) (((CMD) >> 24) & 0x3F)
+#define INDX(CMD_INDX) (TYPE(CMD_TYPE_NORMAL) | _INDX(CMD_INDX))
+#define INDX_ABORT(CMD_INDX) (TYPE(CMD_TYPE_ABORT) | _INDX(CMD_INDX))
+
+#define MMCHS_RSP10 (mMmcHsBase + 0x10)
+#define MMCHS_RSP32 (mMmcHsBase + 0x14)
+#define MMCHS_RSP54 (mMmcHsBase + 0x18)
+#define MMCHS_RSP76 (mMmcHsBase + 0x1C)
+#define MMCHS_DATA (mMmcHsBase + 0x20)
+
+#define MMCHS_PRES_STATE (mMmcHsBase + 0x24)
+#define CMDI_MASK BIT0
+#define CMDI_ALLOWED (0x0UL << 0)
+#define CMDI_NOT_ALLOWED BIT0
+#define DATI_MASK BIT1
+#define DATI_ALLOWED (0x0UL << 1)
+#define DATI_NOT_ALLOWED BIT1
+#define WRITE_PROTECT_OFF BIT19
+
+#define MMCHS_HCTL (mMmcHsBase + 0x28)
+#define DTW_1_BIT (0x0UL << 1)
+#define DTW_4_BIT BIT1
+#define SDBP_MASK BIT8
+#define SDBP_OFF (0x0UL << 8)
+#define SDBP_ON BIT8
+#define SDVS_MASK (0x7UL << 9)
+#define SDVS_1_8_V (0x5UL << 9)
+#define SDVS_3_0_V (0x6UL << 9)
+#define SDVS_3_3_V (0x7UL << 9)
+#define IWE BIT24
+
+#define MMCHS_SYSCTL (mMmcHsBase + 0x2C)
+#define ICE BIT0
+#define ICS_MASK BIT1
+#define ICS BIT1
+#define CEN BIT2
+#define CLKD_MASK (0x3FFUL << 6)
+#define CLKD_80KHZ (0x258UL) //(96*1000/80)/2
+#define CLKD_400KHZ (0xF0UL)
+#define CLKD_12500KHZ (0x200UL)
+#define DTO_MASK (0xFUL << 16)
+#define DTO_VAL (0xEUL << 16)
+#define SRA BIT24
+#define SRC_MASK BIT25
+#define SRC BIT25
+#define SRD BIT26
+
+#define MMCHS_INT_STAT (mMmcHsBase + 0x30)
+#define CC BIT0
+#define TC BIT1
+#define BWR BIT4
+#define BRR BIT5
+#define CARD_INS BIT6
+#define ERRI BIT15
+#define CTO BIT16
+#define DTO BIT20
+#define DCRC BIT21
+#define DEB BIT22
+
+#define MMCHS_IE (mMmcHsBase + 0x34)
+#define CC_EN BIT0
+#define TC_EN BIT1
+#define BWR_EN BIT4
+#define BRR_EN BIT5
+#define CTO_EN BIT16
+#define CCRC_EN BIT17
+#define CEB_EN BIT18
+#define CIE_EN BIT19
+#define DTO_EN BIT20
+#define DCRC_EN BIT21
+#define DEB_EN BIT22
+#define CERR_EN BIT28
+#define BADA_EN BIT29
+#define ALL_EN 0xFFFFFFFF
+
+#define MMCHS_ISE (mMmcHsBase + 0x38)
+#define CC_SIGEN BIT0
+#define TC_SIGEN BIT1
+#define BWR_SIGEN BIT4
+#define BRR_SIGEN BIT5
+#define CTO_SIGEN BIT16
+#define CCRC_SIGEN BIT17
+#define CEB_SIGEN BIT18
+#define CIE_SIGEN BIT19
+#define DTO_SIGEN BIT20
+#define DCRC_SIGEN BIT21
+#define DEB_SIGEN BIT22
+#define CERR_SIGEN BIT28
+#define BADA_SIGEN BIT29
+
+#define MMCHS_AC12 (mMmcHsBase + 0x3C)
+#define MMCHS_HC2R (mMmcHsBase + 0x3E)
+
+#define MMCHS_CAPA (mMmcHsBase + 0x40)
+#define VS30 BIT25
+#define VS18 BIT26
+
+#define MMCHS_CUR_CAPA (mMmcHsBase + 0x48)
+#define MMCHS_REV (mMmcHsBase + 0xFC)
+
+#define BLOCK_COUNT_SHIFT 16
+#define RCA_SHIFT 16
+
+#define CMD_R1 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE)
+#define CMD_R1B (RSP_TYPE_48BUSY | CCCE_ENABLE | CICE_ENABLE)
+#define CMD_R2 (RSP_TYPE_136BITS | CCCE_ENABLE)
+#define CMD_R3 (RSP_TYPE_48BITS)
+#define CMD_R6 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE)
+#define CMD_R7 (RSP_TYPE_48BITS | CCCE_ENABLE | CICE_ENABLE)
+
+#define CMD_R1_ADTC (CMD_R1 | DP_ENABLE)
+#define CMD_R1_ADTC_READ (CMD_R1_ADTC | DDIR_READ)
+#define CMD_R1_ADTC_WRITE (CMD_R1_ADTC | DDIR_WRITE)
+
+#define CMD0 (INDX(0)) // Go idle
+#define CMD1 (INDX(1) | CMD_R3) // MMC: Send Op Cond
+#define CMD2 (INDX(2) | CMD_R2) // Send CID
+#define CMD3 (INDX(3) | CMD_R6) // Set Relative Addr
+#define CMD4 (INDX(4)) // Set DSR
+#define CMD5 (INDX(5) | CMD_R1B) // SDIO: Sleep/Awake
+#define CMD6 (INDX(6) | CMD_R1_ADTC_READ) // Switch
+#define CMD7 (INDX(7) | CMD_R1B) // Select/Deselect
+#define CMD8_SD (INDX(8) | CMD_R7) // Send If Cond
+#define CMD8_SD_ARG (0x0UL << 12 | BIT8 | 0xCEUL << 0)
+#define CMD8_MMC (INDX(8) | CMD_R1_ADTC_READ) // Send Ext Csd
+#define CMD8_MMC_ARG (0)
+#define CMD9 (INDX(9) | CMD_R2) // Send CSD
+#define CMD10 (INDX(10) | CMD_R2) // Send CID
+#define CMD11 (INDX(11) | CMD_R1) // Voltage Switch
+#define CMD12 (INDX_ABORT(12) | CMD_R1B) // Stop Transmission
+#define CMD13 (INDX(13) | CMD_R1) // Send Status
+#define CMD15 (INDX(15)) // Go inactive state
+#define CMD16 (INDX(16) | CMD_R1) // Set Blocklen
+#define CMD17 (INDX(17) | CMD_R1_ADTC_READ) // Read Single Block
+#define CMD18 (INDX(18) | CMD_R1_ADTC_READ | MSBS_MULTBLK) // Read Multiple Blocks
+#define CMD19 (INDX(19) | CMD_R1_ADTC_READ) // SD: Send Tuning Block (64 bytes)
+#define CMD20 (INDX(20) | CMD_R1B) // SD: Speed Class Control
+#define CMD23 (INDX(23) | CMD_R1) // Set Block Count for CMD18 and CMD25
+#define CMD24 (INDX(24) | CMD_R1_ADTC_WRITE) // Write Block
+#define CMD25 (INDX(25) | CMD_R1_ADTC_WRITE | MSBS_MULTBLK) // Write Multiple Blocks
+#define CMD55 (INDX(55) | CMD_R1) // App Cmd
+
+#define ACMD6 (INDX(6) | CMD_R1) // Set Bus Width
+#define ACMD22 (INDX(22) | CMD_R1_ADTC_READ) // SEND_NUM_WR_BLOCKS
+#define ACMD41 (INDX(41) | CMD_R3) // Send Op Cond
+#define ACMD51 (INDX(51) | CMD_R1_ADTC_READ) // Send SCR
+
+// User-friendly command names
+#define CMD_IO_SEND_OP_COND CMD5
+#define CMD_SEND_CSD CMD9 // CSD: Card-Specific Data
+#define CMD_STOP_TRANSMISSION CMD12
+#define CMD_SEND_STATUS CMD13
+#define CMD_READ_SINGLE_BLOCK CMD17
+#define CMD_READ_MULTIPLE_BLOCK CMD18
+#define CMD_SET_BLOCK_COUNT CMD23
+#define CMD_WRITE_SINGLE_BLOCK CMD24
+#define CMD_WRITE_MULTIPLE_BLOCK CMD25
+
+#endif /* __BCM2836_SDIO_H__ */
--
2.34.0.rc2.393.gf8c9666880-goog
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