[PATCH] mtd: cqspi: Wait for transfer completion

[Jagan Teki]

Hi Marek,

On Tue, Sep 14, 2021 at 8:52 AM Marek Vasut <marex at denx.de> wrote:
>
> Wait for the read/write transfer finish bit get actually cleared,
> this does not happen immediately on at least SoCFPGA Gen5.
>
> Signed-off-by: Marek Vasut <marex at denx.de>
> Cc: Jagan Teki <jagan at amarulasolutions.com>
> Cc: Vignesh R <vigneshr at ti.com>
> Cc: Pratyush Yadav <p.yadav at ti.com>
> ---
>  drivers/spi/cadence_qspi_apb.c | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
>
> diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c
> index 429ee335db6..2cdf4c9c9f8 100644
> --- a/drivers/spi/cadence_qspi_apb.c
> +++ b/drivers/spi/cadence_qspi_apb.c
> @@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat,
>         writel(CQSPI_REG_INDIRECTRD_DONE,
>                plat->regbase + CQSPI_REG_INDIRECTRD);
>
> +       /* Check indirect done status */
> +       ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD,
> +                               CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0);
> +       if (ret) {
> +               printf("Indirect read clear completion error (%i)\n", ret);
> +               goto failrd;
> +       }
> +
>         return 0;
>
>  failrd:
> @@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat,
>         /* Clear indirect completion status */
>         writel(CQSPI_REG_INDIRECTWR_DONE,
>                plat->regbase + CQSPI_REG_INDIRECTWR);
> +
> +       /* Check indirect done status */
> +       ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR,
> +                               CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0);
> +       if (ret) {
> +               printf("Indirect write clear completion error (%i)\n", ret);
> +               goto failwr;
> +       }
> +

Does this patch to be part of the release?

Jagan.