Question/issues about i.MX6 DDR configuration

[Francesco Dolcini]

Hello Fabio and Michael,

On Thu, Dec 02, 2021 at 09:36:44PM +0100, Michael Nazzareno Trimarchi wrote:
> On Thu, Dec 2, 2021 at 9:14 PM Fabio Estevam <festevam at gmail.com> wrote:
> > On Thu, Dec 2, 2021 at 1:14 PM Francesco Dolcini
> > <francesco.dolcini at toradex.com> wrote:
> > > I'm a little bit puzzled at the moment, according to the iMX6 reference
> > > manual[4], 44.4.2 MMDC initialization, a specific sequence is required
> > > to be followed and this is implemented by the `mx6_dram_cfg()`[5]
> > > function, but according to what Fabio wrote the raw initialization of
> > > registers was just more reliable for mx6sabresd. Fabio, what was the
> > > reason?
> >
> > The mx6_ddr_sysinfo approach is more elegant, for sure.
> 
> The bootrom loads the dcd using some logic and you write the register
> in sequence.
> You don't respect the ddr initialization or this delay on MMDC
> according to 44.4.2.
> Is that not necessary?

This is my main doubt, is the bootrom loading the DCD using some logic
or it is really equivalent to the raw register writing we are doing in
SPL? I'm not thinking only at delays (if any), but the complete MMDC
initialization flow as documented in the reference manual.

> > It is just that I wanted to keep 100% in sync with the initialization
> > done by the NXP hardware team.

Thanks Fabio for the clarification.

Francesco