[PATCH v7 14/31] arm: highbank: Add devicetree files
Andre Przywara
andre.przywara at arm.com
Tue Dec 7 01:59:48 CET 2021
On Mon, 6 Dec 2021 17:11:52 -0700
Simon Glass <sjg at chromium.org> wrote:
> Sync these files, obtained from Linux v5.15.
Sorry, but this would be wrong.
How do you know which board it is? Highbank or Midway? We use the
same binary for both, and decide either by the DT nodes we find in DRAM
or by some autodetection (Cortex-A9 vs. Cortex-A15) if there are
differences. The memory size would possibly be wrong (it's a DIMM slot).
If you need *some* DT for build reasons, whatever, but at least go with
the empty stub.
And I still don't get this whole development argument: Why would
anyone need some random or partial DT sample in the U-Boot tree to do
development?
If people develop a driver, the document to code against is the
*binding* documentation, which describes what to expect from the DT
nodes. Then you *test* it against an actual tree, but on the actual
hardware, in which case you get the actual DTB, from the board.
If a developer needs to take a sneak peek into an actual DTB,
there are so many simple ways to do that: QEMU's dumpdtb, RPi's SD
card content, U-Boot's "fdt addr $fdtcontroladdr; fdt print", the
kernel's /sys/firmware/devicetree/base, ... When you port U-Boot to a
board, getting hands on the actual DT is probably the least of your
problems.
So why would we need some mostly wrong DTs in the U-Boot tree?
It seems to suggest that you can hack the DT to make things work, but
this sounds bonkers, as the real DTB comes from somewhere else (SPI
flash, SD card, generated based on command line), and patching U-Boot's
copy to make things work is just wishful thinking.
I can see the hacker's desire to play around with the DTB from time
to time (What happens if the GPIO is wrong? Can we deal with two
instances of the same device?), but for those experiments there are
plenty of ways to achieve this - and be it temporarily replacing the
empty DT stub. I just feel that bending the (board's) DT design ideas
for a hacker's pleasure is not justified.
Cheers,
Andre
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> Changes in v7:
> - Bring in files from Linux instead
>
> arch/arm/dts/Makefile | 2 +
> arch/arm/dts/ecx-common.dtsi | 231 +++++++++++++++++++++++++++++++++++
> arch/arm/dts/highbank.dts | 158 ++++++++++++++++++++++++
> configs/highbank_defconfig | 2 +-
> 4 files changed, 392 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/ecx-common.dtsi
> create mode 100644 arch/arm/dts/highbank.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 8bb15b96cc7..453e2fd1a98 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -871,6 +871,8 @@ dtb-$(CONFIG_MX7) += imx7d-sdb.dtb \
> dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-com.dtb \
> imx7ulp-evk.dtb
>
> +dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb
> +
> dtb-$(CONFIG_ARCH_IMX8) += \
> fsl-imx8qm-apalis.dtb \
> fsl-imx8qm-mek.dtb \
> diff --git a/arch/arm/dts/ecx-common.dtsi b/arch/arm/dts/ecx-common.dtsi
> new file mode 100644
> index 00000000000..57a028a6937
> --- /dev/null
> +++ b/arch/arm/dts/ecx-common.dtsi
> @@ -0,0 +1,231 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2011-2012 Calxeda, Inc.
> + */
> +
> +/ {
> + chosen {
> + bootargs = "console=ttyAMA0";
> + };
> +
> + psci {
> + compatible = "arm,psci";
> + method = "smc";
> + cpu_suspend = <0x84000002>;
> + cpu_off = <0x84000004>;
> + cpu_on = <0x84000006>;
> + };
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "simple-bus";
> + interrupt-parent = <&intc>;
> +
> + sata at ffe08000 {
> + compatible = "calxeda,hb-ahci";
> + reg = <0xffe08000 0x10000>;
> + interrupts = <0 83 4>;
> + dma-coherent;
> + calxeda,port-phys = < &combophy5 0>, <&combophy0 0>,
> + <&combophy0 1>, <&combophy0 2>,
> + <&combophy0 3>;
> + calxeda,sgpio-gpio =<&gpioh 5 1>, <&gpioh 6 1>,
> + <&gpioh 7 1>;
> + calxeda,led-order = <4 0 1 2 3>;
> + };
> +
> + sdhci at ffe0e000 {
> + compatible = "calxeda,hb-sdhci";
> + reg = <0xffe0e000 0x1000>;
> + interrupts = <0 90 4>;
> + clocks = <&eclk>;
> + status = "disabled";
> + };
> +
> + ipc at fff20000 {
> + compatible = "arm,pl320", "arm,primecell";
> + reg = <0xfff20000 0x1000>;
> + interrupts = <0 7 4>;
> + clocks = <&pclk>;
> + clock-names = "apb_pclk";
> + };
> +
> + gpioe: gpio at fff30000 {
> + #gpio-cells = <2>;
> + compatible = "arm,pl061", "arm,primecell";
> + gpio-controller;
> + reg = <0xfff30000 0x1000>;
> + interrupts = <0 14 4>;
> + clocks = <&pclk>;
> + clock-names = "apb_pclk";
> + status = "disabled";
> + };
> +
> + gpiof: gpio at fff31000 {
> + #gpio-cells = <2>;
> + compatible = "arm,pl061", "arm,primecell";
> + gpio-controller;
> + reg = <0xfff31000 0x1000>;
> + interrupts = <0 15 4>;
> + clocks = <&pclk>;
> + clock-names = "apb_pclk";
> + status = "disabled";
> + };
> +
> + gpiog: gpio at fff32000 {
> + #gpio-cells = <2>;
> + compatible = "arm,pl061", "arm,primecell";
> + gpio-controller;
> + reg = <0xfff32000 0x1000>;
> + interrupts = <0 16 4>;
> + clocks = <&pclk>;
> + clock-names = "apb_pclk";
> + status = "disabled";
> + };
> +
> + gpioh: gpio at fff33000 {
> + #gpio-cells = <2>;
> + compatible = "arm,pl061", "arm,primecell";
> + gpio-controller;
> + reg = <0xfff33000 0x1000>;
> + interrupts = <0 17 4>;
> + clocks = <&pclk>;
> + clock-names = "apb_pclk";
> + status = "disabled";
> + };
> +
> + timer at fff34000 {
> + compatible = "arm,sp804", "arm,primecell";
> + reg = <0xfff34000 0x1000>;
> + interrupts = <0 18 4>;
> + clocks = <&pclk>;
> + clock-names = "apb_pclk";
> + };
> +
> + rtc at fff35000 {
> + compatible = "arm,pl031", "arm,primecell";
> + reg = <0xfff35000 0x1000>;
> + interrupts = <0 19 4>;
> + clocks = <&pclk>;
> + clock-names = "apb_pclk";
> + };
> +
> + serial at fff36000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0xfff36000 0x1000>;
> + interrupts = <0 20 4>;
> + clocks = <&pclk>, <&pclk>;
> + clock-names = "uartclk", "apb_pclk";
> + };
> +
> + smic at fff3a000 {
> + compatible = "ipmi-smic";
> + device_type = "ipmi";
> + reg = <0xfff3a000 0x1000>;
> + interrupts = <0 24 4>;
> + reg-size = <4>;
> + reg-spacing = <4>;
> + };
> +
> + sregs at fff3c000 {
> + compatible = "calxeda,hb-sregs";
> + reg = <0xfff3c000 0x1000>;
> +
> + clocks {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + osc: oscillator {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <33333000>;
> + };
> +
> + ddrpll: ddrpll {
> + #clock-cells = <0>;
> + compatible = "calxeda,hb-pll-clock";
> + clocks = <&osc>;
> + reg = <0x108>;
> + };
> +
> + a9pll: a9pll {
> + #clock-cells = <0>;
> + compatible = "calxeda,hb-pll-clock";
> + clocks = <&osc>;
> + reg = <0x100>;
> + };
> +
> + a9periphclk: a9periphclk {
> + #clock-cells = <0>;
> + compatible = "calxeda,hb-a9periph-clock";
> + clocks = <&a9pll>;
> + reg = <0x104>;
> + };
> +
> + a9bclk: a9bclk {
> + #clock-cells = <0>;
> + compatible = "calxeda,hb-a9bus-clock";
> + clocks = <&a9pll>;
> + reg = <0x104>;
> + };
> +
> + emmcpll: emmcpll {
> + #clock-cells = <0>;
> + compatible = "calxeda,hb-pll-clock";
> + clocks = <&osc>;
> + reg = <0x10C>;
> + };
> +
> + eclk: eclk {
> + #clock-cells = <0>;
> + compatible = "calxeda,hb-emmc-clock";
> + clocks = <&emmcpll>;
> + reg = <0x114>;
> + };
> +
> + pclk: pclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <150000000>;
> + };
> + };
> + };
> +
> + dma at fff3d000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0xfff3d000 0x1000>;
> + interrupts = <0 92 4>;
> + clocks = <&pclk>;
> + clock-names = "apb_pclk";
> + };
> +
> + ethernet at fff50000 {
> + compatible = "calxeda,hb-xgmac";
> + reg = <0xfff50000 0x1000>;
> + interrupts = <0 77 4>, <0 78 4>, <0 79 4>;
> + dma-coherent;
> + };
> +
> + ethernet at fff51000 {
> + compatible = "calxeda,hb-xgmac";
> + reg = <0xfff51000 0x1000>;
> + interrupts = <0 80 4>, <0 81 4>, <0 82 4>;
> + dma-coherent;
> + };
> +
> + combophy0: combo-phy at fff58000 {
> + compatible = "calxeda,hb-combophy";
> + #phy-cells = <1>;
> + reg = <0xfff58000 0x1000>;
> + phydev = <5>;
> + };
> +
> + combophy5: combo-phy at fff5d000 {
> + compatible = "calxeda,hb-combophy";
> + #phy-cells = <1>;
> + reg = <0xfff5d000 0x1000>;
> + phydev = <31>;
> + };
> + };
> +};
> diff --git a/arch/arm/dts/highbank.dts b/arch/arm/dts/highbank.dts
> new file mode 100644
> index 00000000000..b6b0225a769
> --- /dev/null
> +++ b/arch/arm/dts/highbank.dts
> @@ -0,0 +1,158 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright 2011-2012 Calxeda, Inc.
> + */
> +
> +/dts-v1/;
> +
> +/* First 4KB has pen for secondary cores. */
> +/memreserve/ 0x00000000 0x0001000;
> +
> +/ {
> + model = "Calxeda Highbank";
> + compatible = "calxeda,highbank";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu at 900 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + reg = <0x900>;
> + next-level-cache = <&L2>;
> + clocks = <&a9pll>;
> + clock-names = "cpu";
> + operating-points = <
> + /* kHz ignored */
> + 1300000 1000000
> + 1200000 1000000
> + 1100000 1000000
> + 800000 1000000
> + 400000 1000000
> + 200000 1000000
> + >;
> + clock-latency = <100000>;
> + };
> +
> + cpu at 901 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + reg = <0x901>;
> + next-level-cache = <&L2>;
> + clocks = <&a9pll>;
> + clock-names = "cpu";
> + operating-points = <
> + /* kHz ignored */
> + 1300000 1000000
> + 1200000 1000000
> + 1100000 1000000
> + 800000 1000000
> + 400000 1000000
> + 200000 1000000
> + >;
> + clock-latency = <100000>;
> + };
> +
> + cpu at 902 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + reg = <0x902>;
> + next-level-cache = <&L2>;
> + clocks = <&a9pll>;
> + clock-names = "cpu";
> + operating-points = <
> + /* kHz ignored */
> + 1300000 1000000
> + 1200000 1000000
> + 1100000 1000000
> + 800000 1000000
> + 400000 1000000
> + 200000 1000000
> + >;
> + clock-latency = <100000>;
> + };
> +
> + cpu at 903 {
> + compatible = "arm,cortex-a9";
> + device_type = "cpu";
> + reg = <0x903>;
> + next-level-cache = <&L2>;
> + clocks = <&a9pll>;
> + clock-names = "cpu";
> + operating-points = <
> + /* kHz ignored */
> + 1300000 1000000
> + 1200000 1000000
> + 1100000 1000000
> + 800000 1000000
> + 400000 1000000
> + 200000 1000000
> + >;
> + clock-latency = <100000>;
> + };
> + };
> +
> + memory at 0 {
> + name = "memory";
> + device_type = "memory";
> + reg = <0x00000000 0xff900000>;
> + };
> +
> + soc {
> + ranges = <0x00000000 0x00000000 0xffffffff>;
> +
> + memory-controller at fff00000 {
> + compatible = "calxeda,hb-ddr-ctrl";
> + reg = <0xfff00000 0x1000>;
> + interrupts = <0 91 4>;
> + };
> +
> + timer at fff10600 {
> + compatible = "arm,cortex-a9-twd-timer";
> + reg = <0xfff10600 0x20>;
> + interrupts = <1 13 0xf01>;
> + clocks = <&a9periphclk>;
> + };
> +
> + watchdog at fff10620 {
> + compatible = "arm,cortex-a9-twd-wdt";
> + reg = <0xfff10620 0x20>;
> + interrupts = <1 14 0xf01>;
> + clocks = <&a9periphclk>;
> + };
> +
> + intc: interrupt-controller at fff11000 {
> + compatible = "arm,cortex-a9-gic";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0xfff11000 0x1000>,
> + <0xfff10100 0x100>;
> + };
> +
> + L2: cache-controller {
> + compatible = "arm,pl310-cache";
> + reg = <0xfff12000 0x1000>;
> + interrupts = <0 70 4>;
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a9-pmu";
> + interrupts = <0 76 4>, <0 75 4>, <0 74 4>, <0 73 4>;
> + };
> +
> +
> + sregs at fff3c200 {
> + compatible = "calxeda,hb-sregs-l2-ecc";
> + reg = <0xfff3c200 0x100>;
> + interrupts = <0 71 4>, <0 72 4>;
> + };
> +
> + };
> +};
> +
> +/include/ "ecx-common.dtsi"
> diff --git a/configs/highbank_defconfig b/configs/highbank_defconfig
> index 85b42c70f55..3e8bfcf73a6 100644
> --- a/configs/highbank_defconfig
> +++ b/configs/highbank_defconfig
> @@ -7,6 +7,7 @@ CONFIG_SYS_TEXT_BASE=0x00008000
> CONFIG_SYS_MALLOC_LEN=0x80000
> CONFIG_NR_DRAM_BANKS=2
> CONFIG_ENV_SIZE=0x2000
> +CONFIG_DEFAULT_DEVICE_TREE="highbank"
> CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
> CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
> CONFIG_DISTRO_DEFAULTS=y
> @@ -21,7 +22,6 @@ CONFIG_AUTOBOOT_KEYED_CTRLC=y
> # CONFIG_DISPLAY_BOARDINFO is not set
> CONFIG_MISC_INIT_R=y
> # CONFIG_CMD_SETEXPR is not set
> -CONFIG_OF_BOARD=y
> CONFIG_ENV_IS_IN_NVRAM=y
> CONFIG_ENV_ADDR=0xFFF88000
> CONFIG_SCSI_AHCI=y
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