[PATCH] w1: w1-gpio: Loosen timings to improve cold boot reliability

[Eugen.Hristev at microchip.com]

On 11/30/21 5:46 PM, Chris Morgan wrote:
> On Mon, Nov 22, 2021 at 11:16:22AM +0000, Eugen.Hristev at microchip.com wrote:
>> On 11/8/21 5:07 PM, Chris Morgan wrote:
>>> From: Chris Morgan <macromorgan at hotmail.com>
>>>
>>> On my NTC CHIP whenever I do a cold boot any attached DIPs cannot be
>>> found. Rebooting on the other hand appears to fix the issue. I found
>>> that if I modified the timing slightly (but still within spec) the
>>> w1 identification on cold boot became far more reliable.
>>>
>>> Signed-off-by: Chris Morgan <macromorgan at hotmail.com>
>>> ---
>>>    drivers/w1/w1-gpio.c | 4 ++--
>>>    1 file changed, 2 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/w1/w1-gpio.c b/drivers/w1/w1-gpio.c
>>> index 9346f810ce..5565de2a92 100644
>>> --- a/drivers/w1/w1-gpio.c
>>> +++ b/drivers/w1/w1-gpio.c
>>> @@ -22,8 +22,8 @@
>>>    #define W1_TIMING_E    9
>>>    #define W1_TIMING_F    55
>>>    #define W1_TIMING_G    0
>>> -#define W1_TIMING_H    480
>>> -#define W1_TIMING_I    70
>>> +#define W1_TIMING_H    600
>>> +#define W1_TIMING_I    100
>>>    #define W1_TIMING_J    410
>>>
>>>    struct w1_gpio_pdata {
>>> --
>>> 2.30.2
>>>
>>
>>
>> Hi Chris,
>>
>> I tested your patch on my board sama5d2_xplained, and it works.
>> Thus, you can add my
>> Tested-by: Eugen Hristev <eugen.hristev at microchip.com>
>>
>> However, I disagree with the changes you did in timings. What I found
>> was that timing 'H' could go up to 640 , but timing 'I' to a maximum of
>> 75 or so. [1]
>>
>> I am thinking maybe you could also check your udelays with a scope on
>> the 1wire line ? Because your problem might be in fact in some other
>> part , like udelays not properly aligned/synchronized/accurate at cold
>> boot time, depending on the source of clock you are using.
> 
> I lack a scope, but will extensively test 640 and 75 as the new timings.
> Would that be acceptable?
> 
> Thank you.

Hi Chris,

The timings should be in spec, however, if your particular SoC has a 
problem with delays, this should be investigated.

Does your board with with the maximum timings ? (but still in spec)

Eugen
> 
>>
>> Eugen
>>
>>
>> [1]
>> https://na01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.maximintegrated.com%2Fcontent%2Fdam%2Ffiles%2Fdesign%2Ftools%2Ftech-docs%2F126%2FAN126-timing-calculation.zip&data=04%7C01%7C%7C6787b70951c4494fd76808d9ada98a17%7C84df9e7fe9f640afb435aaaaaaaaaaaa%7C1%7C0%7C637731765952771191%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=V81HrXrKI8d45WTrvWrc6ydJy2rdCX5%2FL8eYjvxcwCs%3D&reserved=0