[PATCH v2] net: zynq: Add support for PHY configuration in SGMII mode

[Michal Simek]

út 14. 12. 2021 v 13:42 odesílatel Michal Simek
<michal.simek at xilinx.com> napsal:
>
> SGMII configuration depends on proper GT setting that's why when node has
> phys property call PSGTR driver to configure it properly.
>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> ---
>
> Changes in v2:
> - Handle also cases where phy reference doesn't exist which means
>   that u-boot doesn't need to configure it (configured via psu_init for
>   example)
> - Error out where reference exists but driver is not compiled in - reported
>   by Sean
>
>  drivers/net/zynq_gem.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
>
> diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
> index 5cbe8d28304b..ac658cd6b5e9 100644
> --- a/drivers/net/zynq_gem.c
> +++ b/drivers/net/zynq_gem.c
> @@ -12,6 +12,7 @@
>  #include <common.h>
>  #include <cpu_func.h>
>  #include <dm.h>
> +#include <generic-phy.h>
>  #include <log.h>
>  #include <net.h>
>  #include <netdev.h>
> @@ -716,6 +717,24 @@ static int zynq_gem_probe(struct udevice *dev)
>         struct zynq_gem_priv *priv = dev_get_priv(dev);
>         int ret;
>
> +       if (priv->interface == PHY_INTERFACE_MODE_SGMII) {
> +               struct phy phy;
> +
> +               ret = generic_phy_get_by_index(dev, 0, &phy);
> +               if (!ret) {
> +                       ret = generic_phy_init(&phy);
> +                       if (ret)
> +                               return ret;
> +
> +                       ret = generic_phy_power_on(&phy);
> +                       if (ret)
> +                               return ret;
> +               } else if (ret != -ENOENT) {
> +                       debug("could not get phy (err %d)\n", ret);
> +                       return ret;
> +               }
> +       }
> +
>         ret = zynq_gem_reset_init(dev);
>         if (ret)
>                 return ret;
> --
> 2.34.1
>

Please ignore this v2. I need to send v3 because there must be a reset
between init and power on.
I will send a new version on phy driver with this function.

Thanks,
Michal


-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs