[PATCH v9] driver: spi: add bcm iproc qspi support
Jagan Teki
jagan at amarulasolutions.com
Thu Dec 16 08:49:09 CET 2021
On Wed, Dec 1, 2021 at 11:40 PM Roman Bacik <roman.bacik at broadcom.com> wrote:
>
> IPROC qspi driver supports both BSPI and MSPI modes.
>
> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
> Signed-off-by: Bharat Gooty <bharat.gooty at broadcom.com>
> Acked-by: Rayagonda Kokatanur <rayagonda.kokatanur at broadcom.com>
>
> Signed-off-by: Roman Bacik <roman.bacik at broadcom.com>
> ---
>
> Changes in v9:
> - merge bspi_set_4byte_mode to bspi_set_flex_mode
> - simplify bspi_set_flex_mode using data from spi_mem_op
> - rename mode_4byte to bspi_4byte
> - use BIT(x) istead of 1<<x
>
> Changes in v8:
> - add 4-byte address support
>
> Changes in v7:
> - remove hardcorded IPROC_BSPI_READ_DUMMY_CYCLES
> - remove unnecessary flags from bspi_read
> - fix BSPI supported operation condition
>
> Changes in v6:
> - remove priv->mode_4byte
> - remove IPROC_BSPI_READ_SUPPORTED
>
> Changes in v5:
> - add binding document
> - implement spi-mem interface for bspi mode
> - use op->cmd.opcode for BSPI_CMD_AND_MODE_BYTE_REG
> - move iproc_qspi.c to spi
>
> Changes in v4:
> - move iproc_qspi.c from spi to mtd/spi
> - remove iproc_qspi.h
> - rename IPROC_QSPI to SPI_FLASH_IPROC
>
> Changes in v3:
> - fix warning by including linux/delay.h
> - change ofdata_to_platdata to of_to_plat
> - change priv_auto_alloc_size to priv_auto
>
> Changes in v2:
> - remove include spi-nor.h
> - define and use named BITs for writing register values
> - remove bspi_set_4byte_mode() method
>
> .../spi/spi-iproc-qspi.txt | 29 +
> drivers/spi/Kconfig | 6 +
> drivers/spi/Makefile | 1 +
> drivers/spi/iproc_qspi.c | 657 ++++++++++++++++++
> 4 files changed, 693 insertions(+)
> create mode 100644 doc/device-tree-bindings/spi/spi-iproc-qspi.txt
> create mode 100644 drivers/spi/iproc_qspi.c
>
> diff --git a/doc/device-tree-bindings/spi/spi-iproc-qspi.txt b/doc/device-tree-bindings/spi/spi-iproc-qspi.txt
> new file mode 100644
> index 000000000000..fb9f1c2ae2da
> --- /dev/null
> +++ b/doc/device-tree-bindings/spi/spi-iproc-qspi.txt
> @@ -0,0 +1,29 @@
> +Broadcom Iproc QSPI controller Device Tree Bindings
> +---------------------------------------------------
> +
> +Required properties:
> +- compatible: should be "brcm,iproc-qspi".
> +- reg: Base address and size of the controllers memory area.
> +- reg-names: "bspi", "bspi_raf", "mspi".
> +- #address-cells: <1>, as required by generic SPI binding.
> +- #size-cells: <0>, also as required by generic SPI binding.
> +
> +Example:
> + qspi: spi at 370000 {
> + compatible = "brcm,iproc-qspi";
> + reg = <0x00370000 0x100>,
> + <0x00370100 0x100>,
> + <0x00370200 0x200>;
> + reg-names = "bspi", "bspi_raf", "mspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + spi_nor_flash: spi_flash at 0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <12500000>;
> + spi-cpol;
> + spi-cpha;
> + spi-tx-bus-width = <1>;
> + spi-rx-bus-width = <4>;
> + };
> + };
Please drop this binding away from this patch.
> diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
> index d07e9a28af82..faebc212753e 100644
> --- a/drivers/spi/Kconfig
> +++ b/drivers/spi/Kconfig
> @@ -178,6 +178,12 @@ config ICH_SPI
> access the SPI NOR flash on platforms embedding this Intel
> ICH IP core.
>
> +config IPROC_QSPI
> + bool "Broadcom iProc QSPI Flash Controller driver"
> + help
> + Enable Broadcom iProc QSPI Flash Controller driver.
> + This driver can be used to access the SPI NOR flash.
> +
> config KIRKWOOD_SPI
> bool "Marvell Kirkwood SPI Driver"
> help
> diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
> index d2f24bccefd3..869763187062 100644
> --- a/drivers/spi/Makefile
> +++ b/drivers/spi/Makefile
> @@ -33,6 +33,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o
> obj-$(CONFIG_FSL_ESPI) += fsl_espi.o
> obj-$(CONFIG_SYNQUACER_SPI) += spi-synquacer.o
> obj-$(CONFIG_ICH_SPI) += ich.o
> +obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o
> obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
> obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o
> obj-$(CONFIG_MPC8XX_SPI) += mpc8xx_spi.o
> diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c
> new file mode 100644
> index 000000000000..d3c3a8c7f028
> --- /dev/null
> +++ b/drivers/spi/iproc_qspi.c
> @@ -0,0 +1,657 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2020-2021 Broadcom
> + */
> +
> +#include <common.h>
> +#include <dm.h>
> +#include <spi.h>
> +#include <spi-mem.h>
> +#include <asm/io.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/log2.h>
> +
> +/* 175MHz */
> +#define QSPI_AXI_CLK 175000000
> +#define QSPI_WAIT_TIMEOUT_MS 200U
> +#define DWORD_ALIGNED(a) (!(((ulong)(a)) & 3))
> +
> +/* Chip attributes */
> +#define SPBR_MIN 8U
> +#define SPBR_MAX 255U
> +#define NUM_CDRAM 16U
> +
> +#define CDRAM_PCS0 2
> +#define CDRAM_CONT BIT(7)
> +#define CDRAM_BITS_EN BIT(6)
> +#define CDRAM_QUAD_MODE BIT(8)
> +#define CDRAM_RBIT_INPUT BIT(10)
> +#define MSPI_SPE BIT(6)
> +#define MSPI_CONT_AFTER_CMD BIT(7)
> +
> +/* Register fields */
> +#define MSPI_SPCR0_MSB_BITS_8 0x00000020
> +#define BSPI_RAF_CONTROL_START_MASK 0x00000001
> +#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001
> +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002
> +#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT 3
> +#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT 1
> +#define BSPI_STRAP_OVERRIDE_SHIFT 0
> +#define BSPI_BPC_DATA_SHIFT 0
> +#define BSPI_BPC_MODE_SHIFT 8
> +#define BSPI_BPC_ADDR_SHIFT 16
> +#define BSPI_BPC_CMD_SHIFT 24
> +#define BSPI_BPP_ADDR_SHIFT 16
> +
> +/* MSPI registers */
> +#define MSPI_SPCR0_LSB_REG 0x000
> +#define MSPI_SPCR0_MSB_REG 0x004
> +#define MSPI_SPCR1_LSB_REG 0x008
> +#define MSPI_SPCR1_MSB_REG 0x00c
> +#define MSPI_NEWQP_REG 0x010
> +#define MSPI_ENDQP_REG 0x014
> +#define MSPI_SPCR2_REG 0x018
> +#define MSPI_STATUS_REG 0x020
> +#define MSPI_CPTQP_REG 0x024
> +#define MSPI_TXRAM_REG 0x040
> +#define MSPI_RXRAM_REG 0x0c0
> +#define MSPI_CDRAM_REG 0x140
> +#define MSPI_WRITE_LOCK_REG 0x180
> +#define MSPI_DISABLE_FLUSH_GEN_REG 0x184
> +
> +/* BSPI registers */
> +#define BSPI_REVISION_ID_REG 0x000
> +#define BSPI_SCRATCH_REG 0x004
> +#define BSPI_MAST_N_BOOT_CTRL_REG 0x008
> +#define BSPI_BUSY_STATUS_REG 0x00c
> +#define BSPI_INTR_STATUS_REG 0x010
> +#define BSPI_B0_STATUS_REG 0x014
> +#define BSPI_B0_CTRL_REG 0x018
> +#define BSPI_B1_STATUS_REG 0x01c
> +#define BSPI_B1_CTRL_REG 0x020
> +#define BSPI_STRAP_OVERRIDE_CTRL_REG 0x024
> +#define BSPI_FLEX_MODE_ENABLE_REG 0x028
> +#define BSPI_BITS_PER_CYCLE_REG 0x02C
> +#define BSPI_BITS_PER_PHASE_REG 0x030
> +#define BSPI_CMD_AND_MODE_BYTE_REG 0x034
> +#define BSPI_FLASH_UPPER_ADDR_BYTE_REG 0x038
> +#define BSPI_XOR_VALUE_REG 0x03C
> +#define BSPI_XOR_ENABLE_REG 0x040
> +#define BSPI_PIO_MODE_ENABLE_REG 0x044
> +#define BSPI_PIO_IODIR_REG 0x048
> +#define BSPI_PIO_DATA_REG 0x04C
> +
> +/* RAF registers */
> +#define BSPI_RAF_START_ADDRESS_REG 0x00
> +#define BSPI_RAF_NUM_WORDS_REG 0x04
> +#define BSPI_RAF_CTRL_REG 0x08
> +#define BSPI_RAF_FULLNESS_REG 0x0C
> +#define BSPI_RAF_WATERMARK_REG 0x10
> +#define BSPI_RAF_STATUS_REG 0x14
> +#define BSPI_RAF_READ_DATA_REG 0x18
> +#define BSPI_RAF_WORD_CNT_REG 0x1C
> +#define BSPI_RAF_CURR_ADDR_REG 0x20
> +
> +#define XFER_DUAL BIT(30)
> +#define XFER_QUAD BIT(31)
> +
> +#define FLASH_BIT BIT(0)
> +#define MAST_N_BOOT_BIT BIT(0)
> +#define WRITE_LOCK_BIT BIT(0)
> +
> +/* state */
> +enum bcm_qspi_state {
> + QSPI_STATE_DISABLED,
> + QSPI_STATE_MSPI,
> + QSPI_STATE_BSPI
> +};
> +
> +/**
> + * struct bcmspi_priv - qspi private structure
> + *
> + * @max_hz: device transfer speed
> + * @spi_mode: spi mode (SPI_... flags)
> + * @frequency: spi max frequency
> + * @state: device state (MSPI/BSPI)
> + * @bspi_addr: bspi read address
> + * @bspi_4byte: bspi 4 byte address mode
> + * @mspi_16bit: mspi transfer mode
> + * @mspi: mspi registers block address
> + * @bspi: bspi registers block address
> + * @bspi_raf: bspi raf registers block address
> + */
> +struct bcmspi_priv {
> + uint max_hz;
> + uint spi_mode;
> + s32 frequency;
> + enum bcm_qspi_state state;
> + u32 bspi_addr;
> + bool bspi_4byte;
> + int mspi_16bit;
> + void __iomem *mspi;
> + void __iomem *bspi;
> + void __iomem *bspi_raf;
> +};
> +
> +/* BSPI mode */
> +
> +static void bspi_flush_prefetch_buffers(struct bcmspi_priv *priv)
> +{
> + writel(0, priv->bspi + BSPI_B0_CTRL_REG);
> + writel(0, priv->bspi + BSPI_B1_CTRL_REG);
> + writel(FLASH_BIT, priv->bspi + BSPI_B0_CTRL_REG);
> + writel(FLASH_BIT, priv->bspi + BSPI_B1_CTRL_REG);
> +}
> +
> +static int bspi_enable(struct bcmspi_priv *priv)
> +{
> + if (priv->state == QSPI_STATE_BSPI)
> + return 0;
> +
> + /* Disable write lock */
> + writel(0, priv->mspi + MSPI_WRITE_LOCK_REG);
> + /* Flush prefetch buffers */
> + bspi_flush_prefetch_buffers(priv);
> + /* Switch to BSPI */
> + writel(0, priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG);
> + /* Update state */
> + priv->state = QSPI_STATE_BSPI;
> +
> + return 0;
> +}
> +
> +static int bspi_disable(struct bcmspi_priv *priv)
> +{
> + if (priv->state == QSPI_STATE_MSPI)
> + return 0;
> +
> + if ((readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) {
> + ulong start = get_timer(0);
> +
> + while (get_timer(start) <
> + QSPI_WAIT_TIMEOUT_MS * CONFIG_SYS_HZ / 1000) {
> + if ((readl(priv->bspi + BSPI_BUSY_STATUS_REG) & 1)
> + == 0) {
> + /* Switch to MSPI */
> + writel(MAST_N_BOOT_BIT, priv->bspi +
> + BSPI_MAST_N_BOOT_CTRL_REG);
> + udelay(1);
> + break;
> + }
> + udelay(1);
> + }
> + if ((readl(priv->bspi + BSPI_MAST_N_BOOT_CTRL_REG) & 1) != 1)
> + return -1;
> + }
This logic look odd to me. Better read the register separably and do
the action of waiting. for waiting please use poll read function -
readl_poll_timeout.
> +
> + /* Enable write lock */
> + writel(WRITE_LOCK_BIT, priv->mspi + MSPI_WRITE_LOCK_REG);
> +
> + /* Update state */
> + priv->state = QSPI_STATE_MSPI;
> +
> + return 0;
> +}
> +
> +static void bspi_read_via_raf(struct bcmspi_priv *priv, u8 *rx, uint bytes)
> +{
> + u32 status;
> + uint words;
> + int aligned;
> +
> + /* Flush data from the previous session (unlikely) */
> + for (;;) {
> + status = readl(priv->bspi_raf + BSPI_RAF_STATUS_REG);
> + if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
> + readl(priv->bspi_raf + BSPI_RAF_READ_DATA_REG);
> + continue;
> + }
> + if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK))
> + break;
> + }
Use some definite timeout instead of forever loop with readl_poll_timeout.
> +
> + /* Transfer is in words */
> + words = (bytes + 3) / 4;
> +
> + /* Setup hardware */
> + if (priv->bspi_4byte) {
> + u32 val = priv->bspi_addr & 0xFF000000;
> +
> + if (val != readl(priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG)) {
> + writel(val, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
> + bspi_flush_prefetch_buffers(priv);
> + }
> + }
> +
> + writel(priv->bspi_addr & 0x00FFFFFF,
> + priv->bspi_raf + BSPI_RAF_START_ADDRESS_REG);
> + writel(words, priv->bspi_raf + BSPI_RAF_NUM_WORDS_REG);
> + writel(0, priv->bspi_raf + BSPI_RAF_WATERMARK_REG);
> +
> + /* Start reading */
> + writel(BSPI_RAF_CONTROL_START_MASK, priv->bspi_raf + BSPI_RAF_CTRL_REG);
> + aligned = DWORD_ALIGNED(rx);
> + while (bytes) {
> + status = readl(priv->bspi_raf + BSPI_RAF_STATUS_REG);
> + if (!(status & BSPI_RAF_STATUS_FIFO_EMPTY_MASK)) {
> + /*
> + * RAF is LE only,
> + * convert data to host endianness
> + */
> + u32 data = le32_to_cpu(readl(priv->bspi_raf +
> + BSPI_RAF_READ_DATA_REG));
mark all these in single line, if it not showing any warning.
> +
> + /* Check if we can use the whole word */
> + if (aligned && bytes >= 4) {
> + *(u32 *)rx = data;
> + rx += 4;
> + bytes -= 4;
> + } else {
> + uint chunk = min(bytes, 4U);
> +
> + /* Read out bytes one by one */
> + while (chunk) {
> + *rx++ = (u8)data;
> + data >>= 8;
> + chunk--;
> + bytes--;
> + }
> + }
> +
> + continue;
> + }
> + if (!(status & BSPI_RAF_STATUS_SESSION_BUSY_MASK)) {
> + /* FIFO is empty and the session is done */
> + break;
> + }
> + }
> +}
> +
> +static int bspi_read(struct bcmspi_priv *priv, const struct spi_mem_op *op)
> +{
> + u8 *rx = op->data.buf.in;
> + uint bytes = op->data.nbytes;
> + uint trans;
> +
> + priv->bspi_addr = op->addr.val;
> +
> + /* Transfer data */
> + while (bytes > 0 && rx) {
> + /* Special handing since RAF cannot go across 16MB boundary */
> + trans = bytes;
> + /*
> + * Divide into multiple transfers if it goes
> + * across the 16MB boundary
> + */
> + if (priv->bspi_4byte &&
> + (priv->bspi_addr >> 24) !=
> + ((priv->bspi_addr + bytes) >> 24))
> + trans = 0x01000000 - (priv->bspi_addr & 0x00FFFFFF);
> +
> + bspi_read_via_raf(priv, rx, trans);
> + priv->bspi_addr += trans;
> + rx += trans;
> + bytes -= trans;
> + }
> +
> + bspi_flush_prefetch_buffers(priv);
> + return 0;
> +}
> +
> +static void bspi_set_flex_mode(struct bcmspi_priv *priv, const struct spi_mem_op *op)
> +{
> + int bpp = (op->dummy.nbytes * 8) / op->dummy.buswidth;
> + int opcode = op->cmd.opcode;
> + int bpc = ilog2(op->data.buswidth) << BSPI_BPC_DATA_SHIFT |
> + ilog2(op->addr.buswidth) << BSPI_BPC_ADDR_SHIFT |
> + ilog2(op->cmd.buswidth) << BSPI_BPC_CMD_SHIFT;
> +
> + /* Disable flex mode first */
> + writel(0, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
> +
> + /* Configure single, dual or quad mode */
> + writel(bpc, priv->bspi + BSPI_BITS_PER_CYCLE_REG);
> +
> + /* Opcode */
> + writel(opcode, priv->bspi + BSPI_CMD_AND_MODE_BYTE_REG);
> +
> + /* Count of dummy cycles */
> + writel(bpp, priv->bspi + BSPI_BITS_PER_PHASE_REG);
> +
> + /* Enable 32-bit address */
> + if (priv->bspi_4byte) {
> + setbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT));
> + } else {
> + clrbits_le32(priv->bspi + BSPI_BITS_PER_PHASE_REG, BIT(BSPI_BPP_ADDR_SHIFT));
> + writel(0, priv->bspi + BSPI_FLASH_UPPER_ADDR_BYTE_REG);
> + }
> +
> + /* Enable flex mode to take effect */
> + writel(1, priv->bspi + BSPI_FLEX_MODE_ENABLE_REG);
> +
> + /* Flush prefetch buffers since 32MB window BSPI could be used */
> + bspi_flush_prefetch_buffers(priv);
> +}
> +
> +static int bspi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
> +{
> + struct udevice *bus = slave->dev->parent;
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> + int ret = -ENOTSUPP;
> +
> + /* BSPI: flash read */
> + if (op->data.dir == SPI_MEM_DATA_IN &&
> + op->data.nbytes && op->addr.nbytes) {
> + priv->bspi_4byte = (op->addr.nbytes > 3);
> + bspi_set_flex_mode(priv, op);
> + ret = bspi_read(priv, op);
> + }
> +
> + return ret;
> +}
> +
> +static const struct spi_controller_mem_ops bspi_mem_ops = {
> + .exec_op = bspi_exec_op,
> +};
> +
> +/* MSPI mode */
> +
> +static int mspi_exec(struct bcmspi_priv *priv, uint bytes,
> + const u8 *tx, u8 *rx, ulong flags)
> +{
> + u32 cdr = CDRAM_PCS0;
> +
> + if (flags & XFER_QUAD) {
> + cdr |= CDRAM_QUAD_MODE;
> +
> + if (!tx)
> + cdr |= CDRAM_RBIT_INPUT;
> + }
> +
> + if (bytes & 1) {
> + /* Use 8-bit queue for odd-bytes transfer */
> + if (priv->mspi_16bit) {
> + setbits_le32(priv->mspi + MSPI_SPCR0_MSB_REG,
> + MSPI_SPCR0_MSB_BITS_8);
> + priv->mspi_16bit = 0;
> + }
> + } else {
> + /* Use 16-bit queue for even-bytes transfer */
> + if (!priv->mspi_16bit) {
> + clrbits_le32(priv->mspi + MSPI_SPCR0_MSB_REG,
> + MSPI_SPCR0_MSB_BITS_8);
> + priv->mspi_16bit = 1;
> + }
> + }
> +
> + while (bytes) {
> + uint chunk;
> + uint queues;
> + ulong start;
> + uint i;
> +
> + /* Separate code for 16bit and 8bit transfers for performance */
> + if (priv->mspi_16bit) {
> + /* Determine how many bytes to process this time */
> + chunk = min(bytes, NUM_CDRAM * 2);
> + queues = (chunk + 1) / 2;
> + bytes -= chunk;
> +
> + /* Fill CDRAMs */
> + for (i = 0; i < queues; i++)
> + writel(cdr | CDRAM_CONT | CDRAM_BITS_EN,
> + priv->mspi + MSPI_CDRAM_REG + (i << 2));
> +
> + /* Fill TXRAMs */
> + for (i = 0; i < chunk; i++)
> + writel(tx ? tx[i] : 0xff,
> + priv->mspi + MSPI_TXRAM_REG + (i << 2));
> + } else {
> + /* Determine how many bytes to process this time */
> + chunk = min(bytes, NUM_CDRAM);
> + queues = chunk;
> + bytes -= chunk;
> +
> + /* Fill CDRAMs and TXRAMS */
> + for (i = 0; i < chunk; i++) {
> + writel(cdr | CDRAM_CONT,
> + priv->mspi + MSPI_CDRAM_REG + (i << 2));
> + writel(tx ? tx[i] : 0xff,
> + priv->mspi + MSPI_TXRAM_REG + (i << 3));
> + }
> + }
> +
> + /* Setup queue pointers */
> + writel(0, priv->mspi + MSPI_NEWQP_REG);
> + writel(queues - 1, priv->mspi + MSPI_ENDQP_REG);
> +
> + /* Deassert CS if requested and it's the last transfer */
> + if (bytes == 0 && (flags & SPI_XFER_END))
> + clrbits_le32(priv->mspi + MSPI_CDRAM_REG +
> + ((queues - 1) << 2), CDRAM_CONT);
> +
> + /* Kick off */
> + writel(0, priv->mspi + MSPI_STATUS_REG);
> + if (bytes == 0 && (flags & SPI_XFER_END))
> + writel(MSPI_SPE, priv->mspi + MSPI_SPCR2_REG);
> + else
> + writel(MSPI_SPE | MSPI_CONT_AFTER_CMD,
> + priv->mspi + MSPI_SPCR2_REG);
> +
> + /* Wait for completion */
> + start = get_timer(0);
> + while (get_timer(start) <
> + QSPI_WAIT_TIMEOUT_MS * CONFIG_SYS_HZ / 1000) {
> + if (readl(priv->mspi + MSPI_STATUS_REG) & 1)
> + break;
> + }
> + if ((readl(priv->mspi + MSPI_STATUS_REG) & 1) == 0)
> + return -1;
readl_poll_timeout
> +
> + /* Read data out */
> + if (rx) {
> + if (priv->mspi_16bit) {
> + for (i = 0; i < chunk; i++) {
> + rx[i] = readl(priv->mspi +
> + MSPI_RXRAM_REG +
> + (i << 2)) & 0xff;
mark all these in single line.
> + }
> + } else {
> + for (i = 0; i < chunk; i++) {
> + rx[i] = readl(priv->mspi +
> + MSPI_RXRAM_REG +
> + (((i << 1) + 1) << 2))
> + & 0xff;
mark all these in single line.
> + }
> + }
> + }
> +
> + /* Advance pointers */
> + if (tx)
> + tx += chunk;
> + if (rx)
> + rx += chunk;
> + }
> +
> + return 0;
> +}
> +
> +static int mspi_xfer(struct udevice *dev, uint bitlen,
> + const void *dout, void *din, ulong flags)
> +{
> + struct udevice *bus = dev->parent;
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> + uint bytes;
> + int ret = 0;
> +
> + /* we can only transfer multiples of 8 bits */
> + if (bitlen % 8)
> + return -EPROTONOSUPPORT;
> +
> + bytes = bitlen / 8;
> +
> + if (flags & SPI_XFER_BEGIN) {
> + /* Switch to MSPI */
> + ret = bspi_disable(priv);
> + if (ret)
> + return ret;
> + }
> +
> + /* MSPI: Transfer */
> + if (bytes)
> + ret = mspi_exec(priv, bytes, dout, din, flags);
> +
> + if (flags & SPI_XFER_END) {
> + /* Switch back to BSPI */
> + ret = bspi_enable(priv);
> + if (ret)
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> +/* iProc interface */
> +
> +static int iproc_qspi_set_speed(struct udevice *bus, uint speed)
> +{
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> + uint spbr;
> +
> + priv->max_hz = speed;
> +
> + /* MSPI: SCK configuration */
> + spbr = (QSPI_AXI_CLK - 1) / (2 * priv->max_hz) + 1;
> + writel(max(min(spbr, SPBR_MAX), SPBR_MIN),
> + priv->mspi + MSPI_SPCR0_LSB_REG);
> +
> + return 0;
> +}
> +
> +static int iproc_qspi_set_mode(struct udevice *bus, uint mode)
> +{
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> +
> + priv->spi_mode = mode;
> +
> + /*
> + * BSPI: override the strap settings.
> + */
> + if (mode & SPI_RX_QUAD) {
> + setbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_SHIFT));
> + setbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT));
> + clrbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT));
> + } else if (mode & SPI_RX_DUAL) {
> + setbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_SHIFT));
> + clrbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT));
> + setbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT));
> + } else {
> + clrbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_SHIFT));
> + clrbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT));
> + clrbits_le32(priv->bspi + BSPI_STRAP_OVERRIDE_CTRL_REG,
> + BIT(BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT));
> + }
> +
> + /*
> + * MSPI: set master bit and mode.
> + */
> + priv->mspi_16bit = 1;
> + writel(0x80 | /* Master */
> + (priv->spi_mode & 3), /* mode: CPOL / CPHA */
> + priv->mspi + MSPI_SPCR0_MSB_REG);
> +
> + return 0;
> +}
> +
> +static int iproc_qspi_claim_bus(struct udevice *dev)
> +{
> + /* Nothing to do */
> + return 0;
> +}
> +
> +static int iproc_qspi_release_bus(struct udevice *dev)
> +{
> + struct udevice *bus = dev->parent;
> + struct bcmspi_priv *priv = dev_get_priv(bus);
> +
> + /* Make sure no operation is in progress */
> + writel(0, priv->mspi + MSPI_SPCR2_REG);
> + udelay(1);
document it about the delay and it's duration.
Thanks,
Jagan.
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