[PATCH u-boot-marvell 2/9] board: gdsys: a38x: Enable PCIe link 2 in spl_board_init()

[Pali Rohár]

A385 controlcenterdc board does not use PCI DM properly and touches some
PCIe devices directly in its board code.

This controlcenterdc spl_board_init() function expects that PCIe link is
already initialized. Link itself is initialized in a38x serdes code but
this will change in future and link initialization will be postponed from
U-Boot SPL to proper U-Boot.

So explicitly enable PCIe link 2 in spl_board_init() function via
SoC Control Register 1 to not break this code by future changes. This board
has PCIe link 2 just x1, so no additional initialization (except enabling
PCIe port) is needed.

Signed-off-by: Pali Rohár <pali at kernel.org>
---
 board/gdsys/a38x/controlcenterdc.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/board/gdsys/a38x/controlcenterdc.c b/board/gdsys/a38x/controlcenterdc.c
index 243d02232667..7d65400ccb0d 100644
--- a/board/gdsys/a38x/controlcenterdc.c
+++ b/board/gdsys/a38x/controlcenterdc.c
@@ -100,6 +100,10 @@ void spl_board_init(void)
 	uint k;
 	struct gpio_desc gpio = {};
 
+	/* Enable PCIe link 2 */
+	setbits_32(MVEBU_REGISTER(0x18204), BIT(2));
+	mdelay(10);
+
 	if (!request_gpio_by_name(&gpio, "pca9698 at 22", 31, "fpga-program-gpio")) {
 		/* prepare FPGA reconfiguration */
 		dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
-- 
2.20.1