[PATCH v3 3/3] rockchip: rk3568: add arch_cpu_init()

[Kever Yang]

On 2021/10/26 上午10:42, Nico Cheng wrote:
> We configured the drive strength and security of EMMC in
> arch_cpu_init().
>
> Signed-off-by: Nico Cheng <nico.cheng at rock-chips.com>
Reviewed-by: Kever Yang <kever.yang at rock-chips.com>

Thanks,
- Kever
> ---
>
> Changes in v3:
> Replace configuration parameters of SGRF_SOC_CON4 with macro
> definitions.
>
> Changes in v2:
> We use the rk_clrreg function instead of the writel to set eMMC sdmmc0 to
> secure.
> Modify comments to make them more explicit.
>
>   arch/arm/mach-rockchip/rk3568/rk3568.c | 27 +++++++++++++++++++++++---
>   1 file changed, 24 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-rockchip/rk3568/rk3568.c b/arch/arm/mach-rockchip/rk3568/rk3568.c
> index 973b4f9dcb..22eeb77d41 100644
> --- a/arch/arm/mach-rockchip/rk3568/rk3568.c
> +++ b/arch/arm/mach-rockchip/rk3568/rk3568.c
> @@ -11,9 +11,18 @@
>   #include <asm/arch-rockchip/hardware.h>
>   #include <dt-bindings/clock/rk3568-cru.h>
>   
> -#define PMUGRF_BASE		0xfdc20000
> -#define GRF_BASE		0xfdc60000
> -
> +#define PMUGRF_BASE			0xfdc20000
> +#define GRF_BASE			0xfdc60000
> +#define GRF_GPIO1B_DS_2			0x218
> +#define GRF_GPIO1B_DS_3			0x21c
> +#define GRF_GPIO1C_DS_0			0x220
> +#define GRF_GPIO1C_DS_1			0x224
> +#define GRF_GPIO1C_DS_2			0x228
> +#define GRF_GPIO1C_DS_3			0x22c
> +#define SGRF_BASE			0xFDD18000
> +#define SGRF_SOC_CON4			0x10
> +#define EMMC_HPROT_SECURE_CTRL		0x03
> +#define SDMMC0_HPROT_SECURE_CTRL	0x01
>   /* PMU_GRF_GPIO0D_IOMUX_L */
>   enum {
>   	GPIO0D1_SHIFT		= 4,
> @@ -81,5 +90,17 @@ void board_debug_uart_init(void)
>   
>   int arch_cpu_init(void)
>   {
> +#ifdef CONFIG_SPL_BUILD
> +	/* Set the emmc sdmmc0 to secure */
> +	rk_clrreg(SGRF_BASE + SGRF_SOC_CON4, (EMMC_HPROT_SECURE_CTRL << 11
> +		| SDMMC0_HPROT_SECURE_CTRL << 4));
> +	/* set the emmc driver strength to level 2 */
> +	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_2);
> +	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1B_DS_3);
> +	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_0);
> +	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_1);
> +	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_2);
> +	writel(0x3f3f0707, GRF_BASE + GRF_GPIO1C_DS_3);
> +#endif
>   	return 0;
>   }