[PATCH] arm64: zynqmp: Sync DT with Linux kernel

[Michal Simek]

st 2. 12. 2020 v 9:03 odesílatel Michal Simek <michal.simek at xilinx.com> napsal:
>
> All changes are recorded in lore.kernel.org. Here are links to that patches
> for the record.
> Link: https://lore.kernel.org/r/f59a63d8cb941592de6d2dee8afa6f120b2e40c8.1601379794.git.michal.simek@xilinx.com
> Link: https://lore.kernel.org/r/68f20a2b2bb0feee80bc3348619c2ee98aa69963.1598263539.git.michal.simek@xilinx.com
> Link: https://lore.kernel.org/r/f767fe007e446a2299fda9905e75b723c650a424.1605021644.git.michal.simek@xilinx.com
> Link: https://lore.kernel.org/r/cc294ae1a79ef845af6809ddb4049f0c0f5bb87a.1598259551.git.michal.simek@xilinx.com
> Link: https://lore.kernel.org/r/20200629081744.13916-1-krzk@kernel.org
>
> And there are other minor changes (just moving things around).
>
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> ---
>
>  arch/arm/dts/zynqmp.dtsi | 61 ++++++++++++++++++----------------------
>  1 file changed, 28 insertions(+), 33 deletions(-)
>
> diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
> index 1634af0bd896..aa0ac95e122e 100644
> --- a/arch/arm/dts/zynqmp.dtsi
> +++ b/arch/arm/dts/zynqmp.dtsi
> @@ -115,8 +115,10 @@
>                               <0x0 0xff9905e0 0x0 0x20>,
>                               <0x0 0xff990e80 0x0 0x20>,
>                               <0x0 0xff990ea0 0x0 0x20>;
> -                       reg-names = "local_request_region", "local_response_region",
> -                                   "remote_request_region", "remote_response_region";
> +                       reg-names = "local_request_region",
> +                                   "local_response_region",
> +                                   "remote_request_region",
> +                                   "remote_response_region";
>                         #mbox-cells = <1>;
>                         xlnx,ipi-id = <4>;
>                 };
> @@ -145,15 +147,10 @@
>         firmware {
>                 zynqmp_firmware: zynqmp-firmware {
>                         compatible = "xlnx,zynqmp-firmware";
> +                       #power-domain-cells = <1>;
>                         method = "smc";
> -                       #power-domain-cells = <0x1>;
>                         u-boot,dm-pre-reloc;
>
> -                       zynqmp_pcap: pcap {
> -                               compatible = "xlnx,zynqmp-pcap-fpga";
> -                               clock-names = "ref_clk";
> -                       };
> -
>                         zynqmp_power: zynqmp-power {
>                                 u-boot,dm-pre-reloc;
>                                 compatible = "xlnx,zynqmp-power";
> @@ -163,6 +160,11 @@
>                                 mbox-names = "tx", "rx";
>                         };
>
> +                       zynqmp_pcap: pcap {
> +                               compatible = "xlnx,zynqmp-pcap-fpga";
> +                               clock-names = "ref_clk";
> +                       };
> +
>                         zynqmp_reset: reset-controller {
>                                 compatible = "xlnx,zynqmp-reset";
>                                 #reset-cells = <1>;
> @@ -206,26 +208,7 @@
>                 };
>         };
>
> -       amba_apu: amba-apu at 0 {
> -               compatible = "simple-bus";
> -               #address-cells = <2>;
> -               #size-cells = <1>;
> -               ranges = <0 0 0 0 0xffffffff>;
> -
> -               gic: interrupt-controller at f9010000 {
> -                       compatible = "arm,gic-400";
> -                       #interrupt-cells = <3>;
> -                       reg = <0x0 0xf9010000 0x10000>,
> -                             <0x0 0xf9020000 0x20000>,
> -                             <0x0 0xf9040000 0x20000>,
> -                             <0x0 0xf9060000 0x20000>;
> -                       interrupt-controller;
> -                       interrupt-parent = <&gic>;
> -                       interrupts = <1 9 0xf04>;
> -               };
> -       };
> -
> -       amba: amba {
> +       amba: axi {
>                 compatible = "simple-bus";
>                 u-boot,dm-pre-reloc;
>                 #address-cells = <2>;
> @@ -380,6 +363,18 @@
>                         power-domains = <&zynqmp_firmware PD_GDMA>;
>                 };
>
> +               gic: interrupt-controller at f9010000 {
> +                       compatible = "arm,gic-400";
> +                       #interrupt-cells = <3>;
> +                       reg = <0x0 0xf9010000 0x0 0x10000>,
> +                             <0x0 0xf9020000 0x0 0x20000>,
> +                             <0x0 0xf9040000 0x0 0x20000>,
> +                             <0x0 0xf9060000 0x0 0x20000>;
> +                       interrupt-controller;
> +                       interrupt-parent = <&gic>;
> +                       interrupts = <1 9 0xf04>;
> +               };
> +
>                 gpu: gpu at fd4b0000 {
>                         status = "disabled";
>                         compatible = "arm,mali-400", "arm,mali-utgard";
> @@ -590,7 +585,7 @@
>                 };
>
>                 i2c0: i2c at ff020000 {
> -                       compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
> +                       compatible = "cdns,i2c-r1p14";
>                         status = "disabled";
>                         interrupt-parent = <&gic>;
>                         interrupts = <0 17 4>;
> @@ -601,7 +596,7 @@
>                 };
>
>                 i2c1: i2c at ff030000 {
> -                       compatible = "cdns,i2c-r1p14", "cdns,i2c-r1p10";
> +                       compatible = "cdns,i2c-r1p14";
>                         status = "disabled";
>                         interrupt-parent = <&gic>;
>                         interrupts = <0 18 4>;
> @@ -639,8 +634,8 @@
>                               <0x0 0xfd480000 0x0 0x1000>,
>                               <0x80 0x00000000 0x0 0x1000000>;
>                         reg-names = "breg", "pcireg", "cfg";
> -                       ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000  /* non-prefetchable memory */
> -                                 0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
> +                       ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000>,/* non-prefetchable memory */
> +                                <0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memory */
>                         bus-range = <0x00 0xff>;
>                         interrupt-map-mask = <0x0 0x0 0x0 0x7>;
>                         interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
> @@ -770,7 +765,7 @@
>                         clock-output-names = "clk_out_sd1", "clk_in_sd1";
>                 };
>
> -               smmu: smmu at fd800000 {
> +               smmu: iommu at fd800000 {
>                         compatible = "arm,mmu-500";
>                         reg = <0x0 0xfd800000 0x0 0x20000>;
>                         #iommu-cells = <1>;
> --
> 2.29.2
>

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs