[PATCH V2] net: dwc_eth_qos: Pad descriptors to cacheline size

Marek Vasut marex at denx.de
Wed Jan 6 21:53:54 CET 2021

On 1/6/21 8:25 PM, Stephen Warren wrote:
> On 1/6/21 7:14 AM, Marek Vasut wrote:
>> The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words
>> after the descriptor. Use this to pad the descriptors to cacheline size and
>> remove the need for noncached memory altogether. Moreover, this lets Tegra
>> use the generic cache flush / invalidate operations.
>> diff --git a/drivers/net/dwc_eth_qos.c b/drivers/net/dwc_eth_qos.c
>> +static void *eqos_alloc_descs(struct eqos_priv *eqos, unsigned int num)
>>   {
>> +	eqos->desc_size = max(sizeof(struct eqos_desc),
>> +			      (unsigned int)ARCH_DMA_MINALIGN);
> I think that should be ALIGN(sizeof(struct eqos_desc),
> ARCH_DMA_MINALIGN), to cover the (unlikely?) case where the descriptor
> is larger than MINALIGN. The new version of eqos_inval_desc_generic() in
> this patch already does the equivalent thing.


>> diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h
>> -#define CONFIG_SYS_NONCACHED_MEMORY	(1 << 20)	/* 1 MiB */
> This is wrong; there are other devices that are used on Tegra that
> require the noncached memory pool, e.g. the r8169 device.

Isn't r8169 PCI device ? Shouldn't the r8169 driver be fixed instead ?

> I'll try and test this patch with the EQoS driver later today.



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