[PATCH] sunxi: dram: h6: Improve DDR3 config detection

[André Przywara]

On 10/01/2021 18:43, Jernej Škrabec wrote:
> Dne petek, 08. januar 2021 ob 03:01:42 CET je André Przywara napisal(a):
>> On 03/12/2020 17:46, Jernej Skrabec wrote:
>>> It turns out that in rare cases, current analytical approach to detect
>>> correct DRAM bus width and rank on H6 doesn't work. On some TV boxes
>>> with DDR3, incorrect DRAM configuration triggers write leveling error
>>> which immediately stops initialization process. Exact reason why this
>>> error appears isn't known. However, if correct configuration is used,
>>> initalization works without problem.
>>>
>>> In order to fix this issue, simply try another configuration when any
>>> kind of error appears during initialization, not just those related to
>>> rank and bus width.
>>
>> It's a bummer that this auto detection doesn't work, it looked to be the
>> right thing.
>> But I prefer functionality over pipe dreams ;-)
>>
>>>
>>> Tested-by: Thomas Graichen <thomas.graichen at googlemail.com>
>>> Signed-off-by: Jernej Skrabec <jernej.skrabec at siol.net>

...

>>> +static void mctl_auto_detect_rank_width(struct dram_para *para)
>>> +{
>>> +	/* this is minimum size that it's supported */
>>> +	para->cols = 8;
>>> +	para->rows = 13;
>>> +
>>> +	/*
>>
>> Can you add here that former versions of this code tried to autodetect
>> rank and width, but this didn't work reliably? This would give people
>> some breadcrumbs to follow with git log/git annotate.
>>
>> Otherwise this is fine:
>>
>> Reviewed-by: Andre Przywara <andre.przywara at arm.com>
>> Tested-by: Andre Przywara <andre.przywara at arm.com> (on Pine H64)
>>
>> I can extend the commit while committing, if you like.
> 
> Please do. Thanks!

Done and applied!

Thanks,
Andre