[PATCH v2] rockchip: rk3328: Add support for FriendlyARM NanoPi R2S
Kever Yang
kever.yang at rock-chips.com
Thu Jan 21 04:58:29 CET 2021
On 2021/1/7 上午7:06, David Bauer wrote:
> This adds support for the NanoPi R2S from FriendlyArm.
>
> Rockchip RK3328 SoC
> 1GB DDR4 RAM
> Gigabit Ethernet (WAN)
> Gigabit Ethernet (USB3) (LAN)
> USB 2.0 Host Port
> MicroSD slot
> Reset button
> WAN - LAN - SYS LED
>
> Signed-off-by: David Bauer <mail at david-bauer.net>
Reviewed-by: Kever Yang<kever.yang at rock-chips.com>
Thanks,
- Kever
> ---
> arch/arm/dts/Makefile | 1 +
> arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi | 40 +++
> arch/arm/dts/rk3328-nanopi-r2s.dts | 370 +++++++++++++++++++++
> board/rockchip/evb_rk3328/MAINTAINERS | 7 +
> configs/nanopi-r2s-rk3328_defconfig | 98 ++++++
> 5 files changed, 516 insertions(+)
> create mode 100644 arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
> create mode 100644 arch/arm/dts/rk3328-nanopi-r2s.dts
> create mode 100644 configs/nanopi-r2s-rk3328_defconfig
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index fd47e408f8..ea5b5586cc 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -110,6 +110,7 @@ dtb-$(CONFIG_ROCKCHIP_RK3308) += \
>
> dtb-$(CONFIG_ROCKCHIP_RK3328) += \
> rk3328-evb.dtb \
> + rk3328-nanopi-r2s.dtb \
> rk3328-roc-cc.dtb \
> rk3328-rock64.dtb \
> rk3328-rock-pi-e.dtb
> diff --git a/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
> new file mode 100644
> index 0000000000..9e2ced1541
> --- /dev/null
> +++ b/arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
> @@ -0,0 +1,40 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * (C) Copyright 2018-2019 Rockchip Electronics Co., Ltd
> + * (C) Copyright 2020 David Bauer
> + */
> +
> +#include "rk3328-u-boot.dtsi"
> +#include "rk3328-sdram-ddr4-666.dtsi"
> +/ {
> + chosen {
> + u-boot,spl-boot-order = "same-as-spl", &sdmmc, &emmc;
> + };
> +};
> +
> +&gpio0 {
> + u-boot,dm-spl;
> +};
> +
> +&pinctrl {
> + u-boot,dm-spl;
> +};
> +
> +&sdmmc0m1_gpio {
> + u-boot,dm-spl;
> +};
> +
> +&pcfg_pull_up_4ma {
> + u-boot,dm-spl;
> +};
> +
> +/* Need this and all the pinctrl/gpio stuff above to set pinmux */
> +&vcc_sd {
> + u-boot,dm-spl;
> +};
> +
> +&gmac2io {
> + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
> + snps,reset-active-low;
> + snps,reset-delays-us = <0 10000 50000>;
> +};
> diff --git a/arch/arm/dts/rk3328-nanopi-r2s.dts b/arch/arm/dts/rk3328-nanopi-r2s.dts
> new file mode 100644
> index 0000000000..5445c5cb3d
> --- /dev/null
> +++ b/arch/arm/dts/rk3328-nanopi-r2s.dts
> @@ -0,0 +1,370 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 David Bauer <mail at david-bauer.net>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include "rk3328.dtsi"
> +
> +/ {
> + model = "FriendlyElec NanoPi R2S";
> + compatible = "friendlyarm,nanopi-r2s", "rockchip,rk3328";
> +
> + chosen {
> + stdout-path = "serial2:1500000n8";
> + };
> +
> + gmac_clk: gmac-clock {
> + compatible = "fixed-clock";
> + clock-frequency = <125000000>;
> + clock-output-names = "gmac_clkin";
> + #clock-cells = <0>;
> + };
> +
> + keys {
> + compatible = "gpio-keys";
> + pinctrl-0 = <&reset_button_pin>;
> + pinctrl-names = "default";
> +
> + reset {
> + label = "reset";
> + gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_RESTART>;
> + debounce-interval = <50>;
> + };
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
> + pinctrl-names = "default";
> +
> + lan_led: led-0 {
> + gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
> + label = "nanopi-r2s:green:lan";
> + };
> +
> + sys_led: led-1 {
> + gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
> + label = "nanopi-r2s:red:sys";
> + };
> +
> + wan_led: led-2 {
> + gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
> + label = "nanopi-r2s:green:wan";
> + };
> + };
> +
> + vcc_io_sdio: sdmmcio-regulator {
> + compatible = "regulator-gpio";
> + enable-active-high;
> + gpios = <&gpio1 RK_PD4 GPIO_ACTIVE_HIGH>;
> + pinctrl-0 = <&sdio_vcc_pin>;
> + pinctrl-names = "default";
> + regulator-name = "vcc_io_sdio";
> + regulator-always-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-settling-time-us = <5000>;
> + regulator-type = "voltage";
> + startup-delay-us = <2000>;
> + states = <1800000 0x1
> + 3300000 0x0>;
> + vin-supply = <&vcc_io_33>;
> + };
> +
> + vcc_sd: sdmmc-regulator {
> + compatible = "regulator-fixed";
> + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
> + pinctrl-0 = <&sdmmc0m1_gpio>;
> + pinctrl-names = "default";
> + regulator-name = "vcc_sd";
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vcc_io_33>;
> + };
> +
> + vdd_5v: vdd-5v {
> + compatible = "regulator-fixed";
> + regulator-name = "vdd_5v";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&cpu1 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&cpu2 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&cpu3 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&gmac2io {
> + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
> + assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
> + clock_in_out = "input";
> + phy-handle = <&rtl8211e>;
> + phy-mode = "rgmii";
> + phy-supply = <&vcc_io_33>;
> + pinctrl-0 = <&rgmiim1_pins>;
> + pinctrl-names = "default";
> + rx_delay = <0x18>;
> + snps,aal;
> + tx_delay = <0x24>;
> + status = "okay";
> +
> + mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + rtl8211e: ethernet-phy at 1 {
> + compatible = "ethernet-phy-id001c.c915",
> + "ethernet-phy-ieee802.3-c22";
> + reg = <1>;
> + pinctrl-0 = <ð_phy_reset_pin>;
> + pinctrl-names = "default";
> + reset-assert-us = <10000>;
> + reset-deassert-us = <50000>;
> + reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> +
> +&i2c1 {
> + status = "okay";
> +
> + rk805: pmic at 18 {
> + compatible = "rockchip,rk805";
> + reg = <0x18>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
> + #clock-cells = <1>;
> + clock-output-names = "xin32k", "rk805-clkout2";
> + gpio-controller;
> + #gpio-cells = <2>;
> + pinctrl-0 = <&pmic_int_l>;
> + pinctrl-names = "default";
> + rockchip,system-power-controller;
> + wakeup-source;
> +
> + vcc1-supply = <&vdd_5v>;
> + vcc2-supply = <&vdd_5v>;
> + vcc3-supply = <&vdd_5v>;
> + vcc4-supply = <&vdd_5v>;
> + vcc5-supply = <&vcc_io_33>;
> + vcc6-supply = <&vdd_5v>;
> +
> + regulators {
> + vdd_log: DCDC_REG1 {
> + regulator-name = "vdd_log";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <712500>;
> + regulator-max-microvolt = <1450000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1000000>;
> + };
> + };
> +
> + vdd_arm: DCDC_REG2 {
> + regulator-name = "vdd_arm";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <712500>;
> + regulator-max-microvolt = <1450000>;
> + regulator-ramp-delay = <12500>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <950000>;
> + };
> + };
> +
> + vcc_ddr: DCDC_REG3 {
> + regulator-name = "vcc_ddr";
> + regulator-always-on;
> + regulator-boot-on;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + vcc_io_33: DCDC_REG4 {
> + regulator-name = "vcc_io_33";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vcc_18: LDO_REG1 {
> + regulator-name = "vcc_18";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vcc18_emmc: LDO_REG2 {
> + regulator-name = "vcc18_emmc";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vdd_10: LDO_REG3 {
> + regulator-name = "vdd_10";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1000000>;
> + };
> + };
> + };
> + };
> +};
> +
> +&io_domains {
> + pmuio-supply = <&vcc_io_33>;
> + vccio1-supply = <&vcc_io_33>;
> + vccio2-supply = <&vcc18_emmc>;
> + vccio3-supply = <&vcc_io_sdio>;
> + vccio4-supply = <&vcc_18>;
> + vccio5-supply = <&vcc_io_33>;
> + vccio6-supply = <&vcc_io_33>;
> + status = "okay";
> +};
> +
> +&pinctrl {
> + button {
> + reset_button_pin: reset-button-pin {
> + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + ethernet-phy {
> + eth_phy_reset_pin: eth-phy-reset-pin {
> + rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
> + };
> + };
> +
> + leds {
> + lan_led_pin: lan-led-pin {
> + rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + sys_led_pin: sys-led-pin {
> + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> +
> + wan_led_pin: wan-led-pin {
> + rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + pmic {
> + pmic_int_l: pmic-int-l {
> + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +
> + sd {
> + sdio_vcc_pin: sdio-vcc-pin {
> + rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +};
> +
> +&pwm2 {
> + status = "okay";
> +};
> +
> +&sdmmc {
> + bus-width = <4>;
> + cap-sd-highspeed;
> + disable-wp;
> + pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
> + pinctrl-names = "default";
> + sd-uhs-sdr12;
> + sd-uhs-sdr25;
> + sd-uhs-sdr50;
> + sd-uhs-sdr104;
> + vmmc-supply = <&vcc_sd>;
> + vqmmc-supply = <&vcc_io_sdio>;
> + status = "okay";
> +};
> +
> +&tsadc {
> + rockchip,hw-tshut-mode = <0>;
> + rockchip,hw-tshut-polarity = <0>;
> + status = "okay";
> +};
> +
> +&u2phy {
> + status = "okay";
> +};
> +
> +&u2phy_host {
> + status = "okay";
> +};
> +
> +&u2phy_otg {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&usb20_otg {
> + status = "okay";
> + dr_mode = "host";
> +};
> +
> +&usb_host0_ehci {
> + status = "okay";
> +};
> +
> +&usb_host0_ohci {
> + status = "okay";
> +};
> diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS
> index e7dd59ff4e..14fda46e8f 100644
> --- a/board/rockchip/evb_rk3328/MAINTAINERS
> +++ b/board/rockchip/evb_rk3328/MAINTAINERS
> @@ -5,6 +5,13 @@ F: board/rockchip/evb_rk3328
> F: include/configs/evb_rk3328.h
> F: configs/evb-rk3328_defconfig
>
> +NANOPI-R2S-RK3328
> +M: David Bauer <mail at david-bauer.net>
> +S: Maintained
> +F: configs/nanopi-r2s-rk3328_defconfig
> +F: arch/arm/dts/rk3328-nanopi-r2s-u-boot.dtsi
> +F: arch/arm/dts/rk3328-nanopi-r2s.dts
> +
> ROC-RK3328-CC
> M: Loic Devulder <ldevulder at suse.com>
> M: Chen-Yu Tsai <wens at csie.org>
> diff --git a/configs/nanopi-r2s-rk3328_defconfig b/configs/nanopi-r2s-rk3328_defconfig
> new file mode 100644
> index 0000000000..2f67439f78
> --- /dev/null
> +++ b/configs/nanopi-r2s-rk3328_defconfig
> @@ -0,0 +1,98 @@
> +CONFIG_ARM=y
> +CONFIG_ARCH_ROCKCHIP=y
> +CONFIG_SYS_TEXT_BASE=0x00200000
> +CONFIG_SPL_GPIO_SUPPORT=y
> +CONFIG_ENV_OFFSET=0x3F8000
> +CONFIG_ROCKCHIP_RK3328=y
> +CONFIG_TPL_ROCKCHIP_COMMON_BOARD=y
> +CONFIG_TPL_LIBCOMMON_SUPPORT=y
> +CONFIG_TPL_LIBGENERIC_SUPPORT=y
> +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
> +CONFIG_SPL_STACK_R_ADDR=0x600000
> +CONFIG_NR_DRAM_BANKS=1
> +CONFIG_DEBUG_UART_BASE=0xFF130000
> +CONFIG_DEBUG_UART_CLOCK=24000000
> +CONFIG_SYSINFO=y
> +CONFIG_DEBUG_UART=y
> +CONFIG_TPL_SYS_MALLOC_F_LEN=0x800
> +# CONFIG_ANDROID_BOOT_IMAGE is not set
> +CONFIG_FIT=y
> +CONFIG_FIT_VERBOSE=y
> +CONFIG_SPL_LOAD_FIT=y
> +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-nanopi-r2s.dtb"
> +CONFIG_MISC_INIT_R=y
> +# CONFIG_DISPLAY_CPUINFO is not set
> +CONFIG_DISPLAY_BOARDINFO_LATE=y
> +# CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
> +CONFIG_TPL_SYS_MALLOC_SIMPLE=y
> +CONFIG_SPL_STACK_R=y
> +CONFIG_SPL_I2C_SUPPORT=y
> +CONFIG_SPL_POWER_SUPPORT=y
> +CONFIG_SPL_ATF=y
> +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y
> +CONFIG_CMD_BOOTZ=y
> +CONFIG_CMD_GPT=y
> +CONFIG_CMD_MMC=y
> +CONFIG_CMD_USB=y
> +# CONFIG_CMD_SETEXPR is not set
> +CONFIG_CMD_TIME=y
> +CONFIG_SPL_OF_CONTROL=y
> +CONFIG_TPL_OF_CONTROL=y
> +CONFIG_DEFAULT_DEVICE_TREE="rk3328-nanopi-r2s"
> +CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
> +CONFIG_TPL_OF_PLATDATA=y
> +CONFIG_ENV_IS_IN_MMC=y
> +CONFIG_SYS_RELOC_GD_ENV_ADDR=y
> +CONFIG_NET_RANDOM_ETHADDR=y
> +CONFIG_TPL_DM=y
> +CONFIG_REGMAP=y
> +CONFIG_SPL_REGMAP=y
> +CONFIG_TPL_REGMAP=y
> +CONFIG_SYSCON=y
> +CONFIG_SPL_SYSCON=y
> +CONFIG_TPL_SYSCON=y
> +CONFIG_CLK=y
> +CONFIG_SPL_CLK=y
> +CONFIG_FASTBOOT_BUF_ADDR=0x800800
> +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
> +CONFIG_ROCKCHIP_GPIO=y
> +CONFIG_SYS_I2C_ROCKCHIP=y
> +CONFIG_MMC_DW=y
> +CONFIG_MMC_DW_ROCKCHIP=y
> +CONFIG_SF_DEFAULT_SPEED=20000000
> +CONFIG_DM_ETH=y
> +CONFIG_ETH_DESIGNWARE=y
> +CONFIG_GMAC_ROCKCHIP=y
> +CONFIG_PINCTRL=y
> +CONFIG_SPL_PINCTRL=y
> +CONFIG_DM_PMIC=y
> +CONFIG_PMIC_RK8XX=y
> +CONFIG_SPL_DM_REGULATOR=y
> +CONFIG_REGULATOR_PWM=y
> +CONFIG_DM_REGULATOR_FIXED=y
> +CONFIG_SPL_DM_REGULATOR_FIXED=y
> +CONFIG_REGULATOR_RK8XX=y
> +CONFIG_PWM_ROCKCHIP=y
> +CONFIG_RAM=y
> +CONFIG_SPL_RAM=y
> +CONFIG_TPL_RAM=y
> +CONFIG_DM_RESET=y
> +CONFIG_BAUDRATE=1500000
> +CONFIG_DEBUG_UART_SHIFT=2
> +CONFIG_SYSRESET=y
> +# CONFIG_TPL_SYSRESET is not set
> +CONFIG_USB=y
> +CONFIG_USB_XHCI_HCD=y
> +CONFIG_USB_XHCI_DWC3=y
> +CONFIG_USB_EHCI_HCD=y
> +CONFIG_USB_EHCI_GENERIC=y
> +CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_GENERIC=y
> +CONFIG_USB_DWC2=y
> +CONFIG_USB_DWC3=y
> +# CONFIG_USB_DWC3_GADGET is not set
> +CONFIG_USB_GADGET=y
> +CONFIG_USB_GADGET_DWC2_OTG=y
> +CONFIG_SPL_TINY_MEMSET=y
> +CONFIG_TPL_TINY_MEMSET=y
> +CONFIG_ERRNO_STR=y
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