[PATCH 11/11] test: pinmux: add test for 'pinctrl-single' driver

Dario Binacchi dariobin at libero.it
Sat Jan 23 19:27:11 CET 2021


The test adds two pinmux nodes to the device tree, one to test when a
register changes only one pin's mux (pinctrl-single,pins), and the other
to test when more than one pin's mux is changed (pinctrl-single,bits).
This required replacing the controller's register access functions when
the driver is used on sandbox.

Signed-off-by: Dario Binacchi <dariobin at libero.it>

---

 arch/sandbox/dts/test.dts        | 65 +++++++++++++++++++++++++
 configs/sandbox_defconfig        |  1 +
 drivers/pinctrl/pinctrl-single.c | 62 +++++++++++++++++++-----
 test/dm/pinmux.c                 | 81 ++++++++++++++++++++++++++++++--
 4 files changed, 193 insertions(+), 16 deletions(-)

diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts
index f86cd0d3b2..e00a163641 100644
--- a/arch/sandbox/dts/test.dts
+++ b/arch/sandbox/dts/test.dts
@@ -513,6 +513,9 @@
 		reg = <0 1>;
 		compatible = "sandbox,i2c";
 		clock-frequency = <100000>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_i2c0_pins>;
+
 		eeprom at 2c {
 			reg = <0x2c>;
 			compatible = "i2c-eeprom";
@@ -592,6 +595,8 @@
 	lcd {
 		u-boot,dm-pre-reloc;
 		compatible = "sandbox,lcd-sdl";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_lcd_pins>;
 		xres = <1366>;
 		yres = <768>;
 	};
@@ -842,6 +847,8 @@
 	pwm: pwm {
 		compatible = "sandbox,pwm";
 		#pwm-cells = <2>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_pwm_pins>;
 	};
 
 	pwm2 {
@@ -913,6 +920,9 @@
 		reg = <0 1>;
 		compatible = "sandbox,spi";
 		cs-gpios = <0>, <0>, <&gpio_a 0>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_spi0_pins>;
+
 		spi.bin at 0 {
 			reg = <0>;
 			compatible = "spansion,m25p16", "jedec,spi-nor";
@@ -1002,6 +1012,8 @@
 	uart0: serial {
 		compatible = "sandbox,serial";
 		u-boot,dm-pre-reloc;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinmux_uart0_pins>;
 	};
 
 	usb_0: usb at 0 {
@@ -1268,6 +1280,59 @@
 		};
 	};
 
+	pinctrl-single-pins {
+		compatible = "pinctrl-single";
+		reg = <0x0000 0x238>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x7f>;
+
+		pinmux_pwm_pins: pinmux_pwm_pins {
+			pinctrl-single,pins = < 0x48 0x06 >;
+		};
+
+		pinmux_spi0_pins: pinmux_spi0_pins {
+			pinctrl-single,pins = <
+				0x190 0x0c
+				0x194 0x0c
+				0x198 0x23
+				0x19c 0x0c
+			>;
+		};
+
+		pinmux_uart0_pins: pinmux_uart0_pins {
+			pinctrl-single,pins = <
+				0x70 0x30
+				0x74 0x00
+			>;
+		};
+	};
+
+	pinctrl-single-bits {
+		compatible = "pinctrl-single";
+		reg = <0x0000 0x50>;
+		#pinctrl-cells = <2>;
+		pinctrl-single,bit-per-mux;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0xf>;
+
+		pinmux_i2c0_pins: pinmux_i2c0_pins {
+			pinctrl-single,bits = <
+				0x10 0x00002200 0x0000ff00
+			>;
+		};
+
+		pinmux_lcd_pins: pinmux_lcd_pins {
+			pinctrl-single,bits = <
+				0x40 0x22222200 0xffffff00
+				0x44 0x22222222 0xffffffff
+				0x48 0x00000022 0x000000ff
+				0x48 0x02000000 0x0f000000
+				0x4c 0x02000022 0x0f0000ff
+			>;
+		};
+	};
+
 	hwspinlock at 0 {
 		compatible = "sandbox,hwspinlock";
 	};
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index 86dc603667..1c7d49f073 100644
--- a/configs/sandbox_defconfig
+++ b/configs/sandbox_defconfig
@@ -193,6 +193,7 @@ CONFIG_PHY_SANDBOX=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_SANDBOX=y
+CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_SANDBOX_POWER_DOMAIN=y
 CONFIG_DM_PMIC=y
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 8db0d9e3d1..0efffd48e7 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -53,12 +53,15 @@ struct single_func {
  * @write: function to write to a configuration register
  */
 struct single_priv {
+#if (IS_ENABLED(CONFIG_SANDBOX))
+	u32 *sandbox_regs;
+#endif
 	unsigned int bits_per_pin;
 	unsigned int npins;
 	char pin_name[PINNAME_SIZE];
 	struct list_head functions;
-	unsigned int (*read)(fdt_addr_t reg);
-	void (*write)(unsigned int val, fdt_addr_t reg);
+	unsigned int (*read)(struct udevice *dev, fdt_addr_t reg);
+	void (*write)(struct udevice *dev, unsigned int val, fdt_addr_t reg);
 };
 
 /**
@@ -91,36 +94,64 @@ struct single_fdt_bits_cfg {
 	fdt32_t mask;
 };
 
-static unsigned int single_readb(fdt_addr_t reg)
+#if (!IS_ENABLED(CONFIG_SANDBOX))
+
+static unsigned int single_readb(struct udevice *dev, fdt_addr_t reg)
 {
 	return readb(reg);
 }
 
-static unsigned int single_readw(fdt_addr_t reg)
+static unsigned int single_readw(struct udevice *dev, fdt_addr_t reg)
 {
 	return readw(reg);
 }
 
-static unsigned int single_readl(fdt_addr_t reg)
+static unsigned int single_readl(struct udevice *dev, fdt_addr_t reg)
 {
 	return readl(reg);
 }
 
-static void single_writeb(unsigned int val, fdt_addr_t reg)
+static void single_writeb(struct udevice *dev, unsigned int val, fdt_addr_t reg)
 {
 	writeb(val, reg);
 }
 
-static void single_writew(unsigned int val, fdt_addr_t reg)
+static void single_writew(struct udevice *dev, unsigned int val, fdt_addr_t reg)
 {
 	writew(val, reg);
 }
 
-static void single_writel(unsigned int val, fdt_addr_t reg)
+static void single_writel(struct udevice *dev, unsigned int val, fdt_addr_t reg)
 {
 	writel(val, reg);
 }
 
+#else /* CONFIG_SANDBOX  */
+
+#define single_readb		single_sandbox_read
+#define single_readw		single_sandbox_read
+#define single_readl		single_sandbox_read
+#define single_writeb		single_sandbox_write
+#define single_writew		single_sandbox_write
+#define single_writel		single_sandbox_write
+
+static unsigned int single_sandbox_read(struct udevice *dev, fdt_addr_t reg)
+{
+	struct single_priv *priv = dev_get_priv(dev);
+
+	return priv->sandbox_regs[reg];
+}
+
+static void single_sandbox_write(struct udevice *dev, unsigned int val,
+				 fdt_addr_t reg)
+{
+	struct single_priv *priv = dev_get_priv(dev);
+
+	priv->sandbox_regs[reg] = val;
+}
+
+#endif /* CONFIG_SANDBOX  */
+
 /**
  * single_get_pin_by_offset() - get a pin based on the register offset
  * @dev: single driver instance
@@ -198,7 +229,7 @@ static int single_get_pin_muxing(struct udevice *dev, unsigned int pin,
 		return offset;
 
 	reg = pdata->base + offset;
-	val = priv->read(reg);
+	val = priv->read(dev, reg);
 
 	if (pdata->bits_per_mux)
 		pin_shift = pin % (pdata->width / priv->bits_per_pin) *
@@ -289,7 +320,8 @@ static int single_configure_pins(struct udevice *dev,
 			continue;
 		}
 
-		priv->write((priv->read(reg) & ~pdata->mask) | val, reg);
+		priv->write(dev, (priv->read(dev, reg) & ~pdata->mask) | val,
+			    reg);
 		dev_dbg(dev, "  reg/val %pa/0x%08x\n", &reg, val);
 		func->pins[func->npins] = pin;
 		func->npins++;
@@ -339,7 +371,7 @@ static int single_configure_bits(struct udevice *dev,
 
 		mask = fdt32_to_cpu(pins->mask);
 		val = fdt32_to_cpu(pins->val) & mask;
-		priv->write((priv->read(reg) & ~mask) | val, reg);
+		priv->write(dev, (priv->read(dev, reg) & ~mask) | val, reg);
 		dev_dbg(dev, "  reg/val %pa/0x%08x\n", &reg, val);
 
 		while (mask) {
@@ -437,6 +469,14 @@ static int single_probe(struct udevice *dev)
 	INIT_LIST_HEAD(&priv->functions);
 
 	size = pdata->offset + pdata->width / BITS_PER_BYTE;
+	#if (CONFIG_IS_ENABLED(SANDBOX))
+	priv->sandbox_regs =
+		devm_kzalloc(dev, size * sizeof(*priv->sandbox_regs),
+			     GFP_KERNEL);
+	if (!priv->sandbox_regs)
+		return -ENOMEM;
+	#endif
+
 	priv->npins = size / (pdata->width / BITS_PER_BYTE);
 	if (pdata->bits_per_mux) {
 		priv->bits_per_pin = fls(pdata->mask);
diff --git a/test/dm/pinmux.c b/test/dm/pinmux.c
index 047184d4bc..db3f14bf7d 100644
--- a/test/dm/pinmux.c
+++ b/test/dm/pinmux.c
@@ -9,16 +9,21 @@
 #include <dm/test.h>
 #include <test/ut.h>
 
-static int dm_test_pinmux(struct unit_test_state *uts)
-{
-	char buf[64];
-	struct udevice *dev;
-
+static char buf[64];
 #define test_muxing(selector, expected) do { \
 	ut_assertok(pinctrl_get_pin_muxing(dev, selector, buf, sizeof(buf))); \
 	ut_asserteq_str(expected, (char *)&buf); \
 } while (0)
 
+#define test_name(selector, expected) do { \
+	ut_assertok(pinctrl_get_pin_name(dev, selector, buf, sizeof(buf))); \
+	ut_asserteq_str(expected, (char *)&buf); \
+} while (0)
+
+static int dm_test_pinmux(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+
 	ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, "pinctrl", &dev));
 	test_muxing(0, "UART TX.");
 	test_muxing(1, "UART RX.");
@@ -55,3 +60,69 @@ static int dm_test_pinmux(struct unit_test_state *uts)
 	return 0;
 }
 DM_TEST(dm_test_pinmux, UT_TESTF_SCAN_FDT);
+
+static int dm_test_pinctrl_single(struct unit_test_state *uts)
+{
+	struct udevice *dev;
+
+	ut_assertok(uclass_get_device_by_name(UCLASS_PWM, "pwm", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_SERIAL, "serial", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_SPI, "spi at 0", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, "pinctrl-single-pins", &dev));
+	ut_asserteq(142, pinctrl_get_pins_count(dev));
+	test_name(0, "PIN0");
+	test_name(141, "PIN141");
+	test_name(142, "Error");
+	test_muxing(0, "0x00000000 0x00000000 UNCLAIMED");
+	test_muxing(18, "0x00000048 0x00000006 pinmux_pwm_pins");
+	test_muxing(28, "0x00000070 0x00000030 pinmux_uart0_pins");
+	test_muxing(29, "0x00000074 0x00000000 pinmux_uart0_pins");
+	test_muxing(100, "0x00000190 0x0000000c pinmux_spi0_pins");
+	test_muxing(101, "0x00000194 0x0000000c pinmux_spi0_pins");
+	test_muxing(102, "0x00000198 0x00000023 pinmux_spi0_pins");
+	test_muxing(103, "0x0000019c 0x0000000c pinmux_spi0_pins");
+	ut_asserteq(-EINVAL, pinctrl_get_pin_muxing(dev, 142, buf, sizeof(buf)));
+	ut_assertok(uclass_get_device_by_name(UCLASS_I2C, "i2c at 0", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_VIDEO, "lcd", &dev));
+	ut_assertok(uclass_get_device_by_name(UCLASS_PINCTRL, "pinctrl-single-bits", &dev));
+	ut_asserteq(160, pinctrl_get_pins_count(dev));
+	test_name(0, "PIN0");
+	test_name(159, "PIN159");
+	test_name(160, "Error");
+	test_muxing(0, "0x00000000 0x00000000 UNCLAIMED");
+	test_muxing(34, "0x00000010 0x00000200 pinmux_i2c0_pins");
+	test_muxing(35, "0x00000010 0x00002000 pinmux_i2c0_pins");
+	test_muxing(130, "0x00000040 0x00000200 pinmux_lcd_pins");
+	test_muxing(131, "0x00000040 0x00002000 pinmux_lcd_pins");
+	test_muxing(132, "0x00000040 0x00020000 pinmux_lcd_pins");
+	test_muxing(133, "0x00000040 0x00200000 pinmux_lcd_pins");
+	test_muxing(134, "0x00000040 0x02000000 pinmux_lcd_pins");
+	test_muxing(135, "0x00000040 0x20000000 pinmux_lcd_pins");
+	test_muxing(136, "0x00000044 0x00000002 pinmux_lcd_pins");
+	test_muxing(137, "0x00000044 0x00000020 pinmux_lcd_pins");
+	test_muxing(138, "0x00000044 0x00000200 pinmux_lcd_pins");
+	test_muxing(139, "0x00000044 0x00002000 pinmux_lcd_pins");
+	test_muxing(140, "0x00000044 0x00020000 pinmux_lcd_pins");
+	test_muxing(141, "0x00000044 0x00200000 pinmux_lcd_pins");
+	test_muxing(142, "0x00000044 0x02000000 pinmux_lcd_pins");
+	test_muxing(143, "0x00000044 0x20000000 pinmux_lcd_pins");
+	test_muxing(144, "0x00000048 0x00000002 pinmux_lcd_pins");
+	test_muxing(145, "0x00000048 0x00000020 pinmux_lcd_pins");
+	test_muxing(146, "0x00000048 0x00000000 UNCLAIMED");
+	test_muxing(147, "0x00000048 0x00000000 UNCLAIMED");
+	test_muxing(148, "0x00000048 0x00000000 UNCLAIMED");
+	test_muxing(149, "0x00000048 0x00000000 UNCLAIMED");
+	test_muxing(150, "0x00000048 0x02000000 pinmux_lcd_pins");
+	test_muxing(151, "0x00000048 0x00000000 UNCLAIMED");
+	test_muxing(152, "0x0000004c 0x00000002 pinmux_lcd_pins");
+	test_muxing(153, "0x0000004c 0x00000020 pinmux_lcd_pins");
+	test_muxing(154, "0x0000004c 0x00000000 UNCLAIMED");
+	test_muxing(155, "0x0000004c 0x00000000 UNCLAIMED");
+	test_muxing(156, "0x0000004c 0x00000000 UNCLAIMED");
+	test_muxing(157, "0x0000004c 0x00000000 UNCLAIMED");
+	test_muxing(158, "0x0000004c 0x02000000 pinmux_lcd_pins");
+	test_muxing(159, "0x0000004c 0x00000000 UNCLAIMED");
+	ut_asserteq(-EINVAL, pinctrl_get_pin_muxing(dev, 160, buf, sizeof(buf)));
+	return 0;
+}
+DM_TEST(dm_test_pinctrl_single, UT_TESTF_SCAN_FDT);
-- 
2.17.1



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