[PATCH v2 18/21] arm: sunxi: add initial H616 DTSI and headers
Andre Przywara
andre.przywara at arm.com
Sun Jan 24 03:17:30 CET 2021
On Mon, 11 Jan 2021 21:11:50 +0100
Jernej Skrabec <jernej.skrabec at siol.net> wrote:
Hi,
> This commit introduces H616 DTSI file and dt-bindings headers needed for
> device tree files.
>
> Files are taken from initial Linux H616 support submission with minor
> change - emac0 fallback has H6 compatible instead of A64, otherwise
> network doesn't work. H616 DTSI is not merged upstream yet.
So I updated to this the the v3 version, putting a link in the commit
message. Also I dropped the emac compatible change, this should be
covered by a U-Boot driver fix (which I will repost shortly).
Regarding the preliminary nature of the DT: This is probably the best we
can get now, so I don't want to block U-Boot support on the Linux DT
acceptance at this stage of development. U-Boot support is also crucial
for kernel development and testing, so this is somewhat of a chicken-egg
problem. We can update the U-Boot DTs at any time later.
> Signed-off-by: Jernej Skrabec <jernej.skrabec at siol.net>
Confirmed to be the version from the Linux patches, so:
Reviewed-by: Andre Przywara <andre.przywara at arm.com>
Cheers,
Andre
> ---
> arch/arm/dts/sun50i-h616.dtsi | 716 ++++++++++++++++++++
> include/dt-bindings/clock/sun50i-h616-ccu.h | 115 ++++
> include/dt-bindings/reset/sun50i-h616-ccu.h | 70 ++
> 3 files changed, 901 insertions(+)
> create mode 100644 arch/arm/dts/sun50i-h616.dtsi
> create mode 100644 include/dt-bindings/clock/sun50i-h616-ccu.h
> create mode 100644 include/dt-bindings/reset/sun50i-h616-ccu.h
>
> diff --git a/arch/arm/dts/sun50i-h616.dtsi b/arch/arm/dts/sun50i-h616.dtsi
> new file mode 100644
> index 000000000000..d416e9a3d3e6
> --- /dev/null
> +++ b/arch/arm/dts/sun50i-h616.dtsi
> @@ -0,0 +1,716 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +// Copyright (C) 2020 Arm Ltd.
> +// based on the H6 dtsi, which is:
> +// Copyright (C) 2017 Icenowy Zheng <icenowy at aosc.io>
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/clock/sun50i-h616-ccu.h>
> +#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
> +#include <dt-bindings/reset/sun50i-h616-ccu.h>
> +#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu at 0 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <0>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu1: cpu at 1 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <1>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu2: cpu at 2 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <2>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> +
> + cpu3: cpu at 3 {
> + compatible = "arm,cortex-a53";
> + device_type = "cpu";
> + reg = <3>;
> + enable-method = "psci";
> + clocks = <&ccu CLK_CPUX>;
> + };
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* 512KiB reserved for ARM Trusted Firmware (BL31) */
> + secmon_reserved: secmon at 40000000 {
> + reg = <0x0 0x40000000 0x0 0x80000>;
> + no-map;
> + };
> + };
> +
> + osc24M: osc24M_clk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "osc24M";
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + arm,no-tick-in-suspend;
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x40000000>;
> +
> + syscon: syscon at 3000000 {
> + compatible = "allwinner,sun50i-h616-system-control";
> + reg = <0x03000000 0x1000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + sram_c: sram at 28000 {
> + compatible = "mmio-sram";
> + reg = <0x00028000 0x30000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x00028000 0x30000>;
> + };
> + };
> +
> + ccu: clock at 3001000 {
> + compatible = "allwinner,sun50i-h616-ccu";
> + reg = <0x03001000 0x1000>;
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>;
> + clock-names = "hosc", "losc", "iosc";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + watchdog: watchdog at 30090a0 {
> + compatible = "allwinner,sun50i-h616-wdt",
> + "allwinner,sun6i-a31-wdt";
> + reg = <0x030090a0 0x20>;
> + interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc24M>;
> + status = "disabled";
> + };
> +
> + pio: pinctrl at 300b000 {
> + compatible = "allwinner,sun50i-h616-pinctrl";
> + reg = <0x0300b000 0x400>;
> + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_APB1>, <&osc24M>, <&rtc 0>;
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + ext_rgmii_pins: rgmii-pins {
> + pins = "PI0", "PI1", "PI2", "PI3", "PI4",
> + "PI5", "PI7", "PI8", "PI9", "PI10",
> + "PI11", "PI12", "PI13", "PI14", "PI15",
> + "PI16";
> + function = "emac0";
> + drive-strength = <40>;
> + };
> +
> + i2c0_pins: i2c0-pins {
> + pins = "PI6", "PI7";
> + function = "i2c0";
> + };
> +
> + i2c3_ph_pins: i2c3-ph-pins {
> + pins = "PH4", "PH5";
> + function = "i2c3";
> + };
> +
> + ir_rx_pin: ir_rx_pin {
> + pins = "PH10";
> + function = "ir_rx";
> + };
> +
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3",
> + "PF4", "PF5";
> + function = "mmc0";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + mmc1_pins: mmc1-pins {
> + pins = "PG0", "PG1", "PG2", "PG3",
> + "PG4", "PG5";
> + function = "mmc1";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + mmc2_pins: mmc2-pins {
> + pins = "PC0", "PC1", "PC5", "PC6",
> + "PC8", "PC9", "PC10", "PC11",
> + "PC13", "PC14", "PC15", "PC16";
> + function = "mmc2";
> + drive-strength = <30>;
> + bias-pull-up;
> + };
> +
> + spi0_pins: spi0-pins {
> + pins = "PC0", "PC2", "PC3", "PC4";
> + function = "spi0";
> + };
> +
> + spi1_pins: spi1-pins {
> + pins = "PH6", "PH7", "PH8";
> + function = "spi1";
> + };
> +
> + spi1_cs_pin: spi1-cs-pin {
> + pins = "PH5";
> + function = "spi1";
> + };
> +
> + uart0_ph_pins: uart0-ph-pins {
> + pins = "PH0", "PH1";
> + function = "uart0";
> + };
> +
> + uart1_pins: uart1-pins {
> + pins = "PG6", "PG7";
> + function = "uart1";
> + };
> +
> + uart1_rts_cts_pins: uart1-rts-cts-pins {
> + pins = "PG8", "PG9";
> + function = "uart1";
> + };
> + };
> +
> + gic: interrupt-controller at 3021000 {
> + compatible = "arm,gic-400";
> + reg = <0x03021000 0x1000>,
> + <0x03022000 0x2000>,
> + <0x03024000 0x2000>,
> + <0x03026000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + };
> +
> + mmc0: mmc at 4020000 {
> + compatible = "allwinner,sun50i-h616-mmc",
> + "allwinner,sun50i-a100-mmc";
> + reg = <0x04020000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc at 4021000 {
> + compatible = "allwinner,sun50i-h616-mmc",
> + "allwinner,sun50i-a100-mmc";
> + reg = <0x04021000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc1_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc2: mmc at 4022000 {
> + compatible = "allwinner,sun50i-h616-emmc",
> + "allwinner,sun50i-a100-emmc";
> + reg = <0x04022000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
> + clock-names = "ahb", "mmc";
> + resets = <&ccu RST_BUS_MMC2>;
> + reset-names = "ahb";
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc2_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + uart0: serial at 5000000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000000 0x400>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> + status = "disabled";
> + };
> +
> + uart1: serial at 5000400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000400 0x400>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> + status = "disabled";
> + };
> +
> + uart2: serial at 5000800 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000800 0x400>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> + status = "disabled";
> + };
> +
> + uart3: serial at 5000c00 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05000c00 0x400>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART3>;
> + resets = <&ccu RST_BUS_UART3>;
> + status = "disabled";
> + };
> +
> + uart4: serial at 5001000 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05001000 0x400>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART4>;
> + resets = <&ccu RST_BUS_UART4>;
> + status = "disabled";
> + };
> +
> + uart5: serial at 5001400 {
> + compatible = "snps,dw-apb-uart";
> + reg = <0x05001400 0x400>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + clocks = <&ccu CLK_BUS_UART5>;
> + resets = <&ccu RST_BUS_UART5>;
> + status = "disabled";
> + };
> +
> + i2c0: i2c at 5002000 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002000 0x400>;
> + interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C0>;
> + resets = <&ccu RST_BUS_I2C0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c1: i2c at 5002400 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002400 0x400>;
> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C1>;
> + resets = <&ccu RST_BUS_I2C1>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c2: i2c at 5002800 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002800 0x400>;
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C2>;
> + resets = <&ccu RST_BUS_I2C2>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c3: i2c at 5002c00 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05002c00 0x400>;
> + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C3>;
> + resets = <&ccu RST_BUS_I2C3>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + i2c4: i2c at 5003000 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x05003000 0x400>;
> + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_I2C4>;
> + resets = <&ccu RST_BUS_I2C4>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi0: spi at 5010000 {
> + compatible = "allwinner,sun50i-h616-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x05010000 0x1000>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + spi1: spi at 5011000 {
> + compatible = "allwinner,sun50i-h616-spi",
> + "allwinner,sun8i-h3-spi";
> + reg = <0x05011000 0x1000>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
> + clock-names = "ahb", "mod";
> + resets = <&ccu RST_BUS_SPI1>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi1_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + emac0: ethernet at 5020000 {
> + compatible = "allwinner,sun50i-h616-emac",
> + "allwinner,sun50i-h6-emac",
> + "allwinner,sun50i-a64-emac";
> + syscon = <&syscon>;
> + reg = <0x05020000 0x10000>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + resets = <&ccu RST_BUS_EMAC0>;
> + reset-names = "stmmaceth";
> + clocks = <&ccu CLK_BUS_EMAC0>;
> + clock-names = "stmmaceth";
> + status = "disabled";
> +
> + mdio0: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + emac1: ethernet at 5030000 {
> + compatible = "allwinner,sun50i-h616-emac";
> + syscon = <&syscon 1>;
> + reg = <0x05030000 0x10000>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + resets = <&ccu RST_BUS_EMAC1>;
> + reset-names = "stmmaceth";
> + clocks = <&ccu CLK_BUS_EMAC1>;
> + clock-names = "stmmaceth";
> + status = "disabled";
> +
> + mdio1: mdio {
> + compatible = "snps,dwmac-mdio";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + usbotg: usb at 5100000 {
> + compatible = "allwinner,sun50i-h616-musb",
> + "allwinner,sun8i-h3-musb";
> + reg = <0x05100000 0x0400>;
> + clocks = <&ccu CLK_BUS_OTG>;
> + resets = <&ccu RST_BUS_OTG>;
> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "mc";
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + extcon = <&usbphy 0>;
> + status = "disabled";
> + };
> +
> + usbphy: phy at 5100400 {
> + compatible = "allwinner,sun50i-h616-usb-phy";
> + reg = <0x05100400 0x24>,
> + <0x05101800 0x14>,
> + <0x05200800 0x14>,
> + <0x05310800 0x14>,
> + <0x05311800 0x14>;
> + reg-names = "phy_ctrl",
> + "pmu0",
> + "pmu1",
> + "pmu2",
> + "pmu3";
> + clocks = <&ccu CLK_USB_PHY0>,
> + <&ccu CLK_USB_PHY1>,
> + <&ccu CLK_USB_PHY2>,
> + <&ccu CLK_USB_PHY3>;
> + clock-names = "usb0_phy",
> + "usb1_phy",
> + "usb2_phy",
> + "usb3_phy";
> + resets = <&ccu RST_USB_PHY0>,
> + <&ccu RST_USB_PHY1>,
> + <&ccu RST_USB_PHY2>,
> + <&ccu RST_USB_PHY3>;
> + reset-names = "usb0_reset",
> + "usb1_reset",
> + "usb2_reset",
> + "usb3_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ehci0: usb at 5101000 {
> + compatible = "allwinner,sun50i-h616-ehci",
> + "generic-ehci";
> + reg = <0x05101000 0x100>;
> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_BUS_EHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_OHCI0>,
> + <&ccu RST_BUS_EHCI0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci0: usb at 5101400 {
> + compatible = "allwinner,sun50i-h616-ohci",
> + "generic-ohci";
> + reg = <0x05101400 0x100>;
> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI0>,
> + <&ccu CLK_USB_OHCI0>;
> + resets = <&ccu RST_BUS_OHCI0>;
> + phys = <&usbphy 0>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb at 5200000 {
> + compatible = "allwinner,sun50i-h616-ehci",
> + "generic-ehci";
> + reg = <0x05200000 0x100>;
> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_BUS_EHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>,
> + <&ccu RST_BUS_EHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci1: usb at 5200400 {
> + compatible = "allwinner,sun50i-h616-ohci",
> + "generic-ohci";
> + reg = <0x05200400 0x100>;
> + interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci2: usb at 5310000 {
> + compatible = "allwinner,sun50i-h616-ehci",
> + "generic-ehci";
> + reg = <0x05310000 0x100>;
> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI2>,
> + <&ccu CLK_BUS_EHCI2>,
> + <&ccu CLK_USB_OHCI2>;
> + resets = <&ccu RST_BUS_OHCI2>,
> + <&ccu RST_BUS_EHCI2>;
> + phys = <&usbphy 2>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci2: usb at 5310400 {
> + compatible = "allwinner,sun50i-h616-ohci",
> + "generic-ohci";
> + reg = <0x05310400 0x100>;
> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI2>,
> + <&ccu CLK_USB_OHCI2>;
> + resets = <&ccu RST_BUS_OHCI2>;
> + phys = <&usbphy 2>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci3: usb at 5311000 {
> + compatible = "allwinner,sun50i-h616-ehci",
> + "generic-ehci";
> + reg = <0x05311000 0x100>;
> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI3>,
> + <&ccu CLK_BUS_EHCI3>,
> + <&ccu CLK_USB_OHCI3>;
> + resets = <&ccu RST_BUS_OHCI3>,
> + <&ccu RST_BUS_EHCI3>;
> + phys = <&usbphy 3>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ohci3: usb at 5311400 {
> + compatible = "allwinner,sun50i-h616-ohci",
> + "generic-ohci";
> + reg = <0x05311400 0x100>;
> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI3>,
> + <&ccu CLK_USB_OHCI3>;
> + resets = <&ccu RST_BUS_OHCI3>;
> + phys = <&usbphy 3>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + rtc: rtc at 7000000 {
> + compatible = "allwinner,sun50i-h616-rtc",
> + "allwinner,sun50i-h6-rtc";
> + reg = <0x07000000 0x400>;
> + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
> + clock-output-names = "osc32k", "osc32k-out", "iosc";
> + #clock-cells = <1>;
> + };
> +
> + r_ccu: clock at 7010000 {
> + compatible = "allwinner,sun50i-h616-r-ccu";
> + reg = <0x07010000 0x400>;
> + clocks = <&osc24M>, <&rtc 0>, <&rtc 2>,
> + <&ccu CLK_PLL_PERIPH0>;
> + clock-names = "hosc", "losc", "iosc", "pll-periph";
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + r_pio: pinctrl at 7022000 {
> + compatible = "allwinner,sun50i-h616-r-pinctrl";
> + reg = <0x07022000 0x400>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB1>, <&osc24M>, <&rtc 0>;
> + clock-names = "apb", "hosc", "losc";
> + gpio-controller;
> + #gpio-cells = <3>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + r_i2c_pins: r-i2c-pins {
> + pins = "PL0", "PL1";
> + function = "s_i2c";
> + };
> + };
> +
> + ir: ir at 7040000 {
> + compatible = "allwinner,sun50i-h616-ir",
> + "allwinner,sun6i-a31-ir";
> + reg = <0x07040000 0x400>;
> + interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB1_IR>,
> + <&r_ccu CLK_IR>;
> + clock-names = "apb", "ir";
> + resets = <&r_ccu RST_R_APB1_IR>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&ir_rx_pin>;
> + status = "disabled";
> + };
> +
> + r_i2c: i2c at 7081400 {
> + compatible = "allwinner,sun50i-h616-i2c",
> + "allwinner,sun6i-a31-i2c";
> + reg = <0x07081400 0x400>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&r_ccu CLK_R_APB2_I2C>;
> + resets = <&r_ccu RST_R_APB2_I2C>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +};
> diff --git a/include/dt-bindings/clock/sun50i-h616-ccu.h b/include/dt-bindings/clock/sun50i-h616-ccu.h
> new file mode 100644
> index 000000000000..4fc08b0df2f3
> --- /dev/null
> +++ b/include/dt-bindings/clock/sun50i-h616-ccu.h
> @@ -0,0 +1,115 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
> +/*
> + * Copyright (C) 2020 Arm Ltd.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_SUN50I_H616_H_
> +#define _DT_BINDINGS_CLK_SUN50I_H616_H_
> +
> +#define CLK_PLL_PERIPH0 4
> +
> +#define CLK_CPUX 21
> +
> +#define CLK_APB1 26
> +
> +#define CLK_DE 29
> +#define CLK_BUS_DE 30
> +#define CLK_DEINTERLACE 31
> +#define CLK_BUS_DEINTERLACE 32
> +#define CLK_G2D 33
> +#define CLK_BUS_G2D 34
> +#define CLK_GPU0 35
> +#define CLK_BUS_GPU 36
> +#define CLK_GPU1 37
> +#define CLK_CE 38
> +#define CLK_BUS_CE 39
> +#define CLK_VE 40
> +#define CLK_BUS_VE 41
> +#define CLK_BUS_DMA 42
> +#define CLK_BUS_HSTIMER 43
> +#define CLK_AVS 44
> +#define CLK_BUS_DBG 45
> +#define CLK_BUS_PSI 46
> +#define CLK_BUS_PWM 47
> +#define CLK_BUS_IOMMU 48
> +
> +#define CLK_MBUS_DMA 50
> +#define CLK_MBUS_VE 51
> +#define CLK_MBUS_CE 52
> +#define CLK_MBUS_TS 53
> +#define CLK_MBUS_NAND 54
> +#define CLK_MBUS_G2D 55
> +
> +#define CLK_NAND0 57
> +#define CLK_NAND1 58
> +#define CLK_BUS_NAND 59
> +#define CLK_MMC0 60
> +#define CLK_MMC1 61
> +#define CLK_MMC2 62
> +#define CLK_BUS_MMC0 63
> +#define CLK_BUS_MMC1 64
> +#define CLK_BUS_MMC2 65
> +#define CLK_BUS_UART0 66
> +#define CLK_BUS_UART1 67
> +#define CLK_BUS_UART2 68
> +#define CLK_BUS_UART3 69
> +#define CLK_BUS_UART4 70
> +#define CLK_BUS_UART5 71
> +#define CLK_BUS_I2C0 72
> +#define CLK_BUS_I2C1 73
> +#define CLK_BUS_I2C2 74
> +#define CLK_BUS_I2C3 75
> +#define CLK_BUS_I2C4 76
> +#define CLK_SPI0 77
> +#define CLK_SPI1 78
> +#define CLK_BUS_SPI0 79
> +#define CLK_BUS_SPI1 80
> +#define CLK_EMAC_25M 81
> +#define CLK_BUS_EMAC0 82
> +#define CLK_BUS_EMAC1 83
> +#define CLK_TS 84
> +#define CLK_BUS_TS 85
> +#define CLK_BUS_THS 86
> +#define CLK_SPDIF 87
> +#define CLK_BUS_SPDIF 88
> +#define CLK_DMIC 89
> +#define CLK_BUS_DMIC 90
> +#define CLK_AUDIO_CODEC_1X 91
> +#define CLK_AUDIO_CODEC_4X 92
> +#define CLK_BUS_AUDIO_CODEC 93
> +#define CLK_AUDIO_HUB 94
> +#define CLK_BUS_AUDIO_HUB 95
> +#define CLK_USB_OHCI0 96
> +#define CLK_USB_PHY0 97
> +#define CLK_USB_OHCI1 98
> +#define CLK_USB_PHY1 99
> +#define CLK_USB_OHCI2 100
> +#define CLK_USB_PHY2 101
> +#define CLK_USB_OHCI3 102
> +#define CLK_USB_PHY3 103
> +#define CLK_BUS_OHCI0 104
> +#define CLK_BUS_OHCI1 105
> +#define CLK_BUS_OHCI2 106
> +#define CLK_BUS_OHCI3 107
> +#define CLK_BUS_EHCI0 108
> +#define CLK_BUS_EHCI1 109
> +#define CLK_BUS_EHCI2 110
> +#define CLK_BUS_EHCI3 111
> +#define CLK_BUS_OTG 112
> +#define CLK_BUS_KEYADC 113
> +#define CLK_HDMI 114
> +#define CLK_HDMI_SLOW 115
> +#define CLK_HDMI_CEC 116
> +#define CLK_BUS_HDMI 117
> +#define CLK_BUS_TCON_TOP 118
> +#define CLK_TCON_TV0 119
> +#define CLK_TCON_TV1 120
> +#define CLK_BUS_TCON_TV0 121
> +#define CLK_BUS_TCON_TV1 122
> +#define CLK_TVE0 123
> +#define CLK_BUS_TVE_TOP 124
> +#define CLK_BUS_TVE0 125
> +#define CLK_HDCP 126
> +#define CLK_BUS_HDCP 127
> +
> +#endif /* _DT_BINDINGS_CLK_SUN50I_H616_H_ */
> diff --git a/include/dt-bindings/reset/sun50i-h616-ccu.h b/include/dt-bindings/reset/sun50i-h616-ccu.h
> new file mode 100644
> index 000000000000..cb6285a8d128
> --- /dev/null
> +++ b/include/dt-bindings/reset/sun50i-h616-ccu.h
> @@ -0,0 +1,70 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */
> +/*
> + * Copyright (C) 2020 Arm Ltd.
> + */
> +
> +#ifndef _DT_BINDINGS_RESET_SUN50I_H616_H_
> +#define _DT_BINDINGS_RESET_SUN50I_H616_H_
> +
> +#define RST_MBUS 0
> +#define RST_BUS_DE 1
> +#define RST_BUS_DEINTERLACE 2
> +#define RST_BUS_GPU 3
> +#define RST_BUS_CE 4
> +#define RST_BUS_VE 5
> +#define RST_BUS_DMA 6
> +#define RST_BUS_HSTIMER 7
> +#define RST_BUS_DBG 8
> +#define RST_BUS_PSI 9
> +#define RST_BUS_PWM 10
> +#define RST_BUS_IOMMU 11
> +#define RST_BUS_DRAM 12
> +#define RST_BUS_NAND 13
> +#define RST_BUS_MMC0 14
> +#define RST_BUS_MMC1 15
> +#define RST_BUS_MMC2 16
> +#define RST_BUS_UART0 17
> +#define RST_BUS_UART1 18
> +#define RST_BUS_UART2 19
> +#define RST_BUS_UART3 20
> +#define RST_BUS_UART4 21
> +#define RST_BUS_UART5 22
> +#define RST_BUS_I2C0 23
> +#define RST_BUS_I2C1 24
> +#define RST_BUS_I2C2 25
> +#define RST_BUS_I2C3 26
> +#define RST_BUS_I2C4 27
> +#define RST_BUS_SPI0 28
> +#define RST_BUS_SPI1 29
> +#define RST_BUS_EMAC0 30
> +#define RST_BUS_EMAC1 31
> +#define RST_BUS_TS 32
> +#define RST_BUS_THS 33
> +#define RST_BUS_SPDIF 34
> +#define RST_BUS_DMIC 35
> +#define RST_BUS_AUDIO_CODEC 36
> +#define RST_BUS_AUDIO_HUB 37
> +#define RST_USB_PHY0 38
> +#define RST_USB_PHY1 39
> +#define RST_USB_PHY2 40
> +#define RST_USB_PHY3 41
> +#define RST_BUS_OHCI0 42
> +#define RST_BUS_OHCI1 43
> +#define RST_BUS_OHCI2 44
> +#define RST_BUS_OHCI3 45
> +#define RST_BUS_EHCI0 46
> +#define RST_BUS_EHCI1 47
> +#define RST_BUS_EHCI2 48
> +#define RST_BUS_EHCI3 49
> +#define RST_BUS_OTG 50
> +#define RST_BUS_HDMI 51
> +#define RST_BUS_HDMI_SUB 52
> +#define RST_BUS_TCON_TOP 53
> +#define RST_BUS_TCON_TV0 54
> +#define RST_BUS_TCON_TV1 55
> +#define RST_BUS_TVE_TOP 56
> +#define RST_BUS_TVE0 57
> +#define RST_BUS_HDCP 58
> +#define RST_BUS_KEYADC 59
> +
> +#endif /* _DT_BINDINGS_RESET_SUN50I_H616_H_ */
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