[RFC PATCH] arm: dts: ls1028a: define QDS networking protocol combinations
Vladimir Oltean
olteanv at gmail.com
Wed Jan 27 12:00:00 CET 2021
From: Alex Marginean <alexandru.marginean at nxp.com>
Includes DT definition for the following serdes protocols using various
PHY cards: 85xx, 13xx, 65xx, 9999, 7777.
Note that the default device tree for QDS now uses 85xx.
Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi
file (the includes at the bottom of the file).
The phy-handle is specified as a path rather than a label because it is
possible to use the #include multiple times (meaning that more than one
PHY riser card of one type is inserted), and therefore, there would be
duplicate labels with the same name.
LBRW means that the board needs lane B rework before using this dtsi.
Signed-off-by: Alex Marginean <alexandru.marginean at nxp.com>
Signed-off-by: Vladimir Oltean <vladimir.oltean at nxp.com>
---
The reason for posting as RFC is that this depends on the Felix switch
driver and device tree bindings which were submitted here:
https://patchwork.ozlabs.org/project/uboot/cover/20210125122357.414742-1-olteanv@gmail.com/
.../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 20 ++++++
.../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 19 ++++++
.../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 49 +++++++++++++++
.../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 26 ++++++++
.../dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi | 19 ++++++
.../fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 63 +++++++++++++++++++
.../dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 48 ++++++++++++++
.../fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 48 ++++++++++++++
.../fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 42 +++++++++++++
.../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 20 ++++++
.../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 20 ++++++
arch/arm/dts/fsl-ls1028a-qds.dtsi | 3 +
arch/arm/dts/fsl-sch-24801.dtsi | 28 +++++++++
arch/arm/dts/fsl-sch-28021.dtsi | 29 +++++++++
arch/arm/dts/fsl-sch-30841.dtsi | 38 +++++++++++
arch/arm/dts/fsl-sch-30842.dtsi | 18 ++++++
16 files changed, 490 insertions(+)
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
create mode 100644 arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
create mode 100644 arch/arm/dts/fsl-sch-24801.dtsi
create mode 100644 arch/arm/dts/fsl-sch-28021.dtsi
create mode 100644 arch/arm/dts/fsl-sch-30841.dtsi
create mode 100644 arch/arm/dts/fsl-sch-30842.dtsi
diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
new file mode 100644
index 000000000000..23816da8eeba
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 1xxx
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC
+ * port 0 USXGMII.
+ */
+&slot1 {
+ #include "fsl-sch-30842.dtsi"
+};
+
+&enetc0 {
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 02}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
new file mode 100644
index 000000000000..c6558ae2e07b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 6xxx
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * This setup is using SCH-30842 cards with AQR112 PHY.
+ */
+&slot1 {
+ #include "fsl-sch-30842.dtsi"
+};
+
+&enetc0 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 02}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
new file mode 100644
index 000000000000..fb1836a8aef3
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 7777
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * This setup is using a SCH-30841 card with AQR412 10G quad PHY.
+ *
+ * Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1.
+ * Bottom port is port 0.
+ * Note that this is only usable for:
+ * - QDS boards WITHOUT lane B rework,
+ * - AQR412 card WITHOUT lane A -> lane C rework
+ *
+ * The following DTS assumes DIP SW5[1-3] = 000b.
+ */
+&slot1 {
+#include "fsl-sch-30841.dtsi"
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port0 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 00}>;
+};
+
+&mscc_felix_port1 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 01}>;
+};
+
+&mscc_felix_port2 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 02}>;
+};
+
+&mscc_felix_port3 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 03}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
new file mode 100644
index 000000000000..1d02a3e11def
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 7xx7
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+&slot1 {
+#include "fsl-sch-30841.dtsi"
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port0 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 02}>;
+};
+
+&mscc_felix_port3 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 03}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
new file mode 100644
index 000000000000..7d4702e4ff2b
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 8xxx
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY in slot 1.
+ */
+&slot1 {
+ #include "fsl-sch-24801.dtsi"
+};
+
+&enetc0 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 1c}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
new file mode 100644
index 000000000000..c92dd1bd2e95
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 9999
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY.
+ * LS1028A QDS boards with lane B rework require two cards for the 4 switch
+ * ports, QDS boards without the lane B rework only require one card.
+ *
+ * Switch ports are routed as follows:
+ * Port 0 goes to 1st port of VSC8234 quad card in slot 1,
+ * Port 1:
+ * - if the QDS has had lane B rework, it is 1st port in slot 2,
+ * - otherwise it is 2nd port in slot 1.
+ * Port 2:
+ * - if DIP SW5[1] = 0 it is 3rd port in slot 1,
+ * - otherwise it is 1st port in slot 3.
+ * Port 3:
+ * - if DIP SW5[2-3] = 00b it is 4th port in slot 1,
+ * - if DIP SW5[2-3] = 01b it is 2nd port in slot 3,
+ * - if DIP SW5[2-3] = 11b it is 1st port in slot 4.
+ *
+ * The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two
+ * SCH-24801 cards are required in slots 1 and 2.
+ */
+&slot1 {
+ #include "fsl-sch-24801.dtsi"
+};
+
+&slot2 {
+ #include "fsl-sch-24801.dtsi"
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port0 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 1c}>;
+};
+
+&mscc_felix_port1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 1c}>;
+};
+
+&mscc_felix_port2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 1e}>;
+};
+
+&mscc_felix_port3 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 1f}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
new file mode 100644
index 000000000000..941f7472eb09
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 9999
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ *
+ */
+
+/*
+ * This set-up is using SCH-24801 cards with VSC8234 quad SGMII PHY.
+ *
+ * Switch ports are mapped 1:1 to VSC8234 card ports seated in slot 1.
+ * Top port is port 0.
+ *
+ * The following DTS assumes DIP SW5[1-3] = 000b.
+ */
+
+&slot1 {
+ #include "fsl-sch-24801.dtsi"
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port0 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 1c}>;
+};
+
+&mscc_felix_port1 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 1d}>;
+};
+
+&mscc_felix_port2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 1e}>;
+};
+
+&mscc_felix_port3 {
+ status = "okay";
+ phy-mode = "sgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 40/phy at 1f}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
new file mode 100644
index 000000000000..7e483e656e28
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW x3xx
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This
+ * is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up.
+ *
+ * We're including the normal .dsti file, not the reworked card .dtsi
+ * intentionally. We are using multiplexing of the 4 interfaces on a single
+ * lane and the rework doesn't actually disable any port. The rework is in fact
+ * needed, otherwise the PHY won't work with the default wiring on the QDS/PHY
+ * card.
+ */
+&slot2 {
+#include "fsl-sch-30841.dtsi"
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port0 {
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 00}>;
+};
+
+&mscc_felix_port1 {
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 01}>;
+};
+
+&mscc_felix_port2 {
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 02}>;
+};
+
+&mscc_felix_port3 {
+ status = "okay";
+ phy-mode = "usxgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 03}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
new file mode 100644
index 000000000000..49fffdb9cb2a
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW x5xx
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2.
+ * This is only available on LS1028A QDS boards with lane B rework.
+ */
+&slot2 {
+ #include "fsl-sch-28021.dtsi"
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port0 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 08}>;
+};
+
+&mscc_felix_port1 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 09}>;
+};
+
+&mscc_felix_port2 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 0a}>;
+};
+
+&mscc_felix_port3 {
+ status = "okay";
+ phy-mode = "qsgmii";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 0b}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
new file mode 100644
index 000000000000..8347462f4cb0
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 7777
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+&slot2 {
+#include "fsl-sch-30842.dtsi"
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port1 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 50/phy at 02}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
new file mode 100644
index 000000000000..6be3b5094c81
--- /dev/null
+++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LS1028A-QDS device tree fragment for RCW 7777
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+&slot3 {
+#include "fsl-sch-30842.dtsi"
+};
+
+&mscc_felix {
+ status = "okay";
+};
+
+&mscc_felix_port2 {
+ status = "okay";
+ phy-mode = "sgmii-2500";
+ phy-handle = <&{/i2c at 2000000/fpga at 66/mux-mdio at 54/mdio at 60/phy at 02}>;
+};
diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi
index 6cdcce1b92fb..da89ff96e98c 100644
--- a/arch/arm/dts/fsl-ls1028a-qds.dtsi
+++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi
@@ -258,3 +258,6 @@
&mdio0 {
status = "okay";
};
+
+#include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
+#include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"
diff --git a/arch/arm/dts/fsl-sch-24801.dtsi b/arch/arm/dts/fsl-sch-24801.dtsi
new file mode 100644
index 000000000000..304afdabc59e
--- /dev/null
+++ b/arch/arm/dts/fsl-sch-24801.dtsi
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Device tree fragment for RCW SCH-24801 card
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * SCH-24801 is a 4xSGMII add-on card used with various FSL QDS boards.
+ * It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces.
+ * PHY addresses are 0x1c - 0x1f.
+ * On the card the first port is the top port (farthest from PEX connector).
+ */
+phy at 1c {
+ reg = <0x1c>;
+};
+
+phy at 1d {
+ reg = <0x1d>;
+};
+
+phy at 1e {
+ reg = <0x1e>;
+};
+
+phy at 1f {
+ reg = <0x1f>;
+};
diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi
new file mode 100644
index 000000000000..584f3fa68cdd
--- /dev/null
+++ b/arch/arm/dts/fsl-sch-28021.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Device tree fragment for RCW SCH-28021 card
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * SCH-28021 is a QSGMII add-on card used with various FSL QDS boards.
+ * It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a
+ * single QSGMII lane.
+ * PHY addresses are 0x08 - 0x0b.
+ * On the card the first port is the top port (farthest from PEX connector).
+ */
+phy at 08 {
+ reg = <0x08>;
+};
+
+phy at 09 {
+ reg = <0x09>;
+};
+
+phy at 0a {
+ reg = <0x0a>;
+};
+
+phy at 0b {
+ reg = <0x0b>;
+};
diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi
new file mode 100644
index 000000000000..ca437d178281
--- /dev/null
+++ b/arch/arm/dts/fsl-sch-30841.dtsi
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Device tree fragment for RCW SCH-30841 card
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * SCH-30841 is a 4 port add-on card used with various FSL QDS boards.
+ * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed
+ * together on a single lane or mapped 1:1 to serdes lanes.
+ * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI.
+ * PHY addresses are 0x00 - 0x03.
+ * On the card the first port is the bottom port (closest to PEX connector).
+ */
+phy at 00 {
+ reg = <0x00>;
+ mdi-reversal = <1>;
+ smb-addr = <0x25>;
+};
+
+phy at 01 {
+ reg = <0x01>;
+ mdi-reversal = <1>;
+ smb-addr = <0x26>;
+};
+
+phy at 02 {
+ reg = <0x02>;
+ mdi-reversal = <1>;
+ smb-addr = <0x27>;
+};
+
+phy at 03 {
+ reg = <0x03>;
+ mdi-reversal = <1>;
+ smb-addr = <0x28>;
+};
diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi
new file mode 100644
index 000000000000..fa0f2cdb1096
--- /dev/null
+++ b/arch/arm/dts/fsl-sch-30842.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * Device tree fragment for RCW SCH-30842 card
+ *
+ * Copyright 2019-2021 NXP Semiconductors
+ */
+
+/*
+ * SCH-30842 is a single port add-on card used with various FSL QDS boards.
+ * It integrates a AQR112 PHY, which supports several protocols - SGMII,
+ * SGMII-2500, USXGMII, XFI.
+ * PHY address is 0x02.
+ */
+phy at 02 {
+ reg = <0x02>;
+ mdi-reversal = <1>;
+ smb-addr = <0x25>;
+};
--
2.25.1
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