[PATCH v3 04/38] ppc: qemu: Support non-identity PCI bus address
Priyanka Jain (OSS)
priyanka.jain at oss.nxp.com
Tue Mar 2 07:34:30 CET 2021
>-----Original Message-----
>From: Bin Meng <bmeng.cn at gmail.com>
>Sent: Monday, March 1, 2021 1:25 PM
>To: Priyanka Jain (OSS) <priyanka.jain at oss.nxp.com>
>Cc: Simon Glass <sjg at chromium.org>; Alexander Graf <agraf at csgraf.de>; U-
>Boot Mailing List <u-boot at lists.denx.de>; Tom Rini <trini at konsulko.com>
>Subject: Re: [PATCH v3 04/38] ppc: qemu: Support non-identity PCI bus address
>
>Hi Priyanka,
>
>On Mon, Mar 1, 2021 at 3:15 PM Priyanka Jain (OSS) <priyanka.jain at oss.nxp.com>
>wrote:
>>
>>
>>
>> >-----Original Message-----
>> >From: Bin Meng <bmeng.cn at gmail.com>
>> >Sent: Friday, February 26, 2021 7:46 PM
>> >To: Priyanka Jain (OSS) <priyanka.jain at oss.nxp.com>
>> >Cc: Simon Glass <sjg at chromium.org>; Alexander Graf <agraf at csgraf.de>;
>> >U- Boot Mailing List <u-boot at lists.denx.de>; Tom Rini
>> ><trini at konsulko.com>
>> >Subject: Re: [PATCH v3 04/38] ppc: qemu: Support non-identity PCI bus
>> >address
>> >
>> >Hi Priyanka,
>> >
>> >On Fri, Feb 26, 2021 at 5:29 PM Priyanka Jain (OSS)
>> ><priyanka.jain at oss.nxp.com>
>> >wrote:
>> >>
>> >>
>> >>
>> >> >-----Original Message-----
>> >> >From: U-Boot <u-boot-bounces at lists.denx.de> On Behalf Of Bin Meng
>> >> >Sent: Thursday, February 25, 2021 2:52 PM
>> >> >To: Simon Glass <sjg at chromium.org>; Alexander Graf
>> >> ><agraf at csgraf.de>; Priyanka Jain <priyanka.jain at nxp.com>
>> >> >Cc: U-Boot Mailing List <u-boot at lists.denx.de>; Tom Rini
>> >> ><trini at konsulko.com>
>> >> >Subject: [PATCH v3 04/38] ppc: qemu: Support non-identity PCI bus
>> >> >address
>> >> >
>> >> >When QEMU originally supported the ppce500 machine back in Jan
>> >> >2014, it was created with a 1:1 mapping of PCI bus address. Things
>> >> >seemed to change rapidly that in Nov 2014 with the following QEMU
>commits:
>> >> >
>> >> >commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper
>> >> >end of address space")
>> >> >
>> >> >and
>> >> >
>> >> >commit cb3778a0455a ("PPC: e500 pci host: Add support for ATMUs")
>> >> >
>> >> >the PCI memory and IO physical address were moved to beyond 4 GiB,
>> >> >but PCI bus address remained below 4 GiB, hence a non-identity
>> >> >mapping was
>> >created.
>> >> >Unfortunately corresponding U-Boot updates were missed along with
>> >> >the QEMU changes and the U-Boot QEMU ppce500 PCI support has been
>> >> >broken
>> >since then.
>> >> >
>> >> >This commit makes the PCI (non-DM version) work again.
>> >> >
>> >> >Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
>> >> >---
>> >> >
>> >> >(no changes since v1)
>> >> >
>> >> > board/freescale/qemu-ppce500/qemu-ppce500.c | 29
>> >> >++++++++++++++-----------
>> >> >----
>> >> > 1 file changed, 14 insertions(+), 15 deletions(-)
>> >> >
>> >> >diff --git a/board/freescale/qemu-ppce500/qemu-ppce500.c
>> >> >b/board/freescale/qemu-ppce500/qemu-ppce500.c
>> >> >index aa5774f..1d68d30 100644
>> >> >--- a/board/freescale/qemu-ppce500/qemu-ppce500.c
>> >> >+++ b/board/freescale/qemu-ppce500/qemu-ppce500.c
>> >> >@@ -85,20 +85,24 @@ int checkboard(void) }
>> >> >
>> >> > static int pci_map_region(void *fdt, int pci_node, int range_id,
>> >> >- phys_size_t *ppaddr, pci_addr_t *pvaddr,
>> >> >- pci_size_t *psize, ulong *pmap_addr)
>> >> >+ phys_addr_t *pbaddr, phys_size_t *ppaddr,
>> >> >+ pci_addr_t *pvaddr, pci_size_t *psize,
>> >> >+ ulong *pmap_addr)
>> >> > {
>> >> >- uint64_t addr;
>> >> >+ uint64_t baddr;
>> >> >+ uint64_t paddr;
>> >> > uint64_t size;
>> >> > ulong map_addr;
>> >> > int r;
>> >> >
>> >> >- r = fdt_read_range(fdt, pci_node, range_id, NULL, &addr, &size);
>> >> >+ r = fdt_read_range(fdt, pci_node, range_id, &baddr, &paddr,
>> >> >+ &size);
>> >> > if (r)
>> >> > return r;
>> >> >
>> >> >+ if (pbaddr)
>> >> >+ *pbaddr = baddr;
>> >> > if (ppaddr)
>> >> >- *ppaddr = addr;
>> >> >+ *ppaddr = paddr;
>> >> > if (psize)
>> >> > *psize = size;
>> >> >
>> >> >@@ -115,7 +119,7 @@ static int pci_map_region(void *fdt, int
>> >> >pci_node, int range_id,
>> >> > return -1;
>> >> >
>> >> > /* Map virtual memory for range */
>> >> >- assert(!tlb_map_range(map_addr, addr, size, TLB_MAP_IO));
>> >> >+ assert(!tlb_map_range(map_addr, paddr, size, TLB_MAP_IO));
>> >> > *pmap_addr = map_addr + size;
>> >> >
>> >> > if (pvaddr)
>> >> >@@ -166,24 +170,19 @@ void pci_init_board(void)
>> >> > pci_info.regs = fdt_translate_address(fdt,
>> >> >pci_node, reg);
>> >> >
>> >> > /* Map MMIO range */
>> >> >- r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_phys, NULL,
>> >> >+ r = pci_map_region(fdt, pci_node, 0, &pci_info.mem_bus,
>> >> >+ &pci_info.mem_phys, NULL,
>> >> > &pci_info.mem_size, &map_addr);
>> >> > if (r)
>> >> > break;
>> >> >
>> >> > /* Map PIO range */
>> >> >- r = pci_map_region(fdt, pci_node, 1, &pci_info.io_phys, NULL,
>> >> >+ r = pci_map_region(fdt, pci_node, 1, &pci_info.io_bus,
>> >> >+ &pci_info.io_phys, NULL,
>> >> > &pci_info.io_size, &map_addr);
>> >> > if (r)
>> >> > break;
>> >> >
>> >> >- /*
>> >> >- * The PCI framework finds virtual addresses for the buses
>> >> >- * through our address map, so tell it the physical addresses.
>> >> >- */
>> >> >- pci_info.mem_bus = pci_info.mem_phys;
>> >> >- pci_info.io_bus = pci_info.io_phys;
>> >> >-
>> >> > /* Instantiate */
>> >> > pci_info.pci_num = pci_num + 1;
>> >> >
>> >> >--
>> >> >2.7.4
>> >>
>> >> Kindly fix below checkpatch warnings, checks:
>> >> WARNING: Possible unwrapped commit description (prefer a maximum 75
>> >> chars per line)
>> >> #10:
>> >> commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper
>> >> end of address space")
>> >>
>> >> WARNING: Unknown commit id 'e6b4e5f4795b', maybe rebased or not
>pulled?
>> >> #10:
>> >> commit e6b4e5f4795b ("PPC: e500: Move CCSR and MMIO space to upper
>> >> end of address space")
>> >>
>> >> WARNING: Unknown commit id 'cb3778a0455a', maybe rebased or not
>pulled?
>> >> #14:
>> >> commit cb3778a0455a ("PPC: e500 pci host: Add support for ATMUs")
>> >>
>> >> CHECK: Prefer kernel type 'u64' over 'uint64_t'
>> >> #45: FILE: board/freescale/qemu-ppce500/qemu-ppce500.c:92:
>> >> + uint64_t baddr;
>> >>
>> >> CHECK: Prefer kernel type 'u64' over 'uint64_t'
>> >> #46: FILE: board/freescale/qemu-ppce500/qemu-ppce500.c:93:
>> >> + uint64_t paddr;
>> >>
>> >> total: 0 errors, 3 warnings, 2 checks, 65 lines checked
>> >
>> >I checked all checkpatch warnings of this series before sending out
>> >for review, and I think all issues you mentioned are something that we don't
>need to fix.
>> >
>> >Sorry I should have mentioned above in the cover letter.
>> >
>> >Regards,
>> >Bin
>>
>> Ok for checkpatch warnings.
>
>Thank you.
>
>> Kindly fix build issue on qemu_ppce500
>
>I did test this before, and mentioned all builds PASS in the cover letter on my
>branch:
>https://dev.azure.com/bmeng/GitHub/_build/results?buildId=325&view=results
>
>>
>> Pull-request:
>> https://github.com/u-boot/u-boot/pull/54/checks?check_run_id=200143593
>> 2
>>
>> Raw logs at:
>> https://dev.azure.com/u-boot/a1096300-2999-4ec4-a21a-4c22075e3771/_api
>> s/build/builds/1882/logs/406
>
>This should be caused by the following patch does not end up in u-boot/master.
>http://patchwork.ozlabs.org/project/uboot/patch/1612363345-24335-1-git-
>send-email-bmeng.cn at gmail.com
>
>which I already pinged Simon.
>
>Hi Simon,
>
>Could you please send PR for the ns16550 fixes?
>
>Regards,
>Bin
Hello Simon,
When are you planning to send this PR?
I have powerpc, fsl-qoriq pull-request ready for v2021.04 which is dependent on the above to pass build test.
Regards
Priyanka
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