[PATCH v2 15/19] clk: sunxi: add DE2 clock driver

Jagan Teki jagan at amarulasolutions.com
Mon Mar 8 08:59:35 CET 2021

On Sun, Mar 7, 2021 at 1:25 AM Jernej Skrabec <jernej.skrabec at siol.net> wrote:
> Video driver currently manages clocks and resets by directly writing to
> registers. This is already a bit messy because each SoC has some
> specifics. It's much better to implement proper clock and reset driver
> which takes information from device tree file.
> Note that this driver is not perfect yet. It still sets PLL and parent
> by hand. Sunxi clock framework still doesn't know how to set parents or
> rates. However, this is already big step in right direction.
> Cc: Lukasz Majewski <lukma at denx.de>
> Signed-off-by: Jernej Skrabec <jernej.skrabec at siol.net>
> ---

Reviewed-by: Jagan Teki <jagan at amarulasolutions.com>

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