[PATCH 7/7] drivers: net: macb: add fu740 support
David Abdurachmanov
david.abdurachmanov at gmail.com
Mon Mar 15 10:00:13 CET 2021
On Thu, Mar 11, 2021 at 4:45 PM Bin Meng <bmeng.cn at gmail.com> wrote:
>
> On Thu, Mar 11, 2021 at 10:42 PM Green Wan <green.wan at sifive.com> wrote:
> >
> >
> >
> > Bin Meng <bmeng.cn at gmail.com>於 2021年3月11日 週四,下午10:22寫道:
> >>
> >> On Thu, Mar 11, 2021 at 9:50 PM Green Wan <green.wan at sifive.com> wrote:
> >> >
> >> > Add fu740 support to macb ethernet driver
> >> >
> >> > Signed-off-by: Green Wan <green.wan at sifive.com>
> >> > ---
> >> > drivers/net/macb.c | 8 +++++++-
> >> > 1 file changed, 7 insertions(+), 1 deletion(-)
> >> >
> >> > diff --git a/drivers/net/macb.c b/drivers/net/macb.c
> >> > index 57ea45e..df65d82 100644
> >> > --- a/drivers/net/macb.c
> >> > +++ b/drivers/net/macb.c
> >> > @@ -592,7 +592,11 @@ static int macb_sifive_clk_init(struct udevice *dev, ulong rate)
> >> > * and output clock on GMII output signal GTX_CLK
> >> > * 1 = MII mode. Use MII input signal TX_CLK in TX logic
> >> > */
> >> > - writel(rate != 125000000, gemgxl_regs);
> >> > + if (device_is_compatible(dev, "sifive,fu540-c000-gem"))
> >> > + writel(rate != 125000000, gemgxl_regs);
> >> > + else if (device_is_compatible(dev, "sifive,fu740-c000-gem"))
> >> > + writel(rate != 125125000, gemgxl_regs);
> >>
> >> 125125000 seems to be an odd value for 1000 Mbps ethernet. Can you
> >> please explain this a little bit?
> >
> >
> > It's simply due to the limitation in the PLL cannot generate 125 000 000 Hz clock precisely. The closet one is 125 125 000 HZ.
>
> So FU540 can but FU740 cannot? I would consider this as a hardware
> regression ...
Note that 125.125MHz is out of spec, but that's the closest we can get
and 1Gbps works fine based on the tests I did.
This is hardware quirk, and probably a comment explaining this should
be provided here.
david
>
> Regards,
> Bin
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