[PATCH v2 5/5] board: imx8mm: Add Engicam i.Core MX8M Mini C.TOUCH 2.0
Jagan Teki
jagan at amarulasolutions.com
Mon Mar 15 18:45:43 CET 2021
Engicam C.TOUCH 2.0 is an EDIMM compliant general purpose Carrier
board.
Genaral features:
- Ethernet 10/100
- Wifi/BT
- USB Type A/OTG
- Audio Out
- CAN
- LVDS panel connector
i.Core MX8M Mini is an EDIMM SoM based on NXP i.MX8M Mini from Engicam.
i.Core MX8M Mini needs to mount on top of this Carrier board for
creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
Linux dts commit details:
commit <a142252061ff> ("arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini
C.TOUCH 2.0")
Add support for it.
Signed-off-by: Jagan Teki <jagan at amarulasolutions.com>
---
Changes for v2:
- add Linux commit details
arch/arm/dts/Makefile | 1 +
.../imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi | 31 ++++++
arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts | 97 +++++++++++++++++++
arch/arm/mach-imx/imx8m/Kconfig | 5 +
board/engicam/imx8mm/MAINTAINERS | 6 ++
configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 92 ++++++++++++++++++
6 files changed, 232 insertions(+)
create mode 100644 arch/arm/dts/imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi
create mode 100644 arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts
create mode 100644 configs/imx8mm-icore-mx8mm-ctouch2_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 08db525bc4..17cf936a1f 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -790,6 +790,7 @@ dtb-$(CONFIG_ARCH_IMX8) += \
dtb-$(CONFIG_ARCH_IMX8M) += \
imx8mm-evk.dtb \
+ imx8mm-icore-mx8mm-ctouch2.dtb \
imx8mm-icore-mx8mm-edimm2.2.dtb \
imx8mm-venice.dtb \
imx8mm-venice-gw71xx-0x.dtb \
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi
new file mode 100644
index 0000000000..8b67bcff7d
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2-u-boot.dtsi
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+#include "imx8mm-icore-mx8mm-u-boot.dtsi"
+
+&gpio1 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_uart2 {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1_gpio {
+ u-boot,dm-spl;
+};
+
+&pinctrl_usdhc1 {
+ u-boot,dm-spl;
+};
+
+&uart2 {
+ u-boot,dm-spl;
+};
+
+&usdhc1 {
+ u-boot,dm-spl;
+};
diff --git a/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts
new file mode 100644
index 0000000000..5389d6f2be
--- /dev/null
+++ b/arch/arm/dts/imx8mm-icore-mx8mm-ctouch2.dts
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 NXP
+ * Copyright (c) 2019 Engicam srl
+ * Copyright (c) 2020 Amarula Solutions(India)
+ */
+
+/dts-v1/;
+#include "imx8mm.dtsi"
+#include "imx8mm-icore-mx8mm.dtsi"
+
+/ {
+ model = "Engicam i.Core MX8M Mini C.TOUCH 2.0";
+ compatible = "engicam,icore-mx8mm-ctouch2", "engicam,icore-mx8mm",
+ "fsl,imx8mm";
+
+ chosen {
+ stdout-path = &uart2;
+ };
+};
+
+&fec1 {
+ status = "okay";
+};
+
+&i2c2 {
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+};
+
+&i2c4 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4>;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_i2c4: i2c4grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3
+ MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
+ MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
+ >;
+ };
+
+ pinctrl_usdhc1_gpio: usdhc1gpiogrp {
+ fsl,pins = <
+ MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
+ MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
+ MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
+ MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
+ MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
+ MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
+ >;
+ };
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+/* SD */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
+ cd-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ no-1-8-v;
+ pm-ignore-notify;
+ keep-power-in-suspend;
+ status = "okay";
+};
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 28a9a51e67..7262ab0517 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -62,6 +62,11 @@ config TARGET_IMX8MM_ICORE_MX8MM
* i.Core MX8M Mini needs to mount on top of EDIMM2.2 for
creating complete i.Core MX8M Mini EDIMM2.2 Starter Kit.
+ i.Core MX8M Mini C.TOUCH 2.0
+ * C.TOUCH 2.0 is a general purpose Carrier board.
+ * i.Core MX8M Mini needs to mount on top of this Carrier board
+ for creating complete i.Core MX8M Mini C.TOUCH 2.0 board.
+
config TARGET_IMX8MN_DDR4_EVK
bool "imx8mn DDR4 EVK board"
select IMX8MN
diff --git a/board/engicam/imx8mm/MAINTAINERS b/board/engicam/imx8mm/MAINTAINERS
index 044a9392ac..2e99a5995f 100644
--- a/board/engicam/imx8mm/MAINTAINERS
+++ b/board/engicam/imx8mm/MAINTAINERS
@@ -1,3 +1,9 @@
+i.Core-MX8M-Mini-CTOUCH2.0
+M: Jagan Teki <jagan at amarulasolutions.com>
+M: Matteo Lisi <matteo.lisi at engicam.com>
+S: Maintained
+F: configs/imx8mm-icore-mx8mm-ctouch2_defconfig
+
i.Core-MX8M-Mini-EDIMM2.2
M: Jagan Teki <jagan at amarulasolutions.com>
M: Matteo Lisi <matteo.lisi at engicam.com>
diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
new file mode 100644
index 0000000000..f771ebdb50
--- /dev/null
+++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig
@@ -0,0 +1,92 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8M=y
+CONFIG_SYS_TEXT_BASE=0x40200000
+CONFIG_SPL_GPIO_SUPPORT=y
+CONFIG_SPL_LIBCOMMON_SUPPORT=y
+CONFIG_SPL_LIBGENERIC_SUPPORT=y
+CONFIG_SYS_MALLOC_F_LEN=0x10000
+CONFIG_ENV_SIZE=0x1000
+CONFIG_ENV_OFFSET=0x400000
+CONFIG_DM_GPIO=y
+CONFIG_SPL_TEXT_BASE=0x7E1000
+CONFIG_TARGET_IMX8MM_ICORE_MX8MM=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_DRIVERS_MISC_SUPPORT=y
+CONFIG_SPL=y
+CONFIG_DEFAULT_DEVICE_TREE="imx8mm-icore-mx8mm-ctouch2"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_EXTERNAL_OFFSET=0x3000
+CONFIG_SPL_LOAD_FIT=y
+CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh"
+CONFIG_OF_SYSTEM_SETUP=y
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg"
+CONFIG_DEFAULT_FDT_FILE="imx8mm-icore-mx8mm-ctouch2.dtb"
+CONFIG_SPL_BOARD_INIT=y
+CONFIG_SPL_SEPARATE_BSS=y
+CONFIG_SPL_POWER_SUPPORT=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="u-boot=> "
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_CRC32 is not set
+CONFIG_CMD_CLK=y
+CONFIG_CMD_FUSE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_REGULATOR=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+# CONFIG_ISO_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+CONFIG_OF_CONTROL=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_MMC=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_SYS_MMC_ENV_DEV=2
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_CLK_COMPOSITE_CCF=y
+CONFIG_CLK_COMPOSITE_CCF=y
+CONFIG_SPL_CLK_IMX8MM=y
+CONFIG_CLK_IMX8MM=y
+CONFIG_MXC_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MXC=y
+CONFIG_DM_MMC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_FSL_USDHC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_ATHEROS=y
+CONFIG_DM_ETH=y
+CONFIG_PHY_GIGE=y
+CONFIG_FEC_MXC=y
+CONFIG_MII=y
+CONFIG_PINCTRL=y
+CONFIG_SPL_PINCTRL=y
+CONFIG_PINCTRL_IMX8M=y
+CONFIG_DM_REGULATOR=y
+CONFIG_SPL_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_CONS_INDEX=2
+CONFIG_DM_SERIAL=y
+# CONFIG_SPL_DM_SERIAL is not set
+CONFIG_MXC_UART=y
+CONFIG_SYSRESET=y
+CONFIG_SPL_SYSRESET=y
+CONFIG_SYSRESET_PSCI=y
+CONFIG_DM_THERMAL=y
+CONFIG_IMX_TMU=y
--
2.25.1
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