[PATCH v2 5/8] drivers: ram: add fu740 support
Green Wan
green.wan at sifive.com
Tue Mar 16 17:33:13 CET 2021
Add fu740 support for ram
Signed-off-by: Green Wan <green.wan at sifive.com>
---
drivers/ram/sifive/Kconfig | 2 +-
drivers/ram/sifive/sifive_ddr.c | 88 ++++++++++++++++++++---------------------
2 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig
index a93cd0e..0aaac02 100644
--- a/drivers/ram/sifive/Kconfig
+++ b/drivers/ram/sifive/Kconfig
@@ -8,6 +8,6 @@ config RAM_SIFIVE
config SIFIVE_DDR
bool "SiFive DDR driver"
depends on RAM_SIFIVE
- default y if TARGET_SIFIVE_UNLEASHED
+ default y if TARGET_SIFIVE_UNLEASHED || TARGET_SIFIVE_UNMATCHED
help
This enables DDR support for the platforms based on SiFive SoC.
diff --git a/drivers/ram/sifive/sifive_ddr.c b/drivers/ram/sifive/sifive_ddr.c
index b7c3ae1..2b23c87 100644
--- a/drivers/ram/sifive/sifive_ddr.c
+++ b/drivers/ram/sifive/sifive_ddr.c
@@ -12,7 +12,6 @@
#include <init.h>
#include <ram.h>
#include <syscon.h>
-#include <asm/global_data.h>
#include <asm/io.h>
#include <clk.h>
#include <wait_bit.h>
@@ -65,16 +64,16 @@
DECLARE_GLOBAL_DATA_PTR;
-struct fu540_ddrctl {
+struct sifive_ddrctl {
volatile u32 denali_ctl[265];
};
-struct fu540_ddrphy {
+struct sifive_ddrphy {
volatile u32 denali_phy[1215];
};
/**
- * struct fu540_ddr_info
+ * struct sifive_ddr_info
*
* @dev : pointer for the device
* @info : UCLASS RAM information
@@ -83,23 +82,23 @@ struct fu540_ddrphy {
* @ctrl : DDR control base address
* @physical_filter_ctrl : DDR physical filter control base address
*/
-struct fu540_ddr_info {
+struct sifive_ddr_info {
struct udevice *dev;
struct ram_info info;
- struct fu540_ddrctl *ctl;
- struct fu540_ddrphy *phy;
+ struct sifive_ddrctl *ctl;
+ struct sifive_ddrphy *phy;
struct clk ddr_clk;
u32 *physical_filter_ctrl;
};
#if defined(CONFIG_SPL_BUILD)
-struct fu540_ddr_params {
- struct fu540_ddrctl pctl_regs;
- struct fu540_ddrphy phy_regs;
+struct sifive_ddr_params {
+ struct sifive_ddrctl pctl_regs;
+ struct sifive_ddrphy phy_regs;
};
struct sifive_dmc_plat {
- struct fu540_ddr_params ddr_params;
+ struct sifive_ddr_params ddr_params;
};
/*
@@ -118,7 +117,7 @@ static void sdram_copy_to_reg(volatile u32 *dest,
}
}
-static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
+static void sifive_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
{
u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1;
@@ -135,8 +134,8 @@ static void fu540_ddr_setup_range_protection(volatile u32 *ctl, u64 end_addr)
0x1 << PORT_ADDR_PROTECTION_EN_OFFSET);
}
-static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
- u64 ddr_end)
+static void sifive_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
+ u64 ddr_end)
{
volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl;
@@ -149,7 +148,7 @@ static void fu540_ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl,
filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2);
}
-static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
+static void sifive_ddr_check_errata(u32 regbase, u32 updownreg)
{
u64 fails = 0;
u32 dq = 0;
@@ -202,7 +201,7 @@ static void fu540_ddr_check_errata(u32 regbase, u32 updownreg)
}
}
-static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
+static u64 sifive_ddr_phy_fixup(volatile u32 *ddrphyreg)
{
u32 slicebase = 0;
@@ -213,7 +212,7 @@ static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
for (u32 reg = 0; reg < 4; reg++) {
u32 updownreg = readl(regbase + reg + ddrphyreg);
- fu540_ddr_check_errata(regbase, updownreg);
+ sifive_ddr_check_errata(regbase, updownreg);
}
slicebase += 128;
}
@@ -221,18 +220,18 @@ static u64 fu540_ddr_phy_fixup(volatile u32 *ddrphyreg)
return(0);
}
-static u32 fu540_ddr_get_dram_class(volatile u32 *ctl)
+static u32 sifive_ddr_get_dram_class(volatile u32 *ctl)
{
u32 reg = readl(DENALI_CTL_0 + ctl);
return ((reg >> DRAM_CLASS_OFFSET) & 0xF);
}
-static int fu540_ddr_setup(struct udevice *dev)
+static int sifive_ddr_setup(struct udevice *dev)
{
- struct fu540_ddr_info *priv = dev_get_priv(dev);
+ struct sifive_ddr_info *priv = dev_get_priv(dev);
struct sifive_dmc_plat *plat = dev_get_plat(dev);
- struct fu540_ddr_params *params = &plat->ddr_params;
+ struct sifive_ddr_params *params = &plat->ddr_params;
volatile u32 *denali_ctl = priv->ctl->denali_ctl;
volatile u32 *denali_phy = priv->phy->denali_phy;
const u64 ddr_size = priv->info.size;
@@ -251,7 +250,7 @@ static int fu540_ddr_setup(struct udevice *dev)
sdram_copy_to_reg(priv->ctl->denali_ctl,
params->pctl_regs.denali_ctl,
- sizeof(struct fu540_ddrctl));
+ sizeof(struct sifive_ddrctl));
/* phy reset */
for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) {
@@ -285,7 +284,7 @@ static int fu540_ddr_setup(struct udevice *dev)
setbits_le32(DENALI_CTL_182 + denali_ctl,
1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET);
- if (fu540_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) {
+ if (sifive_ddr_get_dram_class(denali_ctl) == DRAM_CLASS_DDR4) {
/* Enable vref training DENALI_CTL_184 */
setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET);
}
@@ -302,15 +301,15 @@ static int fu540_ddr_setup(struct udevice *dev)
| (1 << MULTIPLE_OUT_OF_RANGE_OFFSET));
/* set up range protection */
- fu540_ddr_setup_range_protection(denali_ctl, priv->info.size);
+ sifive_ddr_setup_range_protection(denali_ctl, priv->info.size);
/* Mask off port command error interrupt DENALI_CTL_136 */
setbits_le32(DENALI_CTL_136 + denali_ctl,
1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET);
- fu540_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
+ sifive_ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end);
- fu540_ddr_phy_fixup(denali_phy);
+ sifive_ddr_phy_fixup(denali_phy);
/* check size */
priv->info.size = get_ram_size((long *)priv->info.base,
@@ -329,9 +328,9 @@ static int fu540_ddr_setup(struct udevice *dev)
}
#endif
-static int fu540_ddr_probe(struct udevice *dev)
+static int sifive_ddr_probe(struct udevice *dev)
{
- struct fu540_ddr_info *priv = dev_get_priv(dev);
+ struct sifive_ddr_info *priv = dev_get_priv(dev);
/* Read memory base and size from DT */
fdtdec_setup_mem_size_base();
@@ -342,7 +341,7 @@ static int fu540_ddr_probe(struct udevice *dev)
int ret;
u32 clock = 0;
- debug("FU540 DDR probe\n");
+ debug("sifive DDR probe\n");
priv->dev = dev;
ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
@@ -369,42 +368,43 @@ static int fu540_ddr_probe(struct udevice *dev)
return ret;
}
- priv->ctl = (struct fu540_ddrctl *)dev_read_addr_index(dev, 0);
- priv->phy = (struct fu540_ddrphy *)dev_read_addr_index(dev, 1);
+ priv->ctl = (struct sifive_ddrctl *)dev_read_addr_index(dev, 0);
+ priv->phy = (struct sifive_ddrphy *)dev_read_addr_index(dev, 1);
priv->physical_filter_ctrl = (u32 *)dev_read_addr_index(dev, 2);
- return fu540_ddr_setup(dev);
+ return sifive_ddr_setup(dev);
#endif
return 0;
}
-static int fu540_ddr_get_info(struct udevice *dev, struct ram_info *info)
+static int sifive_ddr_get_info(struct udevice *dev, struct ram_info *info)
{
- struct fu540_ddr_info *priv = dev_get_priv(dev);
+ struct sifive_ddr_info *priv = dev_get_priv(dev);
*info = priv->info;
return 0;
}
-static struct ram_ops fu540_ddr_ops = {
- .get_info = fu540_ddr_get_info,
+static struct ram_ops sifive_ddr_ops = {
+ .get_info = sifive_ddr_get_info,
};
-static const struct udevice_id fu540_ddr_ids[] = {
+static const struct udevice_id sifive_ddr_ids[] = {
{ .compatible = "sifive,fu540-c000-ddr" },
+ { .compatible = "sifive,fu740-c000-ddr" },
{ }
};
-U_BOOT_DRIVER(fu540_ddr) = {
- .name = "fu540_ddr",
+U_BOOT_DRIVER(sifive_ddr) = {
+ .name = "sifive_ddr",
.id = UCLASS_RAM,
- .of_match = fu540_ddr_ids,
- .ops = &fu540_ddr_ops,
- .probe = fu540_ddr_probe,
- .priv_auto = sizeof(struct fu540_ddr_info),
+ .of_match = sifive_ddr_ids,
+ .ops = &sifive_ddr_ops,
+ .probe = sifive_ddr_probe,
+ .priv_auto = sizeof(struct sifive_ddr_info),
#if defined(CONFIG_SPL_BUILD)
- .plat_auto = sizeof(struct sifive_dmc_plat),
+ .plat_auto = sizeof(struct sifive_dmc_plat),
#endif
};
--
2.7.4
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