[PATCH 3/4] mmc: fsl_esdhc: add pulse width detection workaround
Jaehoon Chung
jh80.chung at samsung.com
Wed Mar 17 23:47:42 CET 2021
On 3/17/21 11:01 PM, Michael Walle wrote:
> HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a
> workaroung for the pulse width detection. Apply this workaround in
> u-boot, too.
>
> This will make HS400 mode work reliably on the LS1028A SoC.
>
> Signed-off-by: Michael Walle <michael at walle.cc>
> ---
> arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 1 +
> drivers/mmc/Kconfig | 3 +++
> drivers/mmc/fsl_esdhc.c | 6 +++++-
> include/fsl_esdhc.h | 3 +++
> 4 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index c0190a233e..9d1ba4c771 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -48,6 +48,7 @@ config ARCH_LS1028A
> select SYS_FSL_ERRATUM_A009942 if !TFABOOT
> select SYS_FSL_ERRATUM_A050382
> select SYS_FSL_ERRATUM_A011334
> + select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
> select RESV_RAM if GIC_V3_ITS
> imply PANIC_HANG
>
> diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
> index 0b6755fd90..f7620c9cd1 100644
> --- a/drivers/mmc/Kconfig
> +++ b/drivers/mmc/Kconfig
> @@ -815,3 +815,6 @@ config SYS_FSL_ERRATUM_ESDHC_A001
>
> config SYS_FSL_ERRATUM_A011334
> bool
> +
> +config SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
How about using QUIRK instead of WORKAROUD
Best Regards,
Jaehoon Chung
> + bool
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 09ea1a9de9..7501fdb71e 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -71,7 +71,8 @@ struct fsl_esdhc {
> uint sdtimingctl; /* SD timing control register */
> char reserved8[20]; /* reserved */
> uint dllcfg0; /* DLL config 0 register */
> - char reserved9[12]; /* reserved */
> + uint dllcfg1; /* DLL config 1 register */
> + char reserved9[8]; /* reserved */
> uint dllstat0; /* DLL status 0 register */
> char reserved10[664];/* reserved */
> uint esdhcctl; /* eSDHC control register */
> @@ -767,6 +768,9 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
> /* Set timout to the maximum value */
> esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
>
> + if (IS_ENABLED(CONFIG_SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND))
> + esdhc_clrbits32(®s->dllcfg1, DLL_PD_PULSE_STRETCH_SEL);
> +
> return 0;
> }
>
> diff --git a/include/fsl_esdhc.h b/include/fsl_esdhc.h
> index 850a304bd7..f86afe5dad 100644
> --- a/include/fsl_esdhc.h
> +++ b/include/fsl_esdhc.h
> @@ -190,6 +190,9 @@
> #define DLL_RESET 0x40000000
> #define DLL_FREQ_SEL 0x08000000
>
> +/* DLL config 1 register */
> +#define DLL_PD_PULSE_STRETCH_SEL 0x80000000
> +
> /* DLL status 0 register */
> #define DLL_STS_SLV_LOCK 0x08000000
>
>
More information about the U-Boot
mailing list