[PATCH 10/26] imx8mp: refine power on imx8mp board
Peng Fan (OSS)
peng.fan at oss.nxp.com
Fri Mar 19 08:57:02 CET 2021
From: "haidong.zheng" <haidong.zheng at nxp.com>
VDD SOC normal run changed to 0.85V
LPDDR4 freq0 change from 4000MTS to 2400MTS
Signed-off-by: haidong.zheng <haidong.zheng at nxp.com>
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
board/freescale/imx8mp_evk/lpddr4_timing.c | 166 +++++++++++++++++++++
board/freescale/imx8mp_evk/spl.c | 5 +
drivers/ddr/imx/imx8m/Kconfig | 8 +
3 files changed, 179 insertions(+)
mode change 100644 => 100755 board/freescale/imx8mp_evk/lpddr4_timing.c
diff --git a/board/freescale/imx8mp_evk/lpddr4_timing.c b/board/freescale/imx8mp_evk/lpddr4_timing.c
old mode 100644
new mode 100755
index 0759502ba3..9d069fc27a
--- a/board/freescale/imx8mp_evk/lpddr4_timing.c
+++ b/board/freescale/imx8mp_evk/lpddr4_timing.c
@@ -11,6 +11,16 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400304, 0x1 },
{ 0x3d400030, 0x1 },
{ 0x3d400000, 0xa3080020 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x3d400020, 0x223 },
+ { 0x3d400024, 0x124f800 },
+ { 0x3d400064, 0x4900a8 },
+ { 0x3d400070, 0x1027f90 },
+ { 0x3d400074, 0x790 },
+ { 0x3d4000d0, 0xc0030495 },
+ { 0x3d4000d4, 0x770000 },
+ { 0x3d4000dc, 0xc40024 },
+#else
{ 0x3d400020, 0x1323 },
{ 0x3d400024, 0x1e84800 },
{ 0x3d400064, 0x7a017c },
@@ -23,9 +33,29 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4000d0, 0xc00307a3 },
{ 0x3d4000d4, 0xc50000 },
{ 0x3d4000dc, 0xf4003f },
+#endif
{ 0x3d4000e0, 0x330000 },
{ 0x3d4000e8, 0x660048 },
{ 0x3d4000ec, 0x160048 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x3d400100, 0x1618141a },
+ { 0x3d400104, 0x504a6 },
+ { 0x3d40010c, 0x909000 },
+ { 0x3d400110, 0xb04060b },
+ { 0x3d400114, 0x2030909 },
+ { 0x3d400118, 0x1010006 },
+ { 0x3d40011c, 0x301 },
+ { 0x3d400130, 0x20500 },
+ { 0x3d400134, 0xb100002 },
+ { 0x3d400138, 0xad },
+ { 0x3d400144, 0x78003c },
+ { 0x3d400180, 0x2580012 },
+ { 0x3d400184, 0x1e0493e },
+ { 0x3d400188, 0x0 },
+ { 0x3d400190, 0x4938208 },
+ { 0x3d400194, 0x80303 },
+ { 0x3d4001b4, 0x1308 },
+#else
{ 0x3d400100, 0x2028222a },
{ 0x3d400104, 0x807bf },
{ 0x3d40010c, 0xe0e000 },
@@ -43,6 +73,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d400190, 0x49f820e },
{ 0x3d400194, 0x80303 },
{ 0x3d4001b4, 0x1f0e },
+#endif
{ 0x3d4001a0, 0xe0400018 },
{ 0x3d4001a4, 0xdf00e4 },
{ 0x3d4001a8, 0x80000000 },
@@ -50,6 +81,30 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d4001c0, 0x1 },
{ 0x3d4001c4, 0x1 },
{ 0x3d4000f4, 0xc99 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x3d400108, 0x60c1514 },
+ { 0x3d400200, 0x16 },
+ { 0x3d40020c, 0x0 },
+ { 0x3d400210, 0x1f1f },
+ { 0x3d400204, 0x80808 },
+ { 0x3d400214, 0x7070707 },
+ { 0x3d400218, 0x68070707 },
+ { 0x3d40021c, 0xf08 },
+ { 0x3d400250, 0x1f05 },
+ { 0x3d400254, 0x1f },
+ { 0x3d400264, 0x90003ff },
+ { 0x3d40026c, 0x20003ff },
+ { 0x3d400400, 0x111 },
+ { 0x3d400408, 0x72ff },
+ { 0x3d400494, 0x1000e00 },
+ { 0x3d400498, 0x3ff0000 },
+ { 0x3d40049c, 0x1000e00 },
+ { 0x3d4004a0, 0x3ff0000 },
+ { 0x3d402020, 0x21 },
+ { 0x3d402024, 0x30d400 },
+ { 0x3d402050, 0x20d000 },
+ { 0x3d402064, 0xc001c },
+#else
{ 0x3d400108, 0x9121c1c },
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
{ 0x3d400200, 0x13 },
@@ -83,6 +138,7 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402024, 0x30d400 },
{ 0x3d402050, 0x20d000 },
{ 0x3d402064, 0xc0026 },
+#endif
{ 0x3d4020dc, 0x840000 },
{ 0x3d4020e0, 0x330000 },
{ 0x3d4020e8, 0x660048 },
@@ -104,10 +160,17 @@ struct dram_cfg_param ddr_ddrc_cfg[] = {
{ 0x3d402194, 0x80303 },
{ 0x3d4021b4, 0x100 },
{ 0x3d4020f4, 0xc99 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x3d403020, 0x21 },
+ { 0x3d403024, 0xc3500 },
+ { 0x3d403050, 0x20d000 },
+ { 0x3d403064, 0x30007 },
+#else
{ 0x3d403020, 0x1021 },
{ 0x3d403024, 0xc3500 },
{ 0x3d403050, 0x20d000 },
{ 0x3d403064, 0x3000a },
+#endif
{ 0x3d4030dc, 0x840000 },
{ 0x3d4030e0, 0x330000 },
{ 0x3d4030e8, 0x660048 },
@@ -200,7 +263,11 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x7055, 0x1ff },
{ 0x8055, 0x1ff },
{ 0x9055, 0x1ff },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x200c5, 0xa },
+#else
{ 0x200c5, 0x18 },
+#endif
{ 0x1200c5, 0x7 },
{ 0x2200c5, 0x7 },
{ 0x2002e, 0x2 },
@@ -279,7 +346,11 @@ struct dram_cfg_param ddr_ddrphy_cfg[] = {
{ 0x20018, 0x3 },
{ 0x20075, 0x4 },
{ 0x20050, 0x0 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x20008, 0x258 },
+#else
{ 0x20008, 0x3e8 },
+#endif
{ 0x120008, 0x64 },
{ 0x220008, 0x19 },
{ 0x20088, 0x9 },
@@ -1066,6 +1137,38 @@ struct dram_cfg_param ddr_ddrphy_trained_csr[] = {
/* P0 message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_cfg[] = {
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0xd0000, 0x0 },
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x131f },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400f, 0x100 },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x24c4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x24c4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xc400 },
+ { 0x54033, 0x3324 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xc400 },
+ { 0x54039, 0x3324 },
+#else
{ 0xd0000, 0x0 },
{ 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
@@ -1096,6 +1199,7 @@ struct dram_cfg_param ddr_fsp0_cfg[] = {
{ 0x54037, 0x1600 },
{ 0x54038, 0xf400 },
{ 0x54039, 0x333f },
+#endif
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1186,6 +1290,39 @@ struct dram_cfg_param ddr_fsp2_cfg[] = {
/* P0 2D message block paremeter for training firmware */
struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0xd0000, 0x0 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x54003, 0x960 },
+ { 0x54004, 0x2 },
+ { 0x54005, 0x2228 },
+ { 0x54006, 0x14 },
+ { 0x54008, 0x61 },
+ { 0x54009, 0xc8 },
+ { 0x5400b, 0x2 },
+ { 0x5400d, 0x100 },
+ { 0x5400f, 0x100 },
+ { 0x54010, 0x1f7f },
+ { 0x54012, 0x310 },
+ { 0x54019, 0x24c4 },
+ { 0x5401a, 0x33 },
+ { 0x5401b, 0x4866 },
+ { 0x5401c, 0x4800 },
+ { 0x5401e, 0x16 },
+ { 0x5401f, 0x24c4 },
+ { 0x54020, 0x33 },
+ { 0x54021, 0x4866 },
+ { 0x54022, 0x4800 },
+ { 0x54024, 0x16 },
+ { 0x5402b, 0x1000 },
+ { 0x5402c, 0x3 },
+ { 0x54032, 0xc400 },
+ { 0x54033, 0x3324 },
+ { 0x54034, 0x6600 },
+ { 0x54035, 0x48 },
+ { 0x54036, 0x48 },
+ { 0x54037, 0x1600 },
+ { 0x54038, 0xc400 },
+ { 0x54039, 0x3324 },
+#else
{ 0x54003, 0xfa0 },
{ 0x54004, 0x2 },
{ 0x54005, 0x2228 },
@@ -1217,6 +1354,7 @@ struct dram_cfg_param ddr_fsp0_2d_cfg[] = {
{ 0x54037, 0x1600 },
{ 0x54038, 0xf400 },
{ 0x54039, 0x333f },
+#endif
{ 0x5403a, 0x6600 },
{ 0x5403b, 0x48 },
{ 0x5403c, 0x48 },
@@ -1705,10 +1843,16 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x400d6, 0x20a },
{ 0x400d7, 0x20b },
{ 0x2003a, 0x2 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x2000b, 0x4b },
+ { 0x2000c, 0x96 },
+ { 0x2000d, 0x5dc },
+#else
{ 0x200be, 0x3 },
{ 0x2000b, 0x7d },
{ 0x2000c, 0xfa },
{ 0x2000d, 0x9c4 },
+#endif
{ 0x2000e, 0x2c },
{ 0x12000b, 0xc },
{ 0x12000c, 0x19 },
@@ -1728,6 +1872,12 @@ struct dram_cfg_param ddr_phy_pie[] = {
{ 0x90013, 0x6152 },
{ 0x20010, 0x5a },
{ 0x20011, 0x3 },
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ { 0x120010, 0x5a },
+ { 0x120011, 0x3 },
+ { 0x220010, 0x5a },
+ { 0x220011, 0x3 },
+#endif
{ 0x40080, 0xe0 },
{ 0x40081, 0x12 },
{ 0x40082, 0xe0 },
@@ -1811,8 +1961,13 @@ struct dram_cfg_param ddr_phy_pie[] = {
struct dram_fsp_msg ddr_dram_fsp_msg[] = {
{
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ /* P0 2400mts 1D */
+ .drate = 2400,
+#else
/* P0 4000mts 1D */
.drate = 4000,
+#endif
.fw_type = FW_1D_IMAGE,
.fsp_cfg = ddr_fsp0_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg),
@@ -1832,8 +1987,13 @@ struct dram_fsp_msg ddr_dram_fsp_msg[] = {
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp2_cfg),
},
{
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ /* P0 2400mts 2D */
+ .drate = 2400,
+#else
/* P0 4000mts 2D */
.drate = 4000,
+#endif
.fw_type = FW_2D_IMAGE,
.fsp_cfg = ddr_fsp0_2d_cfg,
.fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
@@ -1852,9 +2012,14 @@ struct dram_timing_info dram_timing = {
.ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr),
.ddrphy_pie = ddr_phy_pie,
.ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie),
+#ifdef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
+ .fsp_table = { 2400, 400, 100, },
+#else
.fsp_table = { 4000, 400, 100, },
+#endif
};
+#ifndef CONFIG_IMX8M_LPDDR4_FREQ0_2400MTS
#ifdef CONFIG_IMX8M_DRAM_INLINE_ECC
void board_dram_ecc_scrub(void)
{
@@ -1882,3 +2047,4 @@ void board_dram_ecc_scrub(void)
ddrc_inline_ecc_scrub_end(0x0, 0x5fffffff);
}
#endif
+#endif
diff --git a/board/freescale/imx8mp_evk/spl.c b/board/freescale/imx8mp_evk/spl.c
index ebfd94dc1f..3f043c2b2e 100644
--- a/board/freescale/imx8mp_evk/spl.c
+++ b/board/freescale/imx8mp_evk/spl.c
@@ -84,7 +84,12 @@ int power_init_board(void)
* Enable DVS control through PMIC_STBY_REQ and
* set B1_ENMODE=1 (ON by PMIC_ON_REQ=H)
*/
+#ifdef CONFIG_IMX8M_VDD_SOC_850MV
+ /* set DVS0 to 0.85v for special case*/
+ pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x14);
+#else
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS0, 0x1C);
+#endif
pmic_reg_write(p, PCA9450_BUCK1OUT_DVS1, 0x14);
pmic_reg_write(p, PCA9450_BUCK1CTRL, 0x59);
diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
index a5f5524fbe..a90b7db494 100644
--- a/drivers/ddr/imx/imx8m/Kconfig
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -36,4 +36,12 @@ config IMX8M_DRAM_INLINE_ECC
help
Select this config if you want to use inline ecc feature for
imx8mp-evk board.
+
+config IMX8M_VDD_SOC_850MV
+ bool "imx8mp change the vdd_soc voltage to 850mv"
+ depends on IMX8MP
+
+config IMX8M_LPDDR4_FREQ0_2400MTS
+ bool "imx8m PDDR4 freq0 change from 4000MTS to 2400MTS"
+
endmenu
--
2.30.0
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