[PATCH 22/26] imx8m: ddr: Disable CA VREF Training for LPDDR4

[Tim Harvey]

On Fri, Mar 19, 2021 at 12:31 AM Peng Fan (OSS) <peng.fan at oss.nxp.com> wrote:
>
> From: Ye Li <ye.li at nxp.com>
>
> Users reported LPDDR4 MR12 value is set to 0 during PHY training,
> not the value from FSP timing structure, which cause compliance test failed.
> The root cause is the CATrainOpt[0] is set to 1 in 2D FSP timing
> but not set in 1D.  According to PHY training application node,
> to enable the feature both 1D and 2D need set this field to 1,
> otherwise the training result will be incorrect.
> The PHY training doc also recommends to set CATrainOpt[0] to 0 to use
> MR12 value from message block (FSP structure). So update the LPDDR4
> scripts of all mscale to clear CATrainOpt[0].

Peng,

Is this issue being addressed by an update of the NXP i.MX 8M Family
DDR Tools app that generates this code? Is there a reference to this
issue online anywhere?

A bit unrelated but I would love to see NXP step up and replace the
silly NXP i.MX 8M Family DDR Tools windows app with code that could be
enabled in the SPL to do the same thing. Personally it's a bit of a
joke to require having a Windows PC around to bring up an ARM
processor board and I would hope there are folks at NXP that are
utterly ashamed at this as well. One could easily use the opensource
imx-usb-loader to load an SPL that performed this calibration and
training code.

Tim