[v1 03/17] arm: socfpga: Add handoff data support for Intel N5X device

[Siew Chin Lim]

N5X support both HPS handoff data and DDR handoff data.
HPS handoff data support re-use Straix10 and Agilex code. DDR
handoff data is newly introduced for N5X.

Signed-off-by: Siew Chin Lim <elly.siew.chin.lim at intel.com>
---
 arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 28 +++++++++++++++
 arch/arm/mach-socfpga/wrap_handoff_soc64.c         | 40 ++++++++++++++++++++++
 2 files changed, 68 insertions(+)

diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 3750216a9a..82e230421f 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -23,8 +23,36 @@
 #define SOC64_HANDOFF_OFFSET_DATA	0x10
 #define SOC64_HANDOFF_SIZE		4096
 
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10) || \
+	IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
 #define SOC64_HANDOFF_BASE		0xFFE3F000
 #define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+#define SOC64_HANDOFF_BASE		0xFFE5F000
+#define SOC64_HANDOFF_MISC		(SOC64_HANDOFF_BASE + 0x630)
+
+/* DDR handoff */
+#define SOC64_HANDOFF_DDR_BASE			0xFFE5C000
+#define SOC64_HANDOFF_DDR_MAGIC			0x48524444
+#define SOC64_HANDOFF_DDR_UMCTL2_MAGIC		0x4C54434D
+#define SOC64_HANDOFF_DDR_UMCTL2_DDR4_TYPE	0x34524444
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_0_TYPE	0x3044504C
+#define SOC64_HANDOFF_DDR_UMCTL2_LPDDR4_1_TYPE	0x3144504C
+#define SOC64_HANDOFF_DDR_MEMRESET_BASE		(SOC64_HANDOFF_DDR_BASE + 0xC)
+#define SOC64_HANDOFF_DDR_UMCTL2_SECTION	(SOC64_HANDOFF_DDR_BASE + 0x10)
+#define SOC64_HANDOFF_DDR_PHY_MAGIC		0x43594850
+#define SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC	0x45594850
+#define SOC64_HANDOFF_DDR_PHY_BASE_OFFSET	0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_TYPE_OFFSET	0x8
+#define SOC64_HANDOFF_DDR_UMCTL2_BASE_ADDR_OFFSET	0xC
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_1D_SECTION	0xFFE50000
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_1D_SECTION	0xFFE58000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_2D_SECTION	0xFFE44000
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_2D_SECTION	0xFFE4C000
+#define SOC64_HANDOFF_DDR_TRAIN_IMEM_LENGTH	SZ_32K
+#define SOC64_HANDOFF_DDR_TRAIN_DMEM_LENGTH	SZ_16K
+#endif
+
 #define SOC64_HANDOFF_MUX		(SOC64_HANDOFF_BASE + 0x10)
 #define SOC64_HANDOFF_IOCTL		(SOC64_HANDOFF_BASE + 0x1A0)
 #define SOC64_HANDOFF_FPGA		(SOC64_HANDOFF_BASE + 0x330)
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index a7ad7a18ed..37b4c360fb 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -60,6 +60,46 @@ int socfpga_handoff_read(void *handoff_address, void *table, u32 table_len,
 			debug("at addr  0x%p\n", (u32 *)handoff_address);
 			return -EPERM;
 		}
+	} else {
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
+		temp = readl(handoff_address);
+		if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC) {
+			debug("%s: umctl2 handoff data =\n{\n",
+			      __func__);
+		} else if (temp == SOC64_HANDOFF_DDR_PHY_MAGIC) {
+			debug("%s: PHY handoff data =\n{\n",
+			      __func__);
+		} else if (temp == SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
+			debug("%s: PHY engine handoff data =\n{\n",
+			      __func__);
+		}
+
+		debug("handoff table address = 0x%p table length = 0x%x\n",
+		      table_x32, table_len);
+
+		if (temp == SOC64_HANDOFF_DDR_UMCTL2_MAGIC ||
+		    temp == SOC64_HANDOFF_DDR_PHY_MAGIC ||
+		    temp == SOC64_HANDOFF_DDR_PHY_INIT_ENGINE_MAGIC) {
+			for (i = 0; i < table_len; i++) {
+				*table_x32 = readl(handoff_address +
+						SOC64_HANDOFF_OFFSET_DATA +
+						(i * 4));
+
+				if (!(i % 2))
+					debug(" No.%d Addr 0x%08x: ", i,
+					      *table_x32);
+				else
+					debug(" 0x%08x\n", *table_x32);
+
+				table_x32++;
+			}
+			debug("\n}\n");
+		} else {
+			debug("%s: Cannot find HANDOFF MAGIC ", __func__);
+			debug("at addr 0x%p\n", (u32 *)handoff_address);
+			return -EPERM;
+		}
+#endif
 	}
 
 	return 0;
-- 
2.13.0