[PATCH 14/15] ram: k3-ddrss: Introduce support for AM642 SoCs

Dave Gerlach d-gerlach at ti.com
Tue May 4 04:52:03 CEST 2021


Introduce support for the AM64 DDRSS controller which uses the 16bit
variation of the controller. This controller shares much functionality
with the existing J721e support, so this patch introduces only the new
code needed for am64 specific support from "_16bit_" files with headers
under "16bit/" include path/.

Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use
with CONFIG_K3_DDRSS to allow selecting AM64 support.

Signed-off-by: Dave Gerlach <d-gerlach at ti.com>
---
 drivers/ram/Kconfig                           |   13 +
 drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h  |  108 +
 .../ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h  |   14 +
 .../k3-ddrss/16bit/lpddr4_16bit_structs_if.h  |   15 +
 .../16bit/lpddr4_address_slice_0_macros.h     |  624 ++
 .../16bit/lpddr4_address_slice_1_macros.h     |  624 ++
 .../16bit/lpddr4_address_slice_2_macros.h     |  624 ++
 drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h  | 1306 ++++
 .../k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h |   23 +
 .../16bit/lpddr4_data_slice_0_macros.h        | 2036 ++++++
 .../16bit/lpddr4_data_slice_1_macros.h        | 2036 ++++++
 .../16bit/lpddr4_ddr_controller_macros.h      | 6436 +++++++++++++++++
 .../k3-ddrss/16bit/lpddr4_phy_core_macros.h   | 1838 +++++
 drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h | 5784 +++++++++++++++
 drivers/ram/k3-ddrss/Makefile                 |    4 +
 drivers/ram/k3-ddrss/k3-ddrss.c               |   10 +
 drivers/ram/k3-ddrss/lpddr4_16bit.c           |  396 +
 drivers/ram/k3-ddrss/lpddr4_16bit.h           |   33 +
 .../k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c | 1309 ++++
 drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h    |  257 +
 20 files changed, 23490 insertions(+)
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
 create mode 100644 drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
 create mode 100644 drivers/ram/k3-ddrss/lpddr4_16bit.c
 create mode 100644 drivers/ram/k3-ddrss/lpddr4_16bit.h
 create mode 100644 drivers/ram/k3-ddrss/lpddr4_16bit_ctl_regs_rw_masks.c
 create mode 100644 drivers/ram/k3-ddrss/lpddr4_16bit_sanity.h

diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 4e4e7a9632a6..a79594d35198 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -62,6 +62,9 @@ choice
 	depends on K3_DDRSS
 	prompt "K3 DDRSS Arch Support"
 
+	default K3_J721E_DDRSS if SOC_K3_J721E
+	default K3_AM64_DDRSS if SOC_K3_AM642
+
 config K3_J721E_DDRSS
 	bool "Enable J721E DDRSS support"
 	help
@@ -72,6 +75,16 @@ config K3_J721E_DDRSS
 	  Enabling this config adds support for the DDR memory controller
 	  on J721E family of SoCs.
 
+config K3_AM64_DDRSS
+	bool "Enable AM64 DDRSS support"
+	help
+	  The AM64 DDR subsystem comprises DDR controller, DDR PHY and
+	  wrapper logic to integrate these blocks in the device. The DDR
+	  subsystem is used to provide an interface to external SDRAM
+	  devices which can be utilized for storing program or data.
+	  Enabling this config adds support for the DDR memory controller
+	  on AM642 family of SoCs.
+
 endchoice
 
 config IMXRT_SDRAM
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
new file mode 100644
index 000000000000..ca9d5c57093e
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_if.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_IF_H
+#define LPDDR4_16BIT_IF_H
+
+#include "cdn_stdtypes.h"
+
+#define LPDDR4_INTR_MAX_CS (2U)
+
+#define LPDDR4_INTR_CTL_REG_COUNT (423U)
+
+#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U)
+
+#define LPDDR4_INTR_PHY_REG_COUNT (1406U)
+
+typedef enum {
+	LPDDR4_INTR_TIMEOUT_ZQ_CAL_INIT			= 0U,
+	LPDDR4_INTR_TIMEOUT_ZQ_CALLATCH			= 1U,
+	LPDDR4_INTR_TIMEOUT_ZQ_CALSTART			= 2U,
+	LPDDR4_INTR_TIMEOUT_MRR_TEMP			= 3U,
+	LPDDR4_INTR_TIMEOUT_DQS_OSC_REQ			= 4U,
+	LPDDR4_INTR_TIMEOUT_DFI_UPDATE			= 5U,
+	LPDDR4_INTR_TIMEOUT_LP_WAKEUP			= 6U,
+	LPDDR4_INTR_TIMEOUT_AUTO_REFRESH_MAX		= 7U,
+	LPDDR4_INTR_ECC_ERROR				= 8U,
+	LPDDR4_INTR_LP_DONE				= 9U,
+	LPDDR4_INTR_LP_TIMEOUT				= 10U,
+	LPDDR4_INTR_PORT_TIMEOUT			= 11U,
+	LPDDR4_INTR_RFIFO_TIMEOUT			= 12U,
+	LPDDR4_INTR_TRAINING_ZQ_STATUS			= 13U,
+	LPDDR4_INTR_TRAINING_DQS_OSC_DONE		= 14U,
+	LPDDR4_INTR_TRAINING_DQS_OSC_UPDATE_DONE	= 15U,
+	LPDDR4_INTR_TRAINING_DQS_OSC_OVERFLOW		= 16U,
+	LPDDR4_INTR_TRAINING_DQS_OSC_VAR_OUT		= 17U,
+	LPDDR4_INTR_USERIF_OUTSIDE_MEM_ACCESS		= 18U,
+	LPDDR4_INTR_USERIF_MULTI_OUTSIDE_MEM_ACCESS	= 19U,
+	LPDDR4_INTR_USERIF_PORT_CMD_ERROR		= 20U,
+	LPDDR4_INTR_USERIF_WRAP				= 21U,
+	LPDDR4_INTR_USERIF_INVAL_SETTING		= 22U,
+	LPDDR4_INTR_MISC_MRR_TRAFFIC			= 23U,
+	LPDDR4_INTR_MISC_SW_REQ_MODE			= 24U,
+	LPDDR4_INTR_MISC_CHANGE_TEMP_REFRESH		= 25U,
+	LPDDR4_INTR_MISC_TEMP_ALERT			= 26U,
+	LPDDR4_INTR_MISC_REFRESH_STATUS			= 27U,
+	LPDDR4_INTR_BIST_DONE				= 28U,
+	LPDDR4_INTR_CRC					= 29U,
+	LPDDR4_INTR_DFI_UPDATE_ERROR			= 30U,
+	LPDDR4_INTR_DFI_PHY_ERROR			= 31U,
+	LPDDR4_INTR_DFI_BUS_ERROR			= 32U,
+	LPDDR4_INTR_DFI_STATE_CHANGE			= 33U,
+	LPDDR4_INTR_DFI_DLL_SYNC_DONE			= 34U,
+	LPDDR4_INTR_DFI_TIMEOUT				= 35U,
+	LPDDR4_INTR_DIMM				= 36U,
+	LPDDR4_INTR_FREQ_DFS_REQ_HW_IGNORE		= 37U,
+	LPDDR4_INTR_FREQ_DFS_HW_TERMINATE		= 38U,
+	LPDDR4_INTR_FREQ_DFS_HW_DONE			= 39U,
+	LPDDR4_INTR_FREQ_DFS_REQ_SW_IGNORE		= 40U,
+	LPDDR4_INTR_FREQ_DFS_SW_TERMINATE		= 41U,
+	LPDDR4_INTR_FREQ_DFS_SW_DONE			= 42U,
+	LPDDR4_INTR_INIT_MEM_RESET_DONE			= 43U,
+	LPDDR4_INTR_MC_INIT_DONE			= 44U,
+	LPDDR4_INTR_INIT_POWER_ON_STATE			= 45U,
+	LPDDR4_INTR_MRR_ERROR				= 46U,
+	LPDDR4_INTR_MR_READ_DONE			= 47U,
+	LPDDR4_INTR_MR_WRITE_DONE			= 48U,
+	LPDDR4_INTR_PARITY_ERROR			= 49U,
+	LPDDR4_INTR_LOR_BITS				= 50U
+} lpddr4_intr_ctlinterrupt;
+
+typedef enum {
+	LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT		= 0U,
+	LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT		= 1U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT		= 2U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT		= 3U,
+	LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT		= 4U,
+	LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT		= 5U,
+	LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT		= 6U,
+	LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT		= 7U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT		= 8U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT	= 9U,
+	LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT		= 10U,
+	LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT		= 11U,
+	LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT		= 12U,
+	LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT		= 13U,
+	LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT		= 14U,
+	LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT	= 15U,
+	LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 16U,
+	LPDDR4_INTR_PHY_INDEP_MEM_RST_VALID_BIT		= 17U,
+	LPDDR4_INTR_PHY_INDEP_ZQ_STATUS_BIT		= 18U,
+	LPDDR4_INTR_PHY_INDEP_PERIPHERAL_MRR_DONE_BIT	= 19U,
+	LPDDR4_INTR_PHY_INDEP_WRITE_NODEREG_DONE_BIT	= 20U,
+	LPDDR4_INTR_PHY_INDEP_FREQ_CHANGE_DONE_BIT	= 21U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_G_DONE_BIT		= 22U,
+	LPDDR4_INTR_PHY_INDEP_RDLVL_DONE_BIT		= 23U,
+	LPDDR4_INTR_PHY_INDEP_WRLVL_DONE_BIT		= 24U,
+	LPDDR4_INTR_PHY_INDEP_CALVL_DONE__BIT		= 25U,
+	LPDDR4_INTR_PHY_INDEP_WDQLVL_DONE_BIT		= 26U,
+	LPDDR4_INTR_PHY_INDEP_VREF_DONE_BIT		= 27U,
+	LPDDR4_INTR_PHY_INDEP_ANY_VALID_BIT		= 28U
+} lpddr4_intr_phyindepinterrupt;
+
+#endif  /* LPDDR4_16BIT_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
new file mode 100644
index 000000000000..6c57dd9d00c2
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_obj_if.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_OBJ_IF_H
+#define LPDDR4_16BIT_OBJ_IF_H
+
+#include "lpddr4_16bit_if.h"
+
+#endif  /* LPDDR4_16BIT_OBJ_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
new file mode 100644
index 000000000000..104cb7e052a3
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_16bit_structs_if.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_16BIT_STRUCTS_IF_H
+#define LPDDR4_16BIT_STRUCTS_IF_H
+
+#include "cdn_stdtypes.h"
+#include "lpddr4_16bit_if.h"
+
+#endif  /* LPDDR4_16BIT_STRUCTS_IF_H */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
new file mode 100644
index 000000000000..f22a20a07c0b
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_0_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_512_READ_MASK                             0x000107FFU
+#define LPDDR4__DENALI_PHY_512_WRITE_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH    11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_512
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0_WOSET           0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_512
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_512__PHY_ADR_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0_WIDTH               3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__REG DENALI_PHY_512
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_512__SC_PHY_ADR_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_513_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0_WIDTH              32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__REG DENALI_PHY_513
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_513__PHY_ADR_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_514_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_514_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0_WIDTH         16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0_WIDTH           8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT   24U
+#define LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH    4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_514
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_514__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_515_READ_MASK                             0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_515_WRITE_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_MASK  0x007F0000U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0_WIDTH          7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH         8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_515
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_515__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_516_READ_MASK                             0x01000707U
+#define LPDDR4__DENALI_PHY_516_WRITE_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0_WIDTH         3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_MASK      0x00010000U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0_WOSET              0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG DENALI_PHY_516
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_516__SC_PHY_ADR_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0_WOSET                   0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__REG DENALI_PHY_516
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_516__PHY_ADR_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_517_READ_MASK                             0x011F7F7FU
+#define LPDDR4__DENALI_PHY_517_WRITE_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_MASK          0x0000007FU
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0_WIDTH                  7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_MASK    0x00007F00U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0_WIDTH            7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0_WIDTH             5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0_WOSET               0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__REG DENALI_PHY_517
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_517__PHY_ADR_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_518_READ_MASK                             0x01070301U
+#define LPDDR4__DENALI_PHY_518_WRITE_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH     1U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR     0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET     0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_MASK                  0x00000300U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0_WIDTH                          2U
+#define LPDDR4__PHY_ADR_TYPE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_TYPE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_TYPE_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_MASK      0x00070000U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0_WIDTH              3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_WRADDR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_MASK               0x01000000U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0_WOSET                       0U
+#define LPDDR4__PHY_ADR_IE_MODE_0__REG DENALI_PHY_518
+#define LPDDR4__PHY_ADR_IE_MODE_0__FLD LPDDR4__DENALI_PHY_518__PHY_ADR_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_519_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_MASK              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0_WIDTH                     27U
+#define LPDDR4__PHY_ADR_DDL_MODE_0__REG DENALI_PHY_519
+#define LPDDR4__PHY_ADR_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_519__PHY_ADR_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_520_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_520_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0_WIDTH                      6U
+#define LPDDR4__PHY_ADR_DDL_MASK_0__REG DENALI_PHY_520
+#define LPDDR4__PHY_ADR_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_520__PHY_ADR_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_521_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__REG DENALI_PHY_521
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_521__PHY_ADR_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_522_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0_WIDTH        32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_522
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_522__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_523_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_523_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0_WIDTH                  11U
+#define LPDDR4__PHY_ADR_CALVL_START_0__REG DENALI_PHY_523
+#define LPDDR4__PHY_ADR_CALVL_START_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_START_0
+
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_MASK      0x07FF0000U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0_WIDTH             11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__REG DENALI_PHY_523
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_0__FLD LPDDR4__DENALI_PHY_523__PHY_ADR_CALVL_COARSE_DLY_0
+
+#define LPDDR4__DENALI_PHY_524_READ_MASK                             0x000007FFU
+#define LPDDR4__DENALI_PHY_524_WRITE_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0_WIDTH                    11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__REG DENALI_PHY_524
+#define LPDDR4__PHY_ADR_CALVL_QTR_0__FLD LPDDR4__DENALI_PHY_524__PHY_ADR_CALVL_QTR_0
+
+#define LPDDR4__DENALI_PHY_525_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_MASK        0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0_WIDTH               24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__REG DENALI_PHY_525
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_525__PHY_ADR_CALVL_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_526_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_526_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_MASK        0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0_WIDTH               24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__REG DENALI_PHY_526
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_MASK       0x03000000U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0_WIDTH               2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__REG DENALI_PHY_526
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_0__FLD LPDDR4__DENALI_PHY_526__PHY_ADR_CALVL_RANK_CTRL_0
+
+#define LPDDR4__DENALI_PHY_527_READ_MASK                             0x01FF0F03U
+#define LPDDR4__DENALI_PHY_527_WRITE_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0_WIDTH            2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_NUM_PATTERNS_0
+
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_MASK   0x00000F00U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0_WIDTH           4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_SHIFT  16U
+#define LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0_WIDTH   9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__REG DENALI_PHY_527
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_527__PHY_ADR_CALVL_PERIODIC_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_528_READ_MASK                             0x07000001U
+#define LPDDR4__DENALI_PHY_528_WRITE_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0_WOSET              0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__REG DENALI_PHY_528
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__REG DENALI_PHY_528
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0_WOSET            0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__REG DENALI_PHY_528
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_0__FLD LPDDR4__DENALI_PHY_528__SC_PHY_ADR_CALVL_ERROR_CLR_0
+
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0_WIDTH              3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__REG DENALI_PHY_528
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_528__PHY_ADR_CALVL_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_529_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_0__REG DENALI_PHY_529
+#define LPDDR4__PHY_ADR_CALVL_OBS0_0__FLD LPDDR4__DENALI_PHY_529__PHY_ADR_CALVL_OBS0_0
+
+#define LPDDR4__DENALI_PHY_530_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__REG DENALI_PHY_530
+#define LPDDR4__PHY_ADR_CALVL_OBS1_0__FLD LPDDR4__DENALI_PHY_530__PHY_ADR_CALVL_OBS1_0
+
+#define LPDDR4__DENALI_PHY_531_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__REG DENALI_PHY_531
+#define LPDDR4__PHY_ADR_CALVL_OBS2_0__FLD LPDDR4__DENALI_PHY_531__PHY_ADR_CALVL_OBS2_0
+
+#define LPDDR4__DENALI_PHY_532_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__REG DENALI_PHY_532
+#define LPDDR4__PHY_ADR_CALVL_FG_0_0__FLD LPDDR4__DENALI_PHY_532__PHY_ADR_CALVL_FG_0_0
+
+#define LPDDR4__DENALI_PHY_533_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__REG DENALI_PHY_533
+#define LPDDR4__PHY_ADR_CALVL_BG_0_0__FLD LPDDR4__DENALI_PHY_533__PHY_ADR_CALVL_BG_0_0
+
+#define LPDDR4__DENALI_PHY_534_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__REG DENALI_PHY_534
+#define LPDDR4__PHY_ADR_CALVL_FG_1_0__FLD LPDDR4__DENALI_PHY_534__PHY_ADR_CALVL_FG_1_0
+
+#define LPDDR4__DENALI_PHY_535_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__REG DENALI_PHY_535
+#define LPDDR4__PHY_ADR_CALVL_BG_1_0__FLD LPDDR4__DENALI_PHY_535__PHY_ADR_CALVL_BG_1_0
+
+#define LPDDR4__DENALI_PHY_536_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__REG DENALI_PHY_536
+#define LPDDR4__PHY_ADR_CALVL_FG_2_0__FLD LPDDR4__DENALI_PHY_536__PHY_ADR_CALVL_FG_2_0
+
+#define LPDDR4__DENALI_PHY_537_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__REG DENALI_PHY_537
+#define LPDDR4__PHY_ADR_CALVL_BG_2_0__FLD LPDDR4__DENALI_PHY_537__PHY_ADR_CALVL_BG_2_0
+
+#define LPDDR4__DENALI_PHY_538_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__REG DENALI_PHY_538
+#define LPDDR4__PHY_ADR_CALVL_FG_3_0__FLD LPDDR4__DENALI_PHY_538__PHY_ADR_CALVL_FG_3_0
+
+#define LPDDR4__DENALI_PHY_539_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__REG DENALI_PHY_539
+#define LPDDR4__PHY_ADR_CALVL_BG_3_0__FLD LPDDR4__DENALI_PHY_539__PHY_ADR_CALVL_BG_3_0
+
+#define LPDDR4__DENALI_PHY_540_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540_WRITE_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0_WIDTH                     30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__REG DENALI_PHY_540
+#define LPDDR4__PHY_ADR_ADDR_SEL_0__FLD LPDDR4__DENALI_PHY_540__PHY_ADR_ADDR_SEL_0
+
+#define LPDDR4__DENALI_PHY_541_READ_MASK                             0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_541_WRITE_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_MASK    0x000003FFU
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0_WIDTH           10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_LP4_BOOT_SLV_DELAY_0
+
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0_WIDTH                      6U
+#define LPDDR4__PHY_ADR_BIT_MASK_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_BIT_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_BIT_MASK_0
+
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0_WIDTH                      6U
+#define LPDDR4__PHY_ADR_SEG_MASK_0__REG DENALI_PHY_541
+#define LPDDR4__PHY_ADR_SEG_MASK_0__FLD LPDDR4__DENALI_PHY_541__PHY_ADR_SEG_MASK_0
+
+#define LPDDR4__DENALI_PHY_542_READ_MASK                             0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_542_WRITE_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0_WIDTH              6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CALVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0_WIDTH              6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_CSLVL_TRAIN_MASK_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_MASK    0x000F0000U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0_WIDTH            4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0_WIDTH                  6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__REG DENALI_PHY_542
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_542__PHY_ADR_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_543_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_543_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0_WIDTH                 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__REG DENALI_PHY_543
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_543__PHY_ADR_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_544_READ_MASK                             0x0707FFFFU
+#define LPDDR4__DENALI_PHY_544_WRITE_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0_WIDTH                   8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_ADR_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_544__PHY_ADR_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_MASK            0x0007FF00U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0_WIDTH                   11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_MASK   0x07000000U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0_WIDTH           3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_544
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_544__PHY_PAD_ADR_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_545_READ_MASK                             0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_545_WRITE_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_MASK      0x0000001FU
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_MASK   0x0007FF00U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR0_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__REG DENALI_PHY_545
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_545__PHY_ADR1_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_546_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_546_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_546
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR1_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__REG DENALI_PHY_546
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_546__PHY_ADR2_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_547_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_547_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_547
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR2_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__REG DENALI_PHY_547
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_547__PHY_ADR3_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_548_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_548_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_548
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR3_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__REG DENALI_PHY_548
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_548__PHY_ADR4_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_549_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_549_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_549
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR4_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0_WIDTH              5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__REG DENALI_PHY_549
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_0__FLD LPDDR4__DENALI_PHY_549__PHY_ADR5_SW_WRADDR_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_550_READ_MASK                             0x000F07FFU
+#define LPDDR4__DENALI_PHY_550_WRITE_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__REG DENALI_PHY_550
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR5_CLK_WR_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0_WIDTH                4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__REG DENALI_PHY_550
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_550__PHY_ADR_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_551_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_551_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0_WIDTH           11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_MASK     0x003F0000U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0_WIDTH             6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_MASK     0xFF000000U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0_WIDTH             8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__REG DENALI_PHY_551
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_551__PHY_ADR_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_552_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_552_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0_WIDTH     8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_MASK      0x0003FF00U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_SHIFT              8U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0_WIDTH             10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0_WOSET           0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__REG DENALI_PHY_552
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_552__PHY_ADR_SW_CALVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_553_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_553_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0_WIDTH                4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__REG DENALI_PHY_553
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_553__PHY_ADR_CALVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_554_READ_MASK                             0x0000010FU
+#define LPDDR4__DENALI_PHY_554_WRITE_MASK                            0x0000010FU
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_MASK     0x0000000FU
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0_WIDTH             4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__REG DENALI_PHY_554
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_CALVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0_WOSET          0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_554
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_554__PHY_ADR_MEAS_DLY_STEP_ENABLE_0
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
new file mode 100644
index 000000000000..df5ab9516699
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_1_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_768_READ_MASK                             0x000107FFU
+#define LPDDR4__DENALI_PHY_768_WRITE_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH    11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_768
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1_WOSET           0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_768
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_768__PHY_ADR_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1_WIDTH               3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__REG DENALI_PHY_768
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_768__SC_PHY_ADR_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_769_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1_WIDTH              32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__REG DENALI_PHY_769
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_769__PHY_ADR_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_770_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_770_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_MASK  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1_WIDTH         16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_MASK   0x00FF0000U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1_WIDTH           8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT   24U
+#define LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH    4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_770
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_770__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_771_READ_MASK                             0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_771_WRITE_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_MASK  0x007F0000U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1_WIDTH          7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH         8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_771
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_771__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_772_READ_MASK                             0x01000707U
+#define LPDDR4__DENALI_PHY_772_WRITE_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1_WIDTH         3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_MASK      0x00010000U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1_WOSET              0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__REG DENALI_PHY_772
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_772__SC_PHY_ADR_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1_WOSET                   0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__REG DENALI_PHY_772
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_772__PHY_ADR_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_773_READ_MASK                             0x011F7F7FU
+#define LPDDR4__DENALI_PHY_773_WRITE_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_MASK          0x0000007FU
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1_WIDTH                  7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_MASK    0x00007F00U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_SHIFT            8U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1_WIDTH            7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1_WIDTH             5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1_WOSET               0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__REG DENALI_PHY_773
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_773__PHY_ADR_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_774_READ_MASK                             0x01070301U
+#define LPDDR4__DENALI_PHY_774_WRITE_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH     1U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR     0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET     0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_MASK                  0x00000300U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1_WIDTH                          2U
+#define LPDDR4__PHY_ADR_TYPE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_TYPE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_TYPE_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_MASK      0x00070000U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1_WIDTH              3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_WRADDR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_MASK               0x01000000U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1_WOSET                       0U
+#define LPDDR4__PHY_ADR_IE_MODE_1__REG DENALI_PHY_774
+#define LPDDR4__PHY_ADR_IE_MODE_1__FLD LPDDR4__DENALI_PHY_774__PHY_ADR_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_775_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_MASK              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1_WIDTH                     27U
+#define LPDDR4__PHY_ADR_DDL_MODE_1__REG DENALI_PHY_775
+#define LPDDR4__PHY_ADR_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_775__PHY_ADR_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_776_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_776_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1_WIDTH                      6U
+#define LPDDR4__PHY_ADR_DDL_MASK_1__REG DENALI_PHY_776
+#define LPDDR4__PHY_ADR_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_776__PHY_ADR_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_777_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1_WIDTH                 32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__REG DENALI_PHY_777
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_777__PHY_ADR_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_778_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1_WIDTH        32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_778
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_778__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_779_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_779_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1_WIDTH                  11U
+#define LPDDR4__PHY_ADR_CALVL_START_1__REG DENALI_PHY_779
+#define LPDDR4__PHY_ADR_CALVL_START_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_START_1
+
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_MASK      0x07FF0000U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1_WIDTH             11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__REG DENALI_PHY_779
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_1__FLD LPDDR4__DENALI_PHY_779__PHY_ADR_CALVL_COARSE_DLY_1
+
+#define LPDDR4__DENALI_PHY_780_READ_MASK                             0x000007FFU
+#define LPDDR4__DENALI_PHY_780_WRITE_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1_WIDTH                    11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__REG DENALI_PHY_780
+#define LPDDR4__PHY_ADR_CALVL_QTR_1__FLD LPDDR4__DENALI_PHY_780__PHY_ADR_CALVL_QTR_1
+
+#define LPDDR4__DENALI_PHY_781_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_MASK        0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1_WIDTH               24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__REG DENALI_PHY_781
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_781__PHY_ADR_CALVL_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_782_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_782_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_MASK        0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1_WIDTH               24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__REG DENALI_PHY_782
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_MASK       0x03000000U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1_WIDTH               2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__REG DENALI_PHY_782
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_1__FLD LPDDR4__DENALI_PHY_782__PHY_ADR_CALVL_RANK_CTRL_1
+
+#define LPDDR4__DENALI_PHY_783_READ_MASK                             0x01FF0F03U
+#define LPDDR4__DENALI_PHY_783_WRITE_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1_WIDTH            2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_NUM_PATTERNS_1
+
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_MASK   0x00000F00U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1_WIDTH           4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_SHIFT  16U
+#define LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1_WIDTH   9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__REG DENALI_PHY_783
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_783__PHY_ADR_CALVL_PERIODIC_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_784_READ_MASK                             0x07000001U
+#define LPDDR4__DENALI_PHY_784_WRITE_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_MASK      0x00000001U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1_WOSET              0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__REG DENALI_PHY_784
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__REG DENALI_PHY_784
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WIDTH            1U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOCLR            0U
+#define LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1_WOSET            0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__REG DENALI_PHY_784
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_1__FLD LPDDR4__DENALI_PHY_784__SC_PHY_ADR_CALVL_ERROR_CLR_1
+
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1_WIDTH              3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__REG DENALI_PHY_784
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_784__PHY_ADR_CALVL_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_785_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_1__REG DENALI_PHY_785
+#define LPDDR4__PHY_ADR_CALVL_OBS0_1__FLD LPDDR4__DENALI_PHY_785__PHY_ADR_CALVL_OBS0_1
+
+#define LPDDR4__DENALI_PHY_786_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__REG DENALI_PHY_786
+#define LPDDR4__PHY_ADR_CALVL_OBS1_1__FLD LPDDR4__DENALI_PHY_786__PHY_ADR_CALVL_OBS1_1
+
+#define LPDDR4__DENALI_PHY_787_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1_WIDTH                   32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__REG DENALI_PHY_787
+#define LPDDR4__PHY_ADR_CALVL_OBS2_1__FLD LPDDR4__DENALI_PHY_787__PHY_ADR_CALVL_OBS2_1
+
+#define LPDDR4__DENALI_PHY_788_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__REG DENALI_PHY_788
+#define LPDDR4__PHY_ADR_CALVL_FG_0_1__FLD LPDDR4__DENALI_PHY_788__PHY_ADR_CALVL_FG_0_1
+
+#define LPDDR4__DENALI_PHY_789_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__REG DENALI_PHY_789
+#define LPDDR4__PHY_ADR_CALVL_BG_0_1__FLD LPDDR4__DENALI_PHY_789__PHY_ADR_CALVL_BG_0_1
+
+#define LPDDR4__DENALI_PHY_790_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__REG DENALI_PHY_790
+#define LPDDR4__PHY_ADR_CALVL_FG_1_1__FLD LPDDR4__DENALI_PHY_790__PHY_ADR_CALVL_FG_1_1
+
+#define LPDDR4__DENALI_PHY_791_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__REG DENALI_PHY_791
+#define LPDDR4__PHY_ADR_CALVL_BG_1_1__FLD LPDDR4__DENALI_PHY_791__PHY_ADR_CALVL_BG_1_1
+
+#define LPDDR4__DENALI_PHY_792_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__REG DENALI_PHY_792
+#define LPDDR4__PHY_ADR_CALVL_FG_2_1__FLD LPDDR4__DENALI_PHY_792__PHY_ADR_CALVL_FG_2_1
+
+#define LPDDR4__DENALI_PHY_793_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__REG DENALI_PHY_793
+#define LPDDR4__PHY_ADR_CALVL_BG_2_1__FLD LPDDR4__DENALI_PHY_793__PHY_ADR_CALVL_BG_2_1
+
+#define LPDDR4__DENALI_PHY_794_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__REG DENALI_PHY_794
+#define LPDDR4__PHY_ADR_CALVL_FG_3_1__FLD LPDDR4__DENALI_PHY_794__PHY_ADR_CALVL_FG_3_1
+
+#define LPDDR4__DENALI_PHY_795_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1_WIDTH                   20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__REG DENALI_PHY_795
+#define LPDDR4__PHY_ADR_CALVL_BG_3_1__FLD LPDDR4__DENALI_PHY_795__PHY_ADR_CALVL_BG_3_1
+
+#define LPDDR4__DENALI_PHY_796_READ_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796_WRITE_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1_WIDTH                     30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__REG DENALI_PHY_796
+#define LPDDR4__PHY_ADR_ADDR_SEL_1__FLD LPDDR4__DENALI_PHY_796__PHY_ADR_ADDR_SEL_1
+
+#define LPDDR4__DENALI_PHY_797_READ_MASK                             0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_797_WRITE_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_MASK    0x000003FFU
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1_WIDTH           10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_LP4_BOOT_SLV_DELAY_1
+
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1_WIDTH                      6U
+#define LPDDR4__PHY_ADR_BIT_MASK_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_BIT_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_BIT_MASK_1
+
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1_WIDTH                      6U
+#define LPDDR4__PHY_ADR_SEG_MASK_1__REG DENALI_PHY_797
+#define LPDDR4__PHY_ADR_SEG_MASK_1__FLD LPDDR4__DENALI_PHY_797__PHY_ADR_SEG_MASK_1
+
+#define LPDDR4__DENALI_PHY_798_READ_MASK                             0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_798_WRITE_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1_WIDTH              6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CALVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_MASK      0x00003F00U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_SHIFT              8U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1_WIDTH              6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_CSLVL_TRAIN_MASK_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_MASK    0x000F0000U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1_WIDTH            4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1_WIDTH                  6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__REG DENALI_PHY_798
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_798__PHY_ADR_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_799_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_799_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1_WIDTH                 6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__REG DENALI_PHY_799
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_799__PHY_ADR_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_800_READ_MASK                             0x0707FFFFU
+#define LPDDR4__DENALI_PHY_800_WRITE_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1_WIDTH                   8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_ADR_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_800__PHY_ADR_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_MASK            0x0007FF00U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1_WIDTH                   11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_MASK   0x07000000U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1_WIDTH           3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_800
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_800__PHY_PAD_ADR_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_801_READ_MASK                             0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_801_WRITE_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_MASK      0x0000001FU
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_MASK   0x0007FF00U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR0_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__REG DENALI_PHY_801
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_801__PHY_ADR1_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_802_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_802_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_802
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR1_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__REG DENALI_PHY_802
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_802__PHY_ADR2_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_803_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_803_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_803
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR2_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__REG DENALI_PHY_803
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_803__PHY_ADR3_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_804_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_804_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_804
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR3_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__REG DENALI_PHY_804
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_804__PHY_ADR4_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_805_READ_MASK                             0x001F07FFU
+#define LPDDR4__DENALI_PHY_805_WRITE_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_805
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR4_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1_WIDTH              5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__REG DENALI_PHY_805
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_1__FLD LPDDR4__DENALI_PHY_805__PHY_ADR5_SW_WRADDR_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_806_READ_MASK                             0x000F07FFU
+#define LPDDR4__DENALI_PHY_806_WRITE_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1_WIDTH          11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__REG DENALI_PHY_806
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR5_CLK_WR_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1_WIDTH                4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__REG DENALI_PHY_806
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_806__PHY_ADR_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_807_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_807_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1_WIDTH           11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_MASK     0x003F0000U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1_WIDTH             6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_MASK     0xFF000000U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_SHIFT            24U
+#define LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1_WIDTH             8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__REG DENALI_PHY_807
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_807__PHY_ADR_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_808_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_808_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1_WIDTH     8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_MASK      0x0003FF00U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_SHIFT              8U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1_WIDTH             10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1_WOSET           0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__REG DENALI_PHY_808
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_808__PHY_ADR_SW_CALVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_809_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_809_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1_WIDTH                4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__REG DENALI_PHY_809
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_809__PHY_ADR_CALVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_810_READ_MASK                             0x0000010FU
+#define LPDDR4__DENALI_PHY_810_WRITE_MASK                            0x0000010FU
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_MASK     0x0000000FU
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1_WIDTH             4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__REG DENALI_PHY_810
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_CALVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1_WOSET          0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_810
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_810__PHY_ADR_MEAS_DLY_STEP_ENABLE_1
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
new file mode 100644
index 000000000000..924013e355df
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_address_slice_2_macros.h
@@ -0,0 +1,624 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+#define REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1024_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1024_WRITE_MASK                           0x000107FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2_WIDTH   11U
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_WR_BYPASS_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_MASK  0x00010000U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2_WOSET          0U
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__REG DENALI_PHY_1024
+#define LPDDR4__PHY_ADR_CLK_BYPASS_OVERRIDE_2__FLD LPDDR4__DENALI_PHY_1024__PHY_ADR_CLK_BYPASS_OVERRIDE_2
+
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_MASK      0x07000000U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2_WIDTH              3U
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__REG DENALI_PHY_1024
+#define LPDDR4__SC_PHY_ADR_MANUAL_CLEAR_2__FLD LPDDR4__DENALI_PHY_1024__SC_PHY_ADR_MANUAL_CLEAR_2
+
+#define LPDDR4__DENALI_PHY_1025_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2_WIDTH             32U
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__REG DENALI_PHY_1025
+#define LPDDR4__PHY_ADR_LPBK_RESULT_OBS_2__FLD LPDDR4__DENALI_PHY_1025__PHY_ADR_LPBK_RESULT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1026_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_SHIFT         0U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2_WIDTH        16U
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_LPBK_ERROR_COUNT_OBS_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_LPBK_ERROR_COUNT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_MASK  0x00FF0000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2_WIDTH          8U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_VALUE_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MEAS_DLY_STEP_VALUE_2
+
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_MASK 0x0F000000U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_SHIFT  24U
+#define LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2_WIDTH   4U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__REG DENALI_PHY_1026
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1026__PHY_ADR_MASTER_DLY_LOCK_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1027_READ_MASK                            0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027_WRITE_MASK                           0xFF7F07FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2_WIDTH         11U
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_MASTER_DLY_LOCK_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_MASTER_DLY_LOCK_OBS_2
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_MASK 0x007F0000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2_WIDTH         7U
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_BASE_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_SHIFT       24U
+#define LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2_WIDTH        8U
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__REG DENALI_PHY_1027
+#define LPDDR4__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2__FLD LPDDR4__DENALI_PHY_1027__PHY_ADR_ADDER_SLV_DLY_ENC_OBS_2
+
+#define LPDDR4__DENALI_PHY_1028_READ_MASK                            0x01000707U
+#define LPDDR4__DENALI_PHY_1028_WRITE_MASK                           0x01000707U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_MASK 0x00000007U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2_WIDTH        3U
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLAVE_LOOP_CNT_UPDATE_2
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_MASK 0x00000700U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_SHIFT       8U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2_WIDTH       3U
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_SLV_DLY_ENC_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_MASK     0x00010000U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2_WOSET             0U
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__REG DENALI_PHY_1028
+#define LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_2__FLD LPDDR4__DENALI_PHY_1028__SC_PHY_ADR_SNAP_OBS_REGS_2
+
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2_WOSET                  0U
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__REG DENALI_PHY_1028
+#define LPDDR4__PHY_ADR_TSEL_ENABLE_2__FLD LPDDR4__DENALI_PHY_1028__PHY_ADR_TSEL_ENABLE_2
+
+#define LPDDR4__DENALI_PHY_1029_READ_MASK                            0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029_WRITE_MASK                           0x011F7F7FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_MASK         0x0000007FU
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2_WIDTH                 7U
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_LPBK_CONTROL_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_LPBK_CONTROL_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_MASK   0x00007F00U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2_WIDTH           7U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_START_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_START_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_MASK    0x001F0000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2_WIDTH            5U
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PRBS_PATTERN_MASK_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PRBS_PATTERN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2_WOSET              0U
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__REG DENALI_PHY_1029
+#define LPDDR4__PHY_ADR_PWR_RDC_DISABLE_2__FLD LPDDR4__DENALI_PHY_1029__PHY_ADR_PWR_RDC_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1030_READ_MASK                            0x01070301U
+#define LPDDR4__DENALI_PHY_1030_WRITE_MASK                           0x01070301U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WIDTH    1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOCLR    0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2_WOSET    0U
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_SLV_DLY_CTRL_GATE_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_MASK                 0x00000300U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2_WIDTH                         2U
+#define LPDDR4__PHY_ADR_TYPE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_TYPE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_TYPE_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_MASK     0x00070000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2_WIDTH             3U
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_WRADDR_SHIFT_OBS_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_WRADDR_SHIFT_OBS_2
+
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_MASK              0x01000000U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2_WOSET                      0U
+#define LPDDR4__PHY_ADR_IE_MODE_2__REG DENALI_PHY_1030
+#define LPDDR4__PHY_ADR_IE_MODE_2__FLD LPDDR4__DENALI_PHY_1030__PHY_ADR_IE_MODE_2
+
+#define LPDDR4__DENALI_PHY_1031_READ_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031_WRITE_MASK                           0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_MASK             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2_WIDTH                    27U
+#define LPDDR4__PHY_ADR_DDL_MODE_2__REG DENALI_PHY_1031
+#define LPDDR4__PHY_ADR_DDL_MODE_2__FLD LPDDR4__DENALI_PHY_1031__PHY_ADR_DDL_MODE_2
+
+#define LPDDR4__DENALI_PHY_1032_READ_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_1032_WRITE_MASK                           0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_DDL_MASK_2__REG DENALI_PHY_1032
+#define LPDDR4__PHY_ADR_DDL_MASK_2__FLD LPDDR4__DENALI_PHY_1032__PHY_ADR_DDL_MASK_2
+
+#define LPDDR4__DENALI_PHY_1033_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2_WIDTH                32U
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__REG DENALI_PHY_1033
+#define LPDDR4__PHY_ADR_DDL_TEST_OBS_2__FLD LPDDR4__DENALI_PHY_1033__PHY_ADR_DDL_TEST_OBS_2
+
+#define LPDDR4__DENALI_PHY_1034_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_SHIFT        0U
+#define LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2_WIDTH       32U
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__REG DENALI_PHY_1034
+#define LPDDR4__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2__FLD LPDDR4__DENALI_PHY_1034__PHY_ADR_DDL_TEST_MSTR_DLY_OBS_2
+
+#define LPDDR4__DENALI_PHY_1035_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_MASK          0x000007FFU
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2_WIDTH                 11U
+#define LPDDR4__PHY_ADR_CALVL_START_2__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_START_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_START_2
+
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2_WIDTH            11U
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__REG DENALI_PHY_1035
+#define LPDDR4__PHY_ADR_CALVL_COARSE_DLY_2__FLD LPDDR4__DENALI_PHY_1035__PHY_ADR_CALVL_COARSE_DLY_2
+
+#define LPDDR4__DENALI_PHY_1036_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1036_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2_WIDTH                   11U
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__REG DENALI_PHY_1036
+#define LPDDR4__PHY_ADR_CALVL_QTR_2__FLD LPDDR4__DENALI_PHY_1036__PHY_ADR_CALVL_QTR_2
+
+#define LPDDR4__DENALI_PHY_1037_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__REG DENALI_PHY_1037
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE0_2__FLD LPDDR4__DENALI_PHY_1037__PHY_ADR_CALVL_SWIZZLE0_2
+
+#define LPDDR4__DENALI_PHY_1038_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038_WRITE_MASK                           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_MASK       0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2_WIDTH              24U
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_SWIZZLE1_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_SWIZZLE1_2
+
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_MASK      0x03000000U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_SHIFT             24U
+#define LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2_WIDTH              2U
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__REG DENALI_PHY_1038
+#define LPDDR4__PHY_ADR_CALVL_RANK_CTRL_2__FLD LPDDR4__DENALI_PHY_1038__PHY_ADR_CALVL_RANK_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1039_READ_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039_WRITE_MASK                           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2_WIDTH           2U
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_NUM_PATTERNS_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_NUM_PATTERNS_2
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_MASK  0x00000F00U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2_WIDTH          4U
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_RESP_WAIT_CNT_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_RESP_WAIT_CNT_2
+
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_MASK 0x01FF0000U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_SHIFT 16U
+#define LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2_WIDTH  9U
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__REG DENALI_PHY_1039
+#define LPDDR4__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2__FLD LPDDR4__DENALI_PHY_1039__PHY_ADR_CALVL_PERIODIC_START_OFFSET_2
+
+#define LPDDR4__DENALI_PHY_1040_READ_MASK                            0x07000001U
+#define LPDDR4__DENALI_PHY_1040_WRITE_MASK                           0x07000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2_WOSET             0U
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_DEBUG_MODE_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_DEBUG_MODE_2
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_MASK  0x00000100U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2_WOSET          0U
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_DEBUG_CONT_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_DEBUG_CONT_2
+
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2_WOSET           0U
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__REG DENALI_PHY_1040
+#define LPDDR4__SC_PHY_ADR_CALVL_ERROR_CLR_2__FLD LPDDR4__DENALI_PHY_1040__SC_PHY_ADR_CALVL_ERROR_CLR_2
+
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_MASK     0x07000000U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2_WIDTH             3U
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__REG DENALI_PHY_1040
+#define LPDDR4__PHY_ADR_CALVL_OBS_SELECT_2__FLD LPDDR4__DENALI_PHY_1040__PHY_ADR_CALVL_OBS_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1041_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS0_2__REG DENALI_PHY_1041
+#define LPDDR4__PHY_ADR_CALVL_OBS0_2__FLD LPDDR4__DENALI_PHY_1041__PHY_ADR_CALVL_OBS0_2
+
+#define LPDDR4__DENALI_PHY_1042_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__REG DENALI_PHY_1042
+#define LPDDR4__PHY_ADR_CALVL_OBS1_2__FLD LPDDR4__DENALI_PHY_1042__PHY_ADR_CALVL_OBS1_2
+
+#define LPDDR4__DENALI_PHY_1043_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2_WIDTH                  32U
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__REG DENALI_PHY_1043
+#define LPDDR4__PHY_ADR_CALVL_OBS2_2__FLD LPDDR4__DENALI_PHY_1043__PHY_ADR_CALVL_OBS2_2
+
+#define LPDDR4__DENALI_PHY_1044_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__REG DENALI_PHY_1044
+#define LPDDR4__PHY_ADR_CALVL_FG_0_2__FLD LPDDR4__DENALI_PHY_1044__PHY_ADR_CALVL_FG_0_2
+
+#define LPDDR4__DENALI_PHY_1045_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__REG DENALI_PHY_1045
+#define LPDDR4__PHY_ADR_CALVL_BG_0_2__FLD LPDDR4__DENALI_PHY_1045__PHY_ADR_CALVL_BG_0_2
+
+#define LPDDR4__DENALI_PHY_1046_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__REG DENALI_PHY_1046
+#define LPDDR4__PHY_ADR_CALVL_FG_1_2__FLD LPDDR4__DENALI_PHY_1046__PHY_ADR_CALVL_FG_1_2
+
+#define LPDDR4__DENALI_PHY_1047_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__REG DENALI_PHY_1047
+#define LPDDR4__PHY_ADR_CALVL_BG_1_2__FLD LPDDR4__DENALI_PHY_1047__PHY_ADR_CALVL_BG_1_2
+
+#define LPDDR4__DENALI_PHY_1048_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__REG DENALI_PHY_1048
+#define LPDDR4__PHY_ADR_CALVL_FG_2_2__FLD LPDDR4__DENALI_PHY_1048__PHY_ADR_CALVL_FG_2_2
+
+#define LPDDR4__DENALI_PHY_1049_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__REG DENALI_PHY_1049
+#define LPDDR4__PHY_ADR_CALVL_BG_2_2__FLD LPDDR4__DENALI_PHY_1049__PHY_ADR_CALVL_BG_2_2
+
+#define LPDDR4__DENALI_PHY_1050_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__REG DENALI_PHY_1050
+#define LPDDR4__PHY_ADR_CALVL_FG_3_2__FLD LPDDR4__DENALI_PHY_1050__PHY_ADR_CALVL_FG_3_2
+
+#define LPDDR4__DENALI_PHY_1051_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_MASK           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2_WIDTH                  20U
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__REG DENALI_PHY_1051
+#define LPDDR4__PHY_ADR_CALVL_BG_3_2__FLD LPDDR4__DENALI_PHY_1051__PHY_ADR_CALVL_BG_3_2
+
+#define LPDDR4__DENALI_PHY_1052_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2_WIDTH                    30U
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__REG DENALI_PHY_1052
+#define LPDDR4__PHY_ADR_ADDR_SEL_2__FLD LPDDR4__DENALI_PHY_1052__PHY_ADR_ADDR_SEL_2
+
+#define LPDDR4__DENALI_PHY_1053_READ_MASK                            0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1053_WRITE_MASK                           0x3F3F03FFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2_WIDTH          10U
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_LP4_BOOT_SLV_DELAY_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_LP4_BOOT_SLV_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_MASK             0x003F0000U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_BIT_MASK_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_BIT_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_BIT_MASK_2
+
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_MASK             0x3F000000U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2_WIDTH                     6U
+#define LPDDR4__PHY_ADR_SEG_MASK_2__REG DENALI_PHY_1053
+#define LPDDR4__PHY_ADR_SEG_MASK_2__FLD LPDDR4__DENALI_PHY_1053__PHY_ADR_SEG_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054_READ_MASK                            0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1054_WRITE_MASK                           0x3F0F3F3FU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2_WIDTH             6U
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_CALVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CALVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_MASK     0x00003F00U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2_WIDTH             6U
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_CSLVL_TRAIN_MASK_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_CSLVL_TRAIN_MASK_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2_WIDTH           4U
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_STATIC_TOG_DISABLE_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_STATIC_TOG_DISABLE_2
+
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2_WIDTH                 6U
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__REG DENALI_PHY_1054
+#define LPDDR4__PHY_ADR_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1054__PHY_ADR_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1055_READ_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_1055_WRITE_MASK                           0x0000003FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_MASK        0x0000003FU
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2_WIDTH                6U
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__REG DENALI_PHY_1055
+#define LPDDR4__PHY_ADR_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1055__PHY_ADR_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1056_READ_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1056_WRITE_MASK                           0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2_WIDTH                  8U
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_ADR_TSEL_SELECT_2__FLD LPDDR4__DENALI_PHY_1056__PHY_ADR_TSEL_SELECT_2
+
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_MASK           0x0007FF00U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2_WIDTH                  11U
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_PAD_ADR_IO_CFG_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_IO_CFG_2
+
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_MASK  0x07000000U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2_WIDTH          3U
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__REG DENALI_PHY_1056
+#define LPDDR4__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2__FLD LPDDR4__DENALI_PHY_1056__PHY_PAD_ADR_RX_PCLK_CLK_SEL_2
+
+#define LPDDR4__DENALI_PHY_1057_READ_MASK                            0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1057_WRITE_MASK                           0x1F07FF1FU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_MASK     0x0000001FU
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR0_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_MASK  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR0_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR0_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_MASK     0x1F000000U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1057
+#define LPDDR4__PHY_ADR1_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1057__PHY_ADR1_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1058_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1058_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR1_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR1_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1058
+#define LPDDR4__PHY_ADR2_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1058__PHY_ADR2_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1059_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1059_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR2_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR2_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1059
+#define LPDDR4__PHY_ADR3_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1059__PHY_ADR3_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1060_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1060_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR3_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR3_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1060
+#define LPDDR4__PHY_ADR4_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1060__PHY_ADR4_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1061_READ_MASK                            0x001F07FFU
+#define LPDDR4__DENALI_PHY_1061_WRITE_MASK                           0x001F07FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR4_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR4_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_MASK     0x001F0000U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2_WIDTH             5U
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__REG DENALI_PHY_1061
+#define LPDDR4__PHY_ADR5_SW_WRADDR_SHIFT_2__FLD LPDDR4__DENALI_PHY_1061__PHY_ADR5_SW_WRADDR_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1062_READ_MASK                            0x000F07FFU
+#define LPDDR4__DENALI_PHY_1062_WRITE_MASK                           0x000F07FFU
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_MASK  0x000007FFU
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2_WIDTH         11U
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR5_CLK_WR_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR5_CLK_WR_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2_WIDTH               4U
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__REG DENALI_PHY_1062
+#define LPDDR4__PHY_ADR_SW_MASTER_MODE_2__FLD LPDDR4__DENALI_PHY_1062__PHY_ADR_SW_MASTER_MODE_2
+
+#define LPDDR4__DENALI_PHY_1063_READ_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1063_WRITE_MASK                           0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_MASK   0x000007FFU
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2_WIDTH          11U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_START_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_START_2
+
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_MASK    0x003F0000U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2_WIDTH            6U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_STEP_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_MASK    0xFF000000U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_SHIFT           24U
+#define LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2_WIDTH            8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__REG DENALI_PHY_1063
+#define LPDDR4__PHY_ADR_MASTER_DELAY_WAIT_2__FLD LPDDR4__DENALI_PHY_1063__PHY_ADR_MASTER_DELAY_WAIT_2
+
+#define LPDDR4__DENALI_PHY_1064_READ_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1064_WRITE_MASK                           0x0103FFFFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_SHIFT    0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2_WIDTH    8U
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_MASTER_DELAY_HALF_MEASURE_2
+
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_MASK     0x0003FF00U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2_WIDTH            10U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_2
+
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_MASK  0x01000000U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2_WOSET          0U
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__REG DENALI_PHY_1064
+#define LPDDR4__PHY_ADR_SW_CALVL_DVW_MIN_EN_2__FLD LPDDR4__DENALI_PHY_1064__PHY_ADR_SW_CALVL_DVW_MIN_EN_2
+
+#define LPDDR4__DENALI_PHY_1065_READ_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_1065_WRITE_MASK                           0x0000000FU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2_WIDTH               4U
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__REG DENALI_PHY_1065
+#define LPDDR4__PHY_ADR_CALVL_DLY_STEP_2__FLD LPDDR4__DENALI_PHY_1065__PHY_ADR_CALVL_DLY_STEP_2
+
+#define LPDDR4__DENALI_PHY_1066_READ_MASK                            0x0000010FU
+#define LPDDR4__DENALI_PHY_1066_WRITE_MASK                           0x0000010FU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2_WIDTH            4U
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR_CALVL_CAPTURE_CNT_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_CALVL_CAPTURE_CNT_2
+
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_SHIFT         8U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WIDTH         1U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOCLR         0U
+#define LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2_WOSET         0U
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__REG DENALI_PHY_1066
+#define LPDDR4__PHY_ADR_MEAS_DLY_STEP_ENABLE_2__FLD LPDDR4__DENALI_PHY_1066__PHY_ADR_MEAS_DLY_STEP_ENABLE_2
+
+#endif /* REG_LPDDR4_ADDRESS_SLICE_2_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
new file mode 100644
index 000000000000..21e96c9a9044
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs.h
@@ -0,0 +1,1306 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_CTL_REGS_H_
+#define REG_LPDDR4_CTL_REGS_H_
+
+#include "lpddr4_ddr_controller_macros.h"
+#include "lpddr4_pi_macros.h"
+#include "lpddr4_data_slice_0_macros.h"
+#include "lpddr4_data_slice_1_macros.h"
+#include "lpddr4_address_slice_0_macros.h"
+#include "lpddr4_address_slice_1_macros.h"
+#include "lpddr4_address_slice_2_macros.h"
+#include "lpddr4_phy_core_macros.h"
+
+typedef struct __attribute__((packed)) lpddr4_ctlregs_s {
+	volatile u32 DENALI_CTL_0;
+	volatile u32 DENALI_CTL_1;
+	volatile u32 DENALI_CTL_2;
+	volatile u32 DENALI_CTL_3;
+	volatile u32 DENALI_CTL_4;
+	volatile u32 DENALI_CTL_5;
+	volatile u32 DENALI_CTL_6;
+	volatile u32 DENALI_CTL_7;
+	volatile u32 DENALI_CTL_8;
+	volatile u32 DENALI_CTL_9;
+	volatile u32 DENALI_CTL_10;
+	volatile u32 DENALI_CTL_11;
+	volatile u32 DENALI_CTL_12;
+	volatile u32 DENALI_CTL_13;
+	volatile u32 DENALI_CTL_14;
+	volatile u32 DENALI_CTL_15;
+	volatile u32 DENALI_CTL_16;
+	volatile u32 DENALI_CTL_17;
+	volatile u32 DENALI_CTL_18;
+	volatile u32 DENALI_CTL_19;
+	volatile u32 DENALI_CTL_20;
+	volatile u32 DENALI_CTL_21;
+	volatile u32 DENALI_CTL_22;
+	volatile u32 DENALI_CTL_23;
+	volatile u32 DENALI_CTL_24;
+	volatile u32 DENALI_CTL_25;
+	volatile u32 DENALI_CTL_26;
+	volatile u32 DENALI_CTL_27;
+	volatile u32 DENALI_CTL_28;
+	volatile u32 DENALI_CTL_29;
+	volatile u32 DENALI_CTL_30;
+	volatile u32 DENALI_CTL_31;
+	volatile u32 DENALI_CTL_32;
+	volatile u32 DENALI_CTL_33;
+	volatile u32 DENALI_CTL_34;
+	volatile u32 DENALI_CTL_35;
+	volatile u32 DENALI_CTL_36;
+	volatile u32 DENALI_CTL_37;
+	volatile u32 DENALI_CTL_38;
+	volatile u32 DENALI_CTL_39;
+	volatile u32 DENALI_CTL_40;
+	volatile u32 DENALI_CTL_41;
+	volatile u32 DENALI_CTL_42;
+	volatile u32 DENALI_CTL_43;
+	volatile u32 DENALI_CTL_44;
+	volatile u32 DENALI_CTL_45;
+	volatile u32 DENALI_CTL_46;
+	volatile u32 DENALI_CTL_47;
+	volatile u32 DENALI_CTL_48;
+	volatile u32 DENALI_CTL_49;
+	volatile u32 DENALI_CTL_50;
+	volatile u32 DENALI_CTL_51;
+	volatile u32 DENALI_CTL_52;
+	volatile u32 DENALI_CTL_53;
+	volatile u32 DENALI_CTL_54;
+	volatile u32 DENALI_CTL_55;
+	volatile u32 DENALI_CTL_56;
+	volatile u32 DENALI_CTL_57;
+	volatile u32 DENALI_CTL_58;
+	volatile u32 DENALI_CTL_59;
+	volatile u32 DENALI_CTL_60;
+	volatile u32 DENALI_CTL_61;
+	volatile u32 DENALI_CTL_62;
+	volatile u32 DENALI_CTL_63;
+	volatile u32 DENALI_CTL_64;
+	volatile u32 DENALI_CTL_65;
+	volatile u32 DENALI_CTL_66;
+	volatile u32 DENALI_CTL_67;
+	volatile u32 DENALI_CTL_68;
+	volatile u32 DENALI_CTL_69;
+	volatile u32 DENALI_CTL_70;
+	volatile u32 DENALI_CTL_71;
+	volatile u32 DENALI_CTL_72;
+	volatile u32 DENALI_CTL_73;
+	volatile u32 DENALI_CTL_74;
+	volatile u32 DENALI_CTL_75;
+	volatile u32 DENALI_CTL_76;
+	volatile u32 DENALI_CTL_77;
+	volatile u32 DENALI_CTL_78;
+	volatile u32 DENALI_CTL_79;
+	volatile u32 DENALI_CTL_80;
+	volatile u32 DENALI_CTL_81;
+	volatile u32 DENALI_CTL_82;
+	volatile u32 DENALI_CTL_83;
+	volatile u32 DENALI_CTL_84;
+	volatile u32 DENALI_CTL_85;
+	volatile u32 DENALI_CTL_86;
+	volatile u32 DENALI_CTL_87;
+	volatile u32 DENALI_CTL_88;
+	volatile u32 DENALI_CTL_89;
+	volatile u32 DENALI_CTL_90;
+	volatile u32 DENALI_CTL_91;
+	volatile u32 DENALI_CTL_92;
+	volatile u32 DENALI_CTL_93;
+	volatile u32 DENALI_CTL_94;
+	volatile u32 DENALI_CTL_95;
+	volatile u32 DENALI_CTL_96;
+	volatile u32 DENALI_CTL_97;
+	volatile u32 DENALI_CTL_98;
+	volatile u32 DENALI_CTL_99;
+	volatile u32 DENALI_CTL_100;
+	volatile u32 DENALI_CTL_101;
+	volatile u32 DENALI_CTL_102;
+	volatile u32 DENALI_CTL_103;
+	volatile u32 DENALI_CTL_104;
+	volatile u32 DENALI_CTL_105;
+	volatile u32 DENALI_CTL_106;
+	volatile u32 DENALI_CTL_107;
+	volatile u32 DENALI_CTL_108;
+	volatile u32 DENALI_CTL_109;
+	volatile u32 DENALI_CTL_110;
+	volatile u32 DENALI_CTL_111;
+	volatile u32 DENALI_CTL_112;
+	volatile u32 DENALI_CTL_113;
+	volatile u32 DENALI_CTL_114;
+	volatile u32 DENALI_CTL_115;
+	volatile u32 DENALI_CTL_116;
+	volatile u32 DENALI_CTL_117;
+	volatile u32 DENALI_CTL_118;
+	volatile u32 DENALI_CTL_119;
+	volatile u32 DENALI_CTL_120;
+	volatile u32 DENALI_CTL_121;
+	volatile u32 DENALI_CTL_122;
+	volatile u32 DENALI_CTL_123;
+	volatile u32 DENALI_CTL_124;
+	volatile u32 DENALI_CTL_125;
+	volatile u32 DENALI_CTL_126;
+	volatile u32 DENALI_CTL_127;
+	volatile u32 DENALI_CTL_128;
+	volatile u32 DENALI_CTL_129;
+	volatile u32 DENALI_CTL_130;
+	volatile u32 DENALI_CTL_131;
+	volatile u32 DENALI_CTL_132;
+	volatile u32 DENALI_CTL_133;
+	volatile u32 DENALI_CTL_134;
+	volatile u32 DENALI_CTL_135;
+	volatile u32 DENALI_CTL_136;
+	volatile u32 DENALI_CTL_137;
+	volatile u32 DENALI_CTL_138;
+	volatile u32 DENALI_CTL_139;
+	volatile u32 DENALI_CTL_140;
+	volatile u32 DENALI_CTL_141;
+	volatile u32 DENALI_CTL_142;
+	volatile u32 DENALI_CTL_143;
+	volatile u32 DENALI_CTL_144;
+	volatile u32 DENALI_CTL_145;
+	volatile u32 DENALI_CTL_146;
+	volatile u32 DENALI_CTL_147;
+	volatile u32 DENALI_CTL_148;
+	volatile u32 DENALI_CTL_149;
+	volatile u32 DENALI_CTL_150;
+	volatile u32 DENALI_CTL_151;
+	volatile u32 DENALI_CTL_152;
+	volatile u32 DENALI_CTL_153;
+	volatile u32 DENALI_CTL_154;
+	volatile u32 DENALI_CTL_155;
+	volatile u32 DENALI_CTL_156;
+	volatile u32 DENALI_CTL_157;
+	volatile u32 DENALI_CTL_158;
+	volatile u32 DENALI_CTL_159;
+	volatile u32 DENALI_CTL_160;
+	volatile u32 DENALI_CTL_161;
+	volatile u32 DENALI_CTL_162;
+	volatile u32 DENALI_CTL_163;
+	volatile u32 DENALI_CTL_164;
+	volatile u32 DENALI_CTL_165;
+	volatile u32 DENALI_CTL_166;
+	volatile u32 DENALI_CTL_167;
+	volatile u32 DENALI_CTL_168;
+	volatile u32 DENALI_CTL_169;
+	volatile u32 DENALI_CTL_170;
+	volatile u32 DENALI_CTL_171;
+	volatile u32 DENALI_CTL_172;
+	volatile u32 DENALI_CTL_173;
+	volatile u32 DENALI_CTL_174;
+	volatile u32 DENALI_CTL_175;
+	volatile u32 DENALI_CTL_176;
+	volatile u32 DENALI_CTL_177;
+	volatile u32 DENALI_CTL_178;
+	volatile u32 DENALI_CTL_179;
+	volatile u32 DENALI_CTL_180;
+	volatile u32 DENALI_CTL_181;
+	volatile u32 DENALI_CTL_182;
+	volatile u32 DENALI_CTL_183;
+	volatile u32 DENALI_CTL_184;
+	volatile u32 DENALI_CTL_185;
+	volatile u32 DENALI_CTL_186;
+	volatile u32 DENALI_CTL_187;
+	volatile u32 DENALI_CTL_188;
+	volatile u32 DENALI_CTL_189;
+	volatile u32 DENALI_CTL_190;
+	volatile u32 DENALI_CTL_191;
+	volatile u32 DENALI_CTL_192;
+	volatile u32 DENALI_CTL_193;
+	volatile u32 DENALI_CTL_194;
+	volatile u32 DENALI_CTL_195;
+	volatile u32 DENALI_CTL_196;
+	volatile u32 DENALI_CTL_197;
+	volatile u32 DENALI_CTL_198;
+	volatile u32 DENALI_CTL_199;
+	volatile u32 DENALI_CTL_200;
+	volatile u32 DENALI_CTL_201;
+	volatile u32 DENALI_CTL_202;
+	volatile u32 DENALI_CTL_203;
+	volatile u32 DENALI_CTL_204;
+	volatile u32 DENALI_CTL_205;
+	volatile u32 DENALI_CTL_206;
+	volatile u32 DENALI_CTL_207;
+	volatile u32 DENALI_CTL_208;
+	volatile u32 DENALI_CTL_209;
+	volatile u32 DENALI_CTL_210;
+	volatile u32 DENALI_CTL_211;
+	volatile u32 DENALI_CTL_212;
+	volatile u32 DENALI_CTL_213;
+	volatile u32 DENALI_CTL_214;
+	volatile u32 DENALI_CTL_215;
+	volatile u32 DENALI_CTL_216;
+	volatile u32 DENALI_CTL_217;
+	volatile u32 DENALI_CTL_218;
+	volatile u32 DENALI_CTL_219;
+	volatile u32 DENALI_CTL_220;
+	volatile u32 DENALI_CTL_221;
+	volatile u32 DENALI_CTL_222;
+	volatile u32 DENALI_CTL_223;
+	volatile u32 DENALI_CTL_224;
+	volatile u32 DENALI_CTL_225;
+	volatile u32 DENALI_CTL_226;
+	volatile u32 DENALI_CTL_227;
+	volatile u32 DENALI_CTL_228;
+	volatile u32 DENALI_CTL_229;
+	volatile u32 DENALI_CTL_230;
+	volatile u32 DENALI_CTL_231;
+	volatile u32 DENALI_CTL_232;
+	volatile u32 DENALI_CTL_233;
+	volatile u32 DENALI_CTL_234;
+	volatile u32 DENALI_CTL_235;
+	volatile u32 DENALI_CTL_236;
+	volatile u32 DENALI_CTL_237;
+	volatile u32 DENALI_CTL_238;
+	volatile u32 DENALI_CTL_239;
+	volatile u32 DENALI_CTL_240;
+	volatile u32 DENALI_CTL_241;
+	volatile u32 DENALI_CTL_242;
+	volatile u32 DENALI_CTL_243;
+	volatile u32 DENALI_CTL_244;
+	volatile u32 DENALI_CTL_245;
+	volatile u32 DENALI_CTL_246;
+	volatile u32 DENALI_CTL_247;
+	volatile u32 DENALI_CTL_248;
+	volatile u32 DENALI_CTL_249;
+	volatile u32 DENALI_CTL_250;
+	volatile u32 DENALI_CTL_251;
+	volatile u32 DENALI_CTL_252;
+	volatile u32 DENALI_CTL_253;
+	volatile u32 DENALI_CTL_254;
+	volatile u32 DENALI_CTL_255;
+	volatile u32 DENALI_CTL_256;
+	volatile u32 DENALI_CTL_257;
+	volatile u32 DENALI_CTL_258;
+	volatile u32 DENALI_CTL_259;
+	volatile u32 DENALI_CTL_260;
+	volatile u32 DENALI_CTL_261;
+	volatile u32 DENALI_CTL_262;
+	volatile u32 DENALI_CTL_263;
+	volatile u32 DENALI_CTL_264;
+	volatile u32 DENALI_CTL_265;
+	volatile u32 DENALI_CTL_266;
+	volatile u32 DENALI_CTL_267;
+	volatile u32 DENALI_CTL_268;
+	volatile u32 DENALI_CTL_269;
+	volatile u32 DENALI_CTL_270;
+	volatile u32 DENALI_CTL_271;
+	volatile u32 DENALI_CTL_272;
+	volatile u32 DENALI_CTL_273;
+	volatile u32 DENALI_CTL_274;
+	volatile u32 DENALI_CTL_275;
+	volatile u32 DENALI_CTL_276;
+	volatile u32 DENALI_CTL_277;
+	volatile u32 DENALI_CTL_278;
+	volatile u32 DENALI_CTL_279;
+	volatile u32 DENALI_CTL_280;
+	volatile u32 DENALI_CTL_281;
+	volatile u32 DENALI_CTL_282;
+	volatile u32 DENALI_CTL_283;
+	volatile u32 DENALI_CTL_284;
+	volatile u32 DENALI_CTL_285;
+	volatile u32 DENALI_CTL_286;
+	volatile u32 DENALI_CTL_287;
+	volatile u32 DENALI_CTL_288;
+	volatile u32 DENALI_CTL_289;
+	volatile u32 DENALI_CTL_290;
+	volatile u32 DENALI_CTL_291;
+	volatile u32 DENALI_CTL_292;
+	volatile u32 DENALI_CTL_293;
+	volatile u32 DENALI_CTL_294;
+	volatile u32 DENALI_CTL_295;
+	volatile u32 DENALI_CTL_296;
+	volatile u32 DENALI_CTL_297;
+	volatile u32 DENALI_CTL_298;
+	volatile u32 DENALI_CTL_299;
+	volatile u32 DENALI_CTL_300;
+	volatile u32 DENALI_CTL_301;
+	volatile u32 DENALI_CTL_302;
+	volatile u32 DENALI_CTL_303;
+	volatile u32 DENALI_CTL_304;
+	volatile u32 DENALI_CTL_305;
+	volatile u32 DENALI_CTL_306;
+	volatile u32 DENALI_CTL_307;
+	volatile u32 DENALI_CTL_308;
+	volatile u32 DENALI_CTL_309;
+	volatile u32 DENALI_CTL_310;
+	volatile u32 DENALI_CTL_311;
+	volatile u32 DENALI_CTL_312;
+	volatile u32 DENALI_CTL_313;
+	volatile u32 DENALI_CTL_314;
+	volatile u32 DENALI_CTL_315;
+	volatile u32 DENALI_CTL_316;
+	volatile u32 DENALI_CTL_317;
+	volatile u32 DENALI_CTL_318;
+	volatile u32 DENALI_CTL_319;
+	volatile u32 DENALI_CTL_320;
+	volatile u32 DENALI_CTL_321;
+	volatile u32 DENALI_CTL_322;
+	volatile u32 DENALI_CTL_323;
+	volatile u32 DENALI_CTL_324;
+	volatile u32 DENALI_CTL_325;
+	volatile u32 DENALI_CTL_326;
+	volatile u32 DENALI_CTL_327;
+	volatile u32 DENALI_CTL_328;
+	volatile u32 DENALI_CTL_329;
+	volatile u32 DENALI_CTL_330;
+	volatile u32 DENALI_CTL_331;
+	volatile u32 DENALI_CTL_332;
+	volatile u32 DENALI_CTL_333;
+	volatile u32 DENALI_CTL_334;
+	volatile u32 DENALI_CTL_335;
+	volatile u32 DENALI_CTL_336;
+	volatile u32 DENALI_CTL_337;
+	volatile u32 DENALI_CTL_338;
+	volatile u32 DENALI_CTL_339;
+	volatile u32 DENALI_CTL_340;
+	volatile u32 DENALI_CTL_341;
+	volatile u32 DENALI_CTL_342;
+	volatile u32 DENALI_CTL_343;
+	volatile u32 DENALI_CTL_344;
+	volatile u32 DENALI_CTL_345;
+	volatile u32 DENALI_CTL_346;
+	volatile u32 DENALI_CTL_347;
+	volatile u32 DENALI_CTL_348;
+	volatile u32 DENALI_CTL_349;
+	volatile u32 DENALI_CTL_350;
+	volatile u32 DENALI_CTL_351;
+	volatile u32 DENALI_CTL_352;
+	volatile u32 DENALI_CTL_353;
+	volatile u32 DENALI_CTL_354;
+	volatile u32 DENALI_CTL_355;
+	volatile u32 DENALI_CTL_356;
+	volatile u32 DENALI_CTL_357;
+	volatile u32 DENALI_CTL_358;
+	volatile u32 DENALI_CTL_359;
+	volatile u32 DENALI_CTL_360;
+	volatile u32 DENALI_CTL_361;
+	volatile u32 DENALI_CTL_362;
+	volatile u32 DENALI_CTL_363;
+	volatile u32 DENALI_CTL_364;
+	volatile u32 DENALI_CTL_365;
+	volatile u32 DENALI_CTL_366;
+	volatile u32 DENALI_CTL_367;
+	volatile u32 DENALI_CTL_368;
+	volatile u32 DENALI_CTL_369;
+	volatile u32 DENALI_CTL_370;
+	volatile u32 DENALI_CTL_371;
+	volatile u32 DENALI_CTL_372;
+	volatile u32 DENALI_CTL_373;
+	volatile u32 DENALI_CTL_374;
+	volatile u32 DENALI_CTL_375;
+	volatile u32 DENALI_CTL_376;
+	volatile u32 DENALI_CTL_377;
+	volatile u32 DENALI_CTL_378;
+	volatile u32 DENALI_CTL_379;
+	volatile u32 DENALI_CTL_380;
+	volatile u32 DENALI_CTL_381;
+	volatile u32 DENALI_CTL_382;
+	volatile u32 DENALI_CTL_383;
+	volatile u32 DENALI_CTL_384;
+	volatile u32 DENALI_CTL_385;
+	volatile u32 DENALI_CTL_386;
+	volatile u32 DENALI_CTL_387;
+	volatile u32 DENALI_CTL_388;
+	volatile u32 DENALI_CTL_389;
+	volatile u32 DENALI_CTL_390;
+	volatile u32 DENALI_CTL_391;
+	volatile u32 DENALI_CTL_392;
+	volatile u32 DENALI_CTL_393;
+	volatile u32 DENALI_CTL_394;
+	volatile u32 DENALI_CTL_395;
+	volatile u32 DENALI_CTL_396;
+	volatile u32 DENALI_CTL_397;
+	volatile u32 DENALI_CTL_398;
+	volatile u32 DENALI_CTL_399;
+	volatile u32 DENALI_CTL_400;
+	volatile u32 DENALI_CTL_401;
+	volatile u32 DENALI_CTL_402;
+	volatile u32 DENALI_CTL_403;
+	volatile u32 DENALI_CTL_404;
+	volatile u32 DENALI_CTL_405;
+	volatile u32 DENALI_CTL_406;
+	volatile u32 DENALI_CTL_407;
+	volatile u32 DENALI_CTL_408;
+	volatile u32 DENALI_CTL_409;
+	volatile u32 DENALI_CTL_410;
+	volatile u32 DENALI_CTL_411;
+	volatile u32 DENALI_CTL_412;
+	volatile u32 DENALI_CTL_413;
+	volatile u32 DENALI_CTL_414;
+	volatile u32 DENALI_CTL_415;
+	volatile u32 DENALI_CTL_416;
+	volatile u32 DENALI_CTL_417;
+	volatile u32 DENALI_CTL_418;
+	volatile u32 DENALI_CTL_419;
+	volatile u32 DENALI_CTL_420;
+	volatile u32 DENALI_CTL_421;
+	volatile u32 DENALI_CTL_422;
+	volatile char pad__0[0x1964U];
+	volatile u32 DENALI_PI_0;
+	volatile u32 DENALI_PI_1;
+	volatile u32 DENALI_PI_2;
+	volatile u32 DENALI_PI_3;
+	volatile u32 DENALI_PI_4;
+	volatile u32 DENALI_PI_5;
+	volatile u32 DENALI_PI_6;
+	volatile u32 DENALI_PI_7;
+	volatile u32 DENALI_PI_8;
+	volatile u32 DENALI_PI_9;
+	volatile u32 DENALI_PI_10;
+	volatile u32 DENALI_PI_11;
+	volatile u32 DENALI_PI_12;
+	volatile u32 DENALI_PI_13;
+	volatile u32 DENALI_PI_14;
+	volatile u32 DENALI_PI_15;
+	volatile u32 DENALI_PI_16;
+	volatile u32 DENALI_PI_17;
+	volatile u32 DENALI_PI_18;
+	volatile u32 DENALI_PI_19;
+	volatile u32 DENALI_PI_20;
+	volatile u32 DENALI_PI_21;
+	volatile u32 DENALI_PI_22;
+	volatile u32 DENALI_PI_23;
+	volatile u32 DENALI_PI_24;
+	volatile u32 DENALI_PI_25;
+	volatile u32 DENALI_PI_26;
+	volatile u32 DENALI_PI_27;
+	volatile u32 DENALI_PI_28;
+	volatile u32 DENALI_PI_29;
+	volatile u32 DENALI_PI_30;
+	volatile u32 DENALI_PI_31;
+	volatile u32 DENALI_PI_32;
+	volatile u32 DENALI_PI_33;
+	volatile u32 DENALI_PI_34;
+	volatile u32 DENALI_PI_35;
+	volatile u32 DENALI_PI_36;
+	volatile u32 DENALI_PI_37;
+	volatile u32 DENALI_PI_38;
+	volatile u32 DENALI_PI_39;
+	volatile u32 DENALI_PI_40;
+	volatile u32 DENALI_PI_41;
+	volatile u32 DENALI_PI_42;
+	volatile u32 DENALI_PI_43;
+	volatile u32 DENALI_PI_44;
+	volatile u32 DENALI_PI_45;
+	volatile u32 DENALI_PI_46;
+	volatile u32 DENALI_PI_47;
+	volatile u32 DENALI_PI_48;
+	volatile u32 DENALI_PI_49;
+	volatile u32 DENALI_PI_50;
+	volatile u32 DENALI_PI_51;
+	volatile u32 DENALI_PI_52;
+	volatile u32 DENALI_PI_53;
+	volatile u32 DENALI_PI_54;
+	volatile u32 DENALI_PI_55;
+	volatile u32 DENALI_PI_56;
+	volatile u32 DENALI_PI_57;
+	volatile u32 DENALI_PI_58;
+	volatile u32 DENALI_PI_59;
+	volatile u32 DENALI_PI_60;
+	volatile u32 DENALI_PI_61;
+	volatile u32 DENALI_PI_62;
+	volatile u32 DENALI_PI_63;
+	volatile u32 DENALI_PI_64;
+	volatile u32 DENALI_PI_65;
+	volatile u32 DENALI_PI_66;
+	volatile u32 DENALI_PI_67;
+	volatile u32 DENALI_PI_68;
+	volatile u32 DENALI_PI_69;
+	volatile u32 DENALI_PI_70;
+	volatile u32 DENALI_PI_71;
+	volatile u32 DENALI_PI_72;
+	volatile u32 DENALI_PI_73;
+	volatile u32 DENALI_PI_74;
+	volatile u32 DENALI_PI_75;
+	volatile u32 DENALI_PI_76;
+	volatile u32 DENALI_PI_77;
+	volatile u32 DENALI_PI_78;
+	volatile u32 DENALI_PI_79;
+	volatile u32 DENALI_PI_80;
+	volatile u32 DENALI_PI_81;
+	volatile u32 DENALI_PI_82;
+	volatile u32 DENALI_PI_83;
+	volatile u32 DENALI_PI_84;
+	volatile u32 DENALI_PI_85;
+	volatile u32 DENALI_PI_86;
+	volatile u32 DENALI_PI_87;
+	volatile u32 DENALI_PI_88;
+	volatile u32 DENALI_PI_89;
+	volatile u32 DENALI_PI_90;
+	volatile u32 DENALI_PI_91;
+	volatile u32 DENALI_PI_92;
+	volatile u32 DENALI_PI_93;
+	volatile u32 DENALI_PI_94;
+	volatile u32 DENALI_PI_95;
+	volatile u32 DENALI_PI_96;
+	volatile u32 DENALI_PI_97;
+	volatile u32 DENALI_PI_98;
+	volatile u32 DENALI_PI_99;
+	volatile u32 DENALI_PI_100;
+	volatile u32 DENALI_PI_101;
+	volatile u32 DENALI_PI_102;
+	volatile u32 DENALI_PI_103;
+	volatile u32 DENALI_PI_104;
+	volatile u32 DENALI_PI_105;
+	volatile u32 DENALI_PI_106;
+	volatile u32 DENALI_PI_107;
+	volatile u32 DENALI_PI_108;
+	volatile u32 DENALI_PI_109;
+	volatile u32 DENALI_PI_110;
+	volatile u32 DENALI_PI_111;
+	volatile u32 DENALI_PI_112;
+	volatile u32 DENALI_PI_113;
+	volatile u32 DENALI_PI_114;
+	volatile u32 DENALI_PI_115;
+	volatile u32 DENALI_PI_116;
+	volatile u32 DENALI_PI_117;
+	volatile u32 DENALI_PI_118;
+	volatile u32 DENALI_PI_119;
+	volatile u32 DENALI_PI_120;
+	volatile u32 DENALI_PI_121;
+	volatile u32 DENALI_PI_122;
+	volatile u32 DENALI_PI_123;
+	volatile u32 DENALI_PI_124;
+	volatile u32 DENALI_PI_125;
+	volatile u32 DENALI_PI_126;
+	volatile u32 DENALI_PI_127;
+	volatile u32 DENALI_PI_128;
+	volatile u32 DENALI_PI_129;
+	volatile u32 DENALI_PI_130;
+	volatile u32 DENALI_PI_131;
+	volatile u32 DENALI_PI_132;
+	volatile u32 DENALI_PI_133;
+	volatile u32 DENALI_PI_134;
+	volatile u32 DENALI_PI_135;
+	volatile u32 DENALI_PI_136;
+	volatile u32 DENALI_PI_137;
+	volatile u32 DENALI_PI_138;
+	volatile u32 DENALI_PI_139;
+	volatile u32 DENALI_PI_140;
+	volatile u32 DENALI_PI_141;
+	volatile u32 DENALI_PI_142;
+	volatile u32 DENALI_PI_143;
+	volatile u32 DENALI_PI_144;
+	volatile u32 DENALI_PI_145;
+	volatile u32 DENALI_PI_146;
+	volatile u32 DENALI_PI_147;
+	volatile u32 DENALI_PI_148;
+	volatile u32 DENALI_PI_149;
+	volatile u32 DENALI_PI_150;
+	volatile u32 DENALI_PI_151;
+	volatile u32 DENALI_PI_152;
+	volatile u32 DENALI_PI_153;
+	volatile u32 DENALI_PI_154;
+	volatile u32 DENALI_PI_155;
+	volatile u32 DENALI_PI_156;
+	volatile u32 DENALI_PI_157;
+	volatile u32 DENALI_PI_158;
+	volatile u32 DENALI_PI_159;
+	volatile u32 DENALI_PI_160;
+	volatile u32 DENALI_PI_161;
+	volatile u32 DENALI_PI_162;
+	volatile u32 DENALI_PI_163;
+	volatile u32 DENALI_PI_164;
+	volatile u32 DENALI_PI_165;
+	volatile u32 DENALI_PI_166;
+	volatile u32 DENALI_PI_167;
+	volatile u32 DENALI_PI_168;
+	volatile u32 DENALI_PI_169;
+	volatile u32 DENALI_PI_170;
+	volatile u32 DENALI_PI_171;
+	volatile u32 DENALI_PI_172;
+	volatile u32 DENALI_PI_173;
+	volatile u32 DENALI_PI_174;
+	volatile u32 DENALI_PI_175;
+	volatile u32 DENALI_PI_176;
+	volatile u32 DENALI_PI_177;
+	volatile u32 DENALI_PI_178;
+	volatile u32 DENALI_PI_179;
+	volatile u32 DENALI_PI_180;
+	volatile u32 DENALI_PI_181;
+	volatile u32 DENALI_PI_182;
+	volatile u32 DENALI_PI_183;
+	volatile u32 DENALI_PI_184;
+	volatile u32 DENALI_PI_185;
+	volatile u32 DENALI_PI_186;
+	volatile u32 DENALI_PI_187;
+	volatile u32 DENALI_PI_188;
+	volatile u32 DENALI_PI_189;
+	volatile u32 DENALI_PI_190;
+	volatile u32 DENALI_PI_191;
+	volatile u32 DENALI_PI_192;
+	volatile u32 DENALI_PI_193;
+	volatile u32 DENALI_PI_194;
+	volatile u32 DENALI_PI_195;
+	volatile u32 DENALI_PI_196;
+	volatile u32 DENALI_PI_197;
+	volatile u32 DENALI_PI_198;
+	volatile u32 DENALI_PI_199;
+	volatile u32 DENALI_PI_200;
+	volatile u32 DENALI_PI_201;
+	volatile u32 DENALI_PI_202;
+	volatile u32 DENALI_PI_203;
+	volatile u32 DENALI_PI_204;
+	volatile u32 DENALI_PI_205;
+	volatile u32 DENALI_PI_206;
+	volatile u32 DENALI_PI_207;
+	volatile u32 DENALI_PI_208;
+	volatile u32 DENALI_PI_209;
+	volatile u32 DENALI_PI_210;
+	volatile u32 DENALI_PI_211;
+	volatile u32 DENALI_PI_212;
+	volatile u32 DENALI_PI_213;
+	volatile u32 DENALI_PI_214;
+	volatile u32 DENALI_PI_215;
+	volatile u32 DENALI_PI_216;
+	volatile u32 DENALI_PI_217;
+	volatile u32 DENALI_PI_218;
+	volatile u32 DENALI_PI_219;
+	volatile u32 DENALI_PI_220;
+	volatile u32 DENALI_PI_221;
+	volatile u32 DENALI_PI_222;
+	volatile u32 DENALI_PI_223;
+	volatile u32 DENALI_PI_224;
+	volatile u32 DENALI_PI_225;
+	volatile u32 DENALI_PI_226;
+	volatile u32 DENALI_PI_227;
+	volatile u32 DENALI_PI_228;
+	volatile u32 DENALI_PI_229;
+	volatile u32 DENALI_PI_230;
+	volatile u32 DENALI_PI_231;
+	volatile u32 DENALI_PI_232;
+	volatile u32 DENALI_PI_233;
+	volatile u32 DENALI_PI_234;
+	volatile u32 DENALI_PI_235;
+	volatile u32 DENALI_PI_236;
+	volatile u32 DENALI_PI_237;
+	volatile u32 DENALI_PI_238;
+	volatile u32 DENALI_PI_239;
+	volatile u32 DENALI_PI_240;
+	volatile u32 DENALI_PI_241;
+	volatile u32 DENALI_PI_242;
+	volatile u32 DENALI_PI_243;
+	volatile u32 DENALI_PI_244;
+	volatile u32 DENALI_PI_245;
+	volatile u32 DENALI_PI_246;
+	volatile u32 DENALI_PI_247;
+	volatile u32 DENALI_PI_248;
+	volatile u32 DENALI_PI_249;
+	volatile u32 DENALI_PI_250;
+	volatile u32 DENALI_PI_251;
+	volatile u32 DENALI_PI_252;
+	volatile u32 DENALI_PI_253;
+	volatile u32 DENALI_PI_254;
+	volatile u32 DENALI_PI_255;
+	volatile u32 DENALI_PI_256;
+	volatile u32 DENALI_PI_257;
+	volatile u32 DENALI_PI_258;
+	volatile u32 DENALI_PI_259;
+	volatile u32 DENALI_PI_260;
+	volatile u32 DENALI_PI_261;
+	volatile u32 DENALI_PI_262;
+	volatile u32 DENALI_PI_263;
+	volatile u32 DENALI_PI_264;
+	volatile u32 DENALI_PI_265;
+	volatile u32 DENALI_PI_266;
+	volatile u32 DENALI_PI_267;
+	volatile u32 DENALI_PI_268;
+	volatile u32 DENALI_PI_269;
+	volatile u32 DENALI_PI_270;
+	volatile u32 DENALI_PI_271;
+	volatile u32 DENALI_PI_272;
+	volatile u32 DENALI_PI_273;
+	volatile u32 DENALI_PI_274;
+	volatile u32 DENALI_PI_275;
+	volatile u32 DENALI_PI_276;
+	volatile u32 DENALI_PI_277;
+	volatile u32 DENALI_PI_278;
+	volatile u32 DENALI_PI_279;
+	volatile u32 DENALI_PI_280;
+	volatile u32 DENALI_PI_281;
+	volatile u32 DENALI_PI_282;
+	volatile u32 DENALI_PI_283;
+	volatile u32 DENALI_PI_284;
+	volatile u32 DENALI_PI_285;
+	volatile u32 DENALI_PI_286;
+	volatile u32 DENALI_PI_287;
+	volatile u32 DENALI_PI_288;
+	volatile u32 DENALI_PI_289;
+	volatile u32 DENALI_PI_290;
+	volatile u32 DENALI_PI_291;
+	volatile u32 DENALI_PI_292;
+	volatile u32 DENALI_PI_293;
+	volatile u32 DENALI_PI_294;
+	volatile u32 DENALI_PI_295;
+	volatile u32 DENALI_PI_296;
+	volatile u32 DENALI_PI_297;
+	volatile u32 DENALI_PI_298;
+	volatile u32 DENALI_PI_299;
+	volatile u32 DENALI_PI_300;
+	volatile u32 DENALI_PI_301;
+	volatile u32 DENALI_PI_302;
+	volatile u32 DENALI_PI_303;
+	volatile u32 DENALI_PI_304;
+	volatile u32 DENALI_PI_305;
+	volatile u32 DENALI_PI_306;
+	volatile u32 DENALI_PI_307;
+	volatile u32 DENALI_PI_308;
+	volatile u32 DENALI_PI_309;
+	volatile u32 DENALI_PI_310;
+	volatile u32 DENALI_PI_311;
+	volatile u32 DENALI_PI_312;
+	volatile u32 DENALI_PI_313;
+	volatile u32 DENALI_PI_314;
+	volatile u32 DENALI_PI_315;
+	volatile u32 DENALI_PI_316;
+	volatile u32 DENALI_PI_317;
+	volatile u32 DENALI_PI_318;
+	volatile u32 DENALI_PI_319;
+	volatile u32 DENALI_PI_320;
+	volatile u32 DENALI_PI_321;
+	volatile u32 DENALI_PI_322;
+	volatile u32 DENALI_PI_323;
+	volatile u32 DENALI_PI_324;
+	volatile u32 DENALI_PI_325;
+	volatile u32 DENALI_PI_326;
+	volatile u32 DENALI_PI_327;
+	volatile u32 DENALI_PI_328;
+	volatile u32 DENALI_PI_329;
+	volatile u32 DENALI_PI_330;
+	volatile u32 DENALI_PI_331;
+	volatile u32 DENALI_PI_332;
+	volatile u32 DENALI_PI_333;
+	volatile u32 DENALI_PI_334;
+	volatile u32 DENALI_PI_335;
+	volatile u32 DENALI_PI_336;
+	volatile u32 DENALI_PI_337;
+	volatile u32 DENALI_PI_338;
+	volatile u32 DENALI_PI_339;
+	volatile u32 DENALI_PI_340;
+	volatile u32 DENALI_PI_341;
+	volatile u32 DENALI_PI_342;
+	volatile u32 DENALI_PI_343;
+	volatile u32 DENALI_PI_344;
+	volatile char pad__1[0x1A9CU];
+	volatile u32 DENALI_PHY_0;
+	volatile u32 DENALI_PHY_1;
+	volatile u32 DENALI_PHY_2;
+	volatile u32 DENALI_PHY_3;
+	volatile u32 DENALI_PHY_4;
+	volatile u32 DENALI_PHY_5;
+	volatile u32 DENALI_PHY_6;
+	volatile u32 DENALI_PHY_7;
+	volatile u32 DENALI_PHY_8;
+	volatile u32 DENALI_PHY_9;
+	volatile u32 DENALI_PHY_10;
+	volatile u32 DENALI_PHY_11;
+	volatile u32 DENALI_PHY_12;
+	volatile u32 DENALI_PHY_13;
+	volatile u32 DENALI_PHY_14;
+	volatile u32 DENALI_PHY_15;
+	volatile u32 DENALI_PHY_16;
+	volatile u32 DENALI_PHY_17;
+	volatile u32 DENALI_PHY_18;
+	volatile u32 DENALI_PHY_19;
+	volatile u32 DENALI_PHY_20;
+	volatile u32 DENALI_PHY_21;
+	volatile u32 DENALI_PHY_22;
+	volatile u32 DENALI_PHY_23;
+	volatile u32 DENALI_PHY_24;
+	volatile u32 DENALI_PHY_25;
+	volatile u32 DENALI_PHY_26;
+	volatile u32 DENALI_PHY_27;
+	volatile u32 DENALI_PHY_28;
+	volatile u32 DENALI_PHY_29;
+	volatile u32 DENALI_PHY_30;
+	volatile u32 DENALI_PHY_31;
+	volatile u32 DENALI_PHY_32;
+	volatile u32 DENALI_PHY_33;
+	volatile u32 DENALI_PHY_34;
+	volatile u32 DENALI_PHY_35;
+	volatile u32 DENALI_PHY_36;
+	volatile u32 DENALI_PHY_37;
+	volatile u32 DENALI_PHY_38;
+	volatile u32 DENALI_PHY_39;
+	volatile u32 DENALI_PHY_40;
+	volatile u32 DENALI_PHY_41;
+	volatile u32 DENALI_PHY_42;
+	volatile u32 DENALI_PHY_43;
+	volatile u32 DENALI_PHY_44;
+	volatile u32 DENALI_PHY_45;
+	volatile u32 DENALI_PHY_46;
+	volatile u32 DENALI_PHY_47;
+	volatile u32 DENALI_PHY_48;
+	volatile u32 DENALI_PHY_49;
+	volatile u32 DENALI_PHY_50;
+	volatile u32 DENALI_PHY_51;
+	volatile u32 DENALI_PHY_52;
+	volatile u32 DENALI_PHY_53;
+	volatile u32 DENALI_PHY_54;
+	volatile u32 DENALI_PHY_55;
+	volatile u32 DENALI_PHY_56;
+	volatile u32 DENALI_PHY_57;
+	volatile u32 DENALI_PHY_58;
+	volatile u32 DENALI_PHY_59;
+	volatile u32 DENALI_PHY_60;
+	volatile u32 DENALI_PHY_61;
+	volatile u32 DENALI_PHY_62;
+	volatile u32 DENALI_PHY_63;
+	volatile u32 DENALI_PHY_64;
+	volatile u32 DENALI_PHY_65;
+	volatile u32 DENALI_PHY_66;
+	volatile u32 DENALI_PHY_67;
+	volatile u32 DENALI_PHY_68;
+	volatile u32 DENALI_PHY_69;
+	volatile u32 DENALI_PHY_70;
+	volatile u32 DENALI_PHY_71;
+	volatile u32 DENALI_PHY_72;
+	volatile u32 DENALI_PHY_73;
+	volatile u32 DENALI_PHY_74;
+	volatile u32 DENALI_PHY_75;
+	volatile u32 DENALI_PHY_76;
+	volatile u32 DENALI_PHY_77;
+	volatile u32 DENALI_PHY_78;
+	volatile u32 DENALI_PHY_79;
+	volatile u32 DENALI_PHY_80;
+	volatile u32 DENALI_PHY_81;
+	volatile u32 DENALI_PHY_82;
+	volatile u32 DENALI_PHY_83;
+	volatile u32 DENALI_PHY_84;
+	volatile u32 DENALI_PHY_85;
+	volatile u32 DENALI_PHY_86;
+	volatile u32 DENALI_PHY_87;
+	volatile u32 DENALI_PHY_88;
+	volatile u32 DENALI_PHY_89;
+	volatile u32 DENALI_PHY_90;
+	volatile u32 DENALI_PHY_91;
+	volatile u32 DENALI_PHY_92;
+	volatile u32 DENALI_PHY_93;
+	volatile u32 DENALI_PHY_94;
+	volatile u32 DENALI_PHY_95;
+	volatile u32 DENALI_PHY_96;
+	volatile u32 DENALI_PHY_97;
+	volatile u32 DENALI_PHY_98;
+	volatile u32 DENALI_PHY_99;
+	volatile u32 DENALI_PHY_100;
+	volatile u32 DENALI_PHY_101;
+	volatile u32 DENALI_PHY_102;
+	volatile u32 DENALI_PHY_103;
+	volatile u32 DENALI_PHY_104;
+	volatile u32 DENALI_PHY_105;
+	volatile u32 DENALI_PHY_106;
+	volatile u32 DENALI_PHY_107;
+	volatile u32 DENALI_PHY_108;
+	volatile u32 DENALI_PHY_109;
+	volatile u32 DENALI_PHY_110;
+	volatile u32 DENALI_PHY_111;
+	volatile u32 DENALI_PHY_112;
+	volatile u32 DENALI_PHY_113;
+	volatile u32 DENALI_PHY_114;
+	volatile u32 DENALI_PHY_115;
+	volatile u32 DENALI_PHY_116;
+	volatile u32 DENALI_PHY_117;
+	volatile u32 DENALI_PHY_118;
+	volatile u32 DENALI_PHY_119;
+	volatile u32 DENALI_PHY_120;
+	volatile u32 DENALI_PHY_121;
+	volatile u32 DENALI_PHY_122;
+	volatile u32 DENALI_PHY_123;
+	volatile u32 DENALI_PHY_124;
+	volatile u32 DENALI_PHY_125;
+	volatile char pad__2[0x208U];
+	volatile u32 DENALI_PHY_256;
+	volatile u32 DENALI_PHY_257;
+	volatile u32 DENALI_PHY_258;
+	volatile u32 DENALI_PHY_259;
+	volatile u32 DENALI_PHY_260;
+	volatile u32 DENALI_PHY_261;
+	volatile u32 DENALI_PHY_262;
+	volatile u32 DENALI_PHY_263;
+	volatile u32 DENALI_PHY_264;
+	volatile u32 DENALI_PHY_265;
+	volatile u32 DENALI_PHY_266;
+	volatile u32 DENALI_PHY_267;
+	volatile u32 DENALI_PHY_268;
+	volatile u32 DENALI_PHY_269;
+	volatile u32 DENALI_PHY_270;
+	volatile u32 DENALI_PHY_271;
+	volatile u32 DENALI_PHY_272;
+	volatile u32 DENALI_PHY_273;
+	volatile u32 DENALI_PHY_274;
+	volatile u32 DENALI_PHY_275;
+	volatile u32 DENALI_PHY_276;
+	volatile u32 DENALI_PHY_277;
+	volatile u32 DENALI_PHY_278;
+	volatile u32 DENALI_PHY_279;
+	volatile u32 DENALI_PHY_280;
+	volatile u32 DENALI_PHY_281;
+	volatile u32 DENALI_PHY_282;
+	volatile u32 DENALI_PHY_283;
+	volatile u32 DENALI_PHY_284;
+	volatile u32 DENALI_PHY_285;
+	volatile u32 DENALI_PHY_286;
+	volatile u32 DENALI_PHY_287;
+	volatile u32 DENALI_PHY_288;
+	volatile u32 DENALI_PHY_289;
+	volatile u32 DENALI_PHY_290;
+	volatile u32 DENALI_PHY_291;
+	volatile u32 DENALI_PHY_292;
+	volatile u32 DENALI_PHY_293;
+	volatile u32 DENALI_PHY_294;
+	volatile u32 DENALI_PHY_295;
+	volatile u32 DENALI_PHY_296;
+	volatile u32 DENALI_PHY_297;
+	volatile u32 DENALI_PHY_298;
+	volatile u32 DENALI_PHY_299;
+	volatile u32 DENALI_PHY_300;
+	volatile u32 DENALI_PHY_301;
+	volatile u32 DENALI_PHY_302;
+	volatile u32 DENALI_PHY_303;
+	volatile u32 DENALI_PHY_304;
+	volatile u32 DENALI_PHY_305;
+	volatile u32 DENALI_PHY_306;
+	volatile u32 DENALI_PHY_307;
+	volatile u32 DENALI_PHY_308;
+	volatile u32 DENALI_PHY_309;
+	volatile u32 DENALI_PHY_310;
+	volatile u32 DENALI_PHY_311;
+	volatile u32 DENALI_PHY_312;
+	volatile u32 DENALI_PHY_313;
+	volatile u32 DENALI_PHY_314;
+	volatile u32 DENALI_PHY_315;
+	volatile u32 DENALI_PHY_316;
+	volatile u32 DENALI_PHY_317;
+	volatile u32 DENALI_PHY_318;
+	volatile u32 DENALI_PHY_319;
+	volatile u32 DENALI_PHY_320;
+	volatile u32 DENALI_PHY_321;
+	volatile u32 DENALI_PHY_322;
+	volatile u32 DENALI_PHY_323;
+	volatile u32 DENALI_PHY_324;
+	volatile u32 DENALI_PHY_325;
+	volatile u32 DENALI_PHY_326;
+	volatile u32 DENALI_PHY_327;
+	volatile u32 DENALI_PHY_328;
+	volatile u32 DENALI_PHY_329;
+	volatile u32 DENALI_PHY_330;
+	volatile u32 DENALI_PHY_331;
+	volatile u32 DENALI_PHY_332;
+	volatile u32 DENALI_PHY_333;
+	volatile u32 DENALI_PHY_334;
+	volatile u32 DENALI_PHY_335;
+	volatile u32 DENALI_PHY_336;
+	volatile u32 DENALI_PHY_337;
+	volatile u32 DENALI_PHY_338;
+	volatile u32 DENALI_PHY_339;
+	volatile u32 DENALI_PHY_340;
+	volatile u32 DENALI_PHY_341;
+	volatile u32 DENALI_PHY_342;
+	volatile u32 DENALI_PHY_343;
+	volatile u32 DENALI_PHY_344;
+	volatile u32 DENALI_PHY_345;
+	volatile u32 DENALI_PHY_346;
+	volatile u32 DENALI_PHY_347;
+	volatile u32 DENALI_PHY_348;
+	volatile u32 DENALI_PHY_349;
+	volatile u32 DENALI_PHY_350;
+	volatile u32 DENALI_PHY_351;
+	volatile u32 DENALI_PHY_352;
+	volatile u32 DENALI_PHY_353;
+	volatile u32 DENALI_PHY_354;
+	volatile u32 DENALI_PHY_355;
+	volatile u32 DENALI_PHY_356;
+	volatile u32 DENALI_PHY_357;
+	volatile u32 DENALI_PHY_358;
+	volatile u32 DENALI_PHY_359;
+	volatile u32 DENALI_PHY_360;
+	volatile u32 DENALI_PHY_361;
+	volatile u32 DENALI_PHY_362;
+	volatile u32 DENALI_PHY_363;
+	volatile u32 DENALI_PHY_364;
+	volatile u32 DENALI_PHY_365;
+	volatile u32 DENALI_PHY_366;
+	volatile u32 DENALI_PHY_367;
+	volatile u32 DENALI_PHY_368;
+	volatile u32 DENALI_PHY_369;
+	volatile u32 DENALI_PHY_370;
+	volatile u32 DENALI_PHY_371;
+	volatile u32 DENALI_PHY_372;
+	volatile u32 DENALI_PHY_373;
+	volatile u32 DENALI_PHY_374;
+	volatile u32 DENALI_PHY_375;
+	volatile u32 DENALI_PHY_376;
+	volatile u32 DENALI_PHY_377;
+	volatile u32 DENALI_PHY_378;
+	volatile u32 DENALI_PHY_379;
+	volatile u32 DENALI_PHY_380;
+	volatile u32 DENALI_PHY_381;
+	volatile char pad__3[0x208U];
+	volatile u32 DENALI_PHY_512;
+	volatile u32 DENALI_PHY_513;
+	volatile u32 DENALI_PHY_514;
+	volatile u32 DENALI_PHY_515;
+	volatile u32 DENALI_PHY_516;
+	volatile u32 DENALI_PHY_517;
+	volatile u32 DENALI_PHY_518;
+	volatile u32 DENALI_PHY_519;
+	volatile u32 DENALI_PHY_520;
+	volatile u32 DENALI_PHY_521;
+	volatile u32 DENALI_PHY_522;
+	volatile u32 DENALI_PHY_523;
+	volatile u32 DENALI_PHY_524;
+	volatile u32 DENALI_PHY_525;
+	volatile u32 DENALI_PHY_526;
+	volatile u32 DENALI_PHY_527;
+	volatile u32 DENALI_PHY_528;
+	volatile u32 DENALI_PHY_529;
+	volatile u32 DENALI_PHY_530;
+	volatile u32 DENALI_PHY_531;
+	volatile u32 DENALI_PHY_532;
+	volatile u32 DENALI_PHY_533;
+	volatile u32 DENALI_PHY_534;
+	volatile u32 DENALI_PHY_535;
+	volatile u32 DENALI_PHY_536;
+	volatile u32 DENALI_PHY_537;
+	volatile u32 DENALI_PHY_538;
+	volatile u32 DENALI_PHY_539;
+	volatile u32 DENALI_PHY_540;
+	volatile u32 DENALI_PHY_541;
+	volatile u32 DENALI_PHY_542;
+	volatile u32 DENALI_PHY_543;
+	volatile u32 DENALI_PHY_544;
+	volatile u32 DENALI_PHY_545;
+	volatile u32 DENALI_PHY_546;
+	volatile u32 DENALI_PHY_547;
+	volatile u32 DENALI_PHY_548;
+	volatile u32 DENALI_PHY_549;
+	volatile u32 DENALI_PHY_550;
+	volatile u32 DENALI_PHY_551;
+	volatile u32 DENALI_PHY_552;
+	volatile u32 DENALI_PHY_553;
+	volatile u32 DENALI_PHY_554;
+	volatile char pad__4[0x354U];
+	volatile u32 DENALI_PHY_768;
+	volatile u32 DENALI_PHY_769;
+	volatile u32 DENALI_PHY_770;
+	volatile u32 DENALI_PHY_771;
+	volatile u32 DENALI_PHY_772;
+	volatile u32 DENALI_PHY_773;
+	volatile u32 DENALI_PHY_774;
+	volatile u32 DENALI_PHY_775;
+	volatile u32 DENALI_PHY_776;
+	volatile u32 DENALI_PHY_777;
+	volatile u32 DENALI_PHY_778;
+	volatile u32 DENALI_PHY_779;
+	volatile u32 DENALI_PHY_780;
+	volatile u32 DENALI_PHY_781;
+	volatile u32 DENALI_PHY_782;
+	volatile u32 DENALI_PHY_783;
+	volatile u32 DENALI_PHY_784;
+	volatile u32 DENALI_PHY_785;
+	volatile u32 DENALI_PHY_786;
+	volatile u32 DENALI_PHY_787;
+	volatile u32 DENALI_PHY_788;
+	volatile u32 DENALI_PHY_789;
+	volatile u32 DENALI_PHY_790;
+	volatile u32 DENALI_PHY_791;
+	volatile u32 DENALI_PHY_792;
+	volatile u32 DENALI_PHY_793;
+	volatile u32 DENALI_PHY_794;
+	volatile u32 DENALI_PHY_795;
+	volatile u32 DENALI_PHY_796;
+	volatile u32 DENALI_PHY_797;
+	volatile u32 DENALI_PHY_798;
+	volatile u32 DENALI_PHY_799;
+	volatile u32 DENALI_PHY_800;
+	volatile u32 DENALI_PHY_801;
+	volatile u32 DENALI_PHY_802;
+	volatile u32 DENALI_PHY_803;
+	volatile u32 DENALI_PHY_804;
+	volatile u32 DENALI_PHY_805;
+	volatile u32 DENALI_PHY_806;
+	volatile u32 DENALI_PHY_807;
+	volatile u32 DENALI_PHY_808;
+	volatile u32 DENALI_PHY_809;
+	volatile u32 DENALI_PHY_810;
+	volatile char pad__5[0x354U];
+	volatile u32 DENALI_PHY_1024;
+	volatile u32 DENALI_PHY_1025;
+	volatile u32 DENALI_PHY_1026;
+	volatile u32 DENALI_PHY_1027;
+	volatile u32 DENALI_PHY_1028;
+	volatile u32 DENALI_PHY_1029;
+	volatile u32 DENALI_PHY_1030;
+	volatile u32 DENALI_PHY_1031;
+	volatile u32 DENALI_PHY_1032;
+	volatile u32 DENALI_PHY_1033;
+	volatile u32 DENALI_PHY_1034;
+	volatile u32 DENALI_PHY_1035;
+	volatile u32 DENALI_PHY_1036;
+	volatile u32 DENALI_PHY_1037;
+	volatile u32 DENALI_PHY_1038;
+	volatile u32 DENALI_PHY_1039;
+	volatile u32 DENALI_PHY_1040;
+	volatile u32 DENALI_PHY_1041;
+	volatile u32 DENALI_PHY_1042;
+	volatile u32 DENALI_PHY_1043;
+	volatile u32 DENALI_PHY_1044;
+	volatile u32 DENALI_PHY_1045;
+	volatile u32 DENALI_PHY_1046;
+	volatile u32 DENALI_PHY_1047;
+	volatile u32 DENALI_PHY_1048;
+	volatile u32 DENALI_PHY_1049;
+	volatile u32 DENALI_PHY_1050;
+	volatile u32 DENALI_PHY_1051;
+	volatile u32 DENALI_PHY_1052;
+	volatile u32 DENALI_PHY_1053;
+	volatile u32 DENALI_PHY_1054;
+	volatile u32 DENALI_PHY_1055;
+	volatile u32 DENALI_PHY_1056;
+	volatile u32 DENALI_PHY_1057;
+	volatile u32 DENALI_PHY_1058;
+	volatile u32 DENALI_PHY_1059;
+	volatile u32 DENALI_PHY_1060;
+	volatile u32 DENALI_PHY_1061;
+	volatile u32 DENALI_PHY_1062;
+	volatile u32 DENALI_PHY_1063;
+	volatile u32 DENALI_PHY_1064;
+	volatile u32 DENALI_PHY_1065;
+	volatile u32 DENALI_PHY_1066;
+	volatile char pad__6[0x354U];
+	volatile u32 DENALI_PHY_1280;
+	volatile u32 DENALI_PHY_1281;
+	volatile u32 DENALI_PHY_1282;
+	volatile u32 DENALI_PHY_1283;
+	volatile u32 DENALI_PHY_1284;
+	volatile u32 DENALI_PHY_1285;
+	volatile u32 DENALI_PHY_1286;
+	volatile u32 DENALI_PHY_1287;
+	volatile u32 DENALI_PHY_1288;
+	volatile u32 DENALI_PHY_1289;
+	volatile u32 DENALI_PHY_1290;
+	volatile u32 DENALI_PHY_1291;
+	volatile u32 DENALI_PHY_1292;
+	volatile u32 DENALI_PHY_1293;
+	volatile u32 DENALI_PHY_1294;
+	volatile u32 DENALI_PHY_1295;
+	volatile u32 DENALI_PHY_1296;
+	volatile u32 DENALI_PHY_1297;
+	volatile u32 DENALI_PHY_1298;
+	volatile u32 DENALI_PHY_1299;
+	volatile u32 DENALI_PHY_1300;
+	volatile u32 DENALI_PHY_1301;
+	volatile u32 DENALI_PHY_1302;
+	volatile u32 DENALI_PHY_1303;
+	volatile u32 DENALI_PHY_1304;
+	volatile u32 DENALI_PHY_1305;
+	volatile u32 DENALI_PHY_1306;
+	volatile u32 DENALI_PHY_1307;
+	volatile u32 DENALI_PHY_1308;
+	volatile u32 DENALI_PHY_1309;
+	volatile u32 DENALI_PHY_1310;
+	volatile u32 DENALI_PHY_1311;
+	volatile u32 DENALI_PHY_1312;
+	volatile u32 DENALI_PHY_1313;
+	volatile u32 DENALI_PHY_1314;
+	volatile u32 DENALI_PHY_1315;
+	volatile u32 DENALI_PHY_1316;
+	volatile u32 DENALI_PHY_1317;
+	volatile u32 DENALI_PHY_1318;
+	volatile u32 DENALI_PHY_1319;
+	volatile u32 DENALI_PHY_1320;
+	volatile u32 DENALI_PHY_1321;
+	volatile u32 DENALI_PHY_1322;
+	volatile u32 DENALI_PHY_1323;
+	volatile u32 DENALI_PHY_1324;
+	volatile u32 DENALI_PHY_1325;
+	volatile u32 DENALI_PHY_1326;
+	volatile u32 DENALI_PHY_1327;
+	volatile u32 DENALI_PHY_1328;
+	volatile u32 DENALI_PHY_1329;
+	volatile u32 DENALI_PHY_1330;
+	volatile u32 DENALI_PHY_1331;
+	volatile u32 DENALI_PHY_1332;
+	volatile u32 DENALI_PHY_1333;
+	volatile u32 DENALI_PHY_1334;
+	volatile u32 DENALI_PHY_1335;
+	volatile u32 DENALI_PHY_1336;
+	volatile u32 DENALI_PHY_1337;
+	volatile u32 DENALI_PHY_1338;
+	volatile u32 DENALI_PHY_1339;
+	volatile u32 DENALI_PHY_1340;
+	volatile u32 DENALI_PHY_1341;
+	volatile u32 DENALI_PHY_1342;
+	volatile u32 DENALI_PHY_1343;
+	volatile u32 DENALI_PHY_1344;
+	volatile u32 DENALI_PHY_1345;
+	volatile u32 DENALI_PHY_1346;
+	volatile u32 DENALI_PHY_1347;
+	volatile u32 DENALI_PHY_1348;
+	volatile u32 DENALI_PHY_1349;
+	volatile u32 DENALI_PHY_1350;
+	volatile u32 DENALI_PHY_1351;
+	volatile u32 DENALI_PHY_1352;
+	volatile u32 DENALI_PHY_1353;
+	volatile u32 DENALI_PHY_1354;
+	volatile u32 DENALI_PHY_1355;
+	volatile u32 DENALI_PHY_1356;
+	volatile u32 DENALI_PHY_1357;
+	volatile u32 DENALI_PHY_1358;
+	volatile u32 DENALI_PHY_1359;
+	volatile u32 DENALI_PHY_1360;
+	volatile u32 DENALI_PHY_1361;
+	volatile u32 DENALI_PHY_1362;
+	volatile u32 DENALI_PHY_1363;
+	volatile u32 DENALI_PHY_1364;
+	volatile u32 DENALI_PHY_1365;
+	volatile u32 DENALI_PHY_1366;
+	volatile u32 DENALI_PHY_1367;
+	volatile u32 DENALI_PHY_1368;
+	volatile u32 DENALI_PHY_1369;
+	volatile u32 DENALI_PHY_1370;
+	volatile u32 DENALI_PHY_1371;
+	volatile u32 DENALI_PHY_1372;
+	volatile u32 DENALI_PHY_1373;
+	volatile u32 DENALI_PHY_1374;
+	volatile u32 DENALI_PHY_1375;
+	volatile u32 DENALI_PHY_1376;
+	volatile u32 DENALI_PHY_1377;
+	volatile u32 DENALI_PHY_1378;
+	volatile u32 DENALI_PHY_1379;
+	volatile u32 DENALI_PHY_1380;
+	volatile u32 DENALI_PHY_1381;
+	volatile u32 DENALI_PHY_1382;
+	volatile u32 DENALI_PHY_1383;
+	volatile u32 DENALI_PHY_1384;
+	volatile u32 DENALI_PHY_1385;
+	volatile u32 DENALI_PHY_1386;
+	volatile u32 DENALI_PHY_1387;
+	volatile u32 DENALI_PHY_1388;
+	volatile u32 DENALI_PHY_1389;
+	volatile u32 DENALI_PHY_1390;
+	volatile u32 DENALI_PHY_1391;
+	volatile u32 DENALI_PHY_1392;
+	volatile u32 DENALI_PHY_1393;
+	volatile u32 DENALI_PHY_1394;
+	volatile u32 DENALI_PHY_1395;
+	volatile u32 DENALI_PHY_1396;
+	volatile u32 DENALI_PHY_1397;
+	volatile u32 DENALI_PHY_1398;
+	volatile u32 DENALI_PHY_1399;
+	volatile u32 DENALI_PHY_1400;
+	volatile u32 DENALI_PHY_1401;
+	volatile u32 DENALI_PHY_1402;
+	volatile u32 DENALI_PHY_1403;
+	volatile u32 DENALI_PHY_1404;
+	volatile u32 DENALI_PHY_1405;
+} lpddr4_ctlregs;
+
+#endif /* REG_LPDDR4_CTL_REGS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
new file mode 100644
index 000000000000..c17e7f776421
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ctl_regs_rw_masks.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef LPDDR4_RW_MASKS_H_
+#define LPDDR4_RW_MASKS_H_
+
+#include "cdn_stdint.h"
+
+extern u32 g_lpddr4_ddr_controller_rw_mask[423];
+extern u32 g_lpddr4_pi_rw_mask[345];
+extern u32 g_lpddr4_data_slice_0_rw_mask[126];
+extern u32 g_lpddr4_data_slice_1_rw_mask[126];
+extern u32 g_lpddr4_address_slice_0_rw_mask[43];
+extern u32 g_lpddr4_address_slice_1_rw_mask[43];
+extern u32 g_lpddr4_address_slice_2_rw_mask[43];
+extern u32 g_lpddr4_phy_core_rw_mask[126];
+
+#endif /* LPDDR4_RW_MASKS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
new file mode 100644
index 000000000000..d3bf24e677bf
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_0_macros.h
@@ -0,0 +1,2036 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_0_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_0_READ_MASK                               0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0_WRITE_MASK                              0x07FF7F07U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_MASK    0x00000007U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0_WIDTH            3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_MASK  0x00007F00U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0_WIDTH          7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_0__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_MASK   0x07FF0000U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0_WIDTH          11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_0
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_0__PHY_CLK_WR_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1_READ_MASK                               0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1_WRITE_MASK                              0x0703FF0FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_MASK  0x0000000FU
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0_WIDTH          4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_IO_PAD_DELAY_TIMING_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0_WIDTH       10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_MASK   0x07000000U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0_WIDTH           3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__REG DENALI_PHY_1
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_0__FLD LPDDR4__DENALI_PHY_1__PHY_WRITE_PATH_LAT_ADD_BYPASS_0
+
+#define LPDDR4__DENALI_PHY_2_READ_MASK                               0x010303FFU
+#define LPDDR4__DENALI_PHY_2_WRITE_MASK                              0x010303FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_SHIFT       0U
+#define LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_2__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_MASK     0x00030000U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0_WIDTH             2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_2__PHY_BYPASS_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_MASK         0x01000000U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0_WOSET                 0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__REG DENALI_PHY_2
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_0__FLD LPDDR4__DENALI_PHY_2__PHY_CLK_BYPASS_OVERRIDE_0
+
+#define LPDDR4__DENALI_PHY_3_READ_MASK                               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3_WRITE_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_MASK              0x00003F00U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__REG DENALI_PHY_3
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_0__FLD LPDDR4__DENALI_PHY_3__PHY_SW_WRDQ3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4_READ_MASK                               0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4_WRITE_MASK                              0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_MASK              0x0000003FU
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ4_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_MASK              0x00003F00U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ5_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_MASK              0x003F0000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ6_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_MASK              0x3F000000U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0_WIDTH                      6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__REG DENALI_PHY_4
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_0__FLD LPDDR4__DENALI_PHY_4__PHY_SW_WRDQ7_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5_READ_MASK                               0x1F030F3FU
+#define LPDDR4__DENALI_PHY_5_WRITE_MASK                              0x1F030F3FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_MASK               0x0000003FU
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0_WIDTH                       6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDM_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDM_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_MASK              0x00000F00U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0_WIDTH                      4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_0__FLD LPDDR4__DENALI_PHY_5__PHY_SW_WRDQS_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0_WIDTH           2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_MASK      0x1F000000U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0_WIDTH              5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__REG DENALI_PHY_5
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_5__PHY_LP4_BOOT_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_6_READ_MASK                               0x030F0F1FU
+#define LPDDR4__DENALI_PHY_6_WRITE_MASK                              0x030F0F1FU
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0_WIDTH                4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_SHIFT      16U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0_WIDTH       4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_SHIFT       24U
+#define LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0_WIDTH        2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_6
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_6__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_7_READ_MASK                               0x01FF031FU
+#define LPDDR4__DENALI_PHY_7_WRITE_MASK                              0x01FF031FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_MASK   0x0000001FU
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0_WIDTH           5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_7__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_MASK                0x00000300U
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0_WIDTH                        2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_CTRL_LPBK_EN_0__FLD LPDDR4__DENALI_PHY_7__PHY_CTRL_LPBK_EN_0
+
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0_WIDTH                        9U
+#define LPDDR4__PHY_LPBK_CONTROL_0__REG DENALI_PHY_7
+#define LPDDR4__PHY_LPBK_CONTROL_0__FLD LPDDR4__DENALI_PHY_7__PHY_LPBK_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_8_READ_MASK                               0x00000101U
+#define LPDDR4__DENALI_PHY_8_WRITE_MASK                              0x00000101U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0_WOSET                 0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_0__FLD LPDDR4__DENALI_PHY_8__PHY_LPBK_DFX_TIMEOUT_EN_0
+
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_SHIFT             8U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WIDTH             1U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WOCLR             0U
+#define LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0_WOSET             0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__REG DENALI_PHY_8
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_0__FLD LPDDR4__DENALI_PHY_8__PHY_GATE_DELAY_COMP_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_9_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_MASK  0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0_WIDTH         32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__REG DENALI_PHY_9
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_0__FLD LPDDR4__DENALI_PHY_9__PHY_AUTO_TIMING_MARGIN_CONTROL_0
+
+#define LPDDR4__DENALI_PHY_10_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_MASK     0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0_WIDTH            28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__REG DENALI_PHY_10
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_0__FLD LPDDR4__DENALI_PHY_10__PHY_AUTO_TIMING_MARGIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_11_READ_MASK                              0x7F0101FFU
+#define LPDDR4__DENALI_PHY_11_WRITE_MASK                             0x7F0101FFU
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_MASK                    0x000001FFU
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_SHIFT                            0U
+#define LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0_WIDTH                            9U
+#define LPDDR4__PHY_DQ_IDLE_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_DQ_IDLE_0__FLD LPDDR4__DENALI_PHY_11__PHY_DQ_IDLE_0
+
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_MASK                0x00010000U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0_WOSET                        0U
+#define LPDDR4__PHY_PDA_MODE_EN_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_PDA_MODE_EN_0__FLD LPDDR4__DENALI_PHY_11__PHY_PDA_MODE_EN_0
+
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_MASK         0x7F000000U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0_WIDTH                 7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__REG DENALI_PHY_11
+#define LPDDR4__PHY_PRBS_PATTERN_START_0__FLD LPDDR4__DENALI_PHY_11__PHY_PRBS_PATTERN_START_0
+
+#define LPDDR4__DENALI_PHY_12_READ_MASK                              0x010101FFU
+#define LPDDR4__DENALI_PHY_12_WRITE_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_MASK          0x000001FFU
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0_WIDTH                  9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_0__FLD LPDDR4__DENALI_PHY_12__PHY_PRBS_PATTERN_MASK_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0_WOSET            0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_SHIFT      24U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WIDTH       1U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOCLR       0U
+#define LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0_WOSET       0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__REG DENALI_PHY_12
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_12__PHY_RDLVL_MULTI_PATT_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_13_READ_MASK                              0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_13_WRITE_MASK                             0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_MASK      0x0000003FU
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0_WIDTH              6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_0__FLD LPDDR4__DENALI_PHY_13__PHY_VREF_INITIAL_STEPSIZE_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_MASK             0x00007F00U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0_WIDTH                     7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_VREF_TRAIN_OBS_0__FLD LPDDR4__DENALI_PHY_13__PHY_VREF_TRAIN_OBS_0
+
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__REG DENALI_PHY_13
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_13__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_14_READ_MASK                              0x01FF000FU
+#define LPDDR4__DENALI_PHY_14_WRITE_MASK                             0x01FF000FU
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0_WIDTH            4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_ERROR_DELAY_SELECT_0
+
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_MASK           0x00000100U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0_WOSET                   0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG DENALI_PHY_14
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD LPDDR4__DENALI_PHY_14__SC_PHY_SNAP_OBS_REGS_0
+
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_MASK     0x01FF0000U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0_WIDTH             9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__REG DENALI_PHY_14
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_14__PHY_GATE_SMPL1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_15_READ_MASK                              0x01FF0701U
+#define LPDDR4__DENALI_PHY_15_WRITE_MASK                             0x01FF0701U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_MASK                      0x00000001U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_SHIFT                              0U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WIDTH                              1U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WOCLR                              0U
+#define LPDDR4__DENALI_PHY_15__PHY_LPDDR_0_WOSET                              0U
+#define LPDDR4__PHY_LPDDR_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_LPDDR_0__FLD LPDDR4__DENALI_PHY_15__PHY_LPDDR_0
+
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_MASK                  0x00000700U
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0_WIDTH                          3U
+#define LPDDR4__PHY_MEM_CLASS_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_MEM_CLASS_0__FLD LPDDR4__DENALI_PHY_15__PHY_MEM_CLASS_0
+
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_MASK     0x01FF0000U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0_WIDTH             9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__REG DENALI_PHY_15
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_15__PHY_GATE_SMPL2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_16_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_16_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_MASK          0x00000003U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0_WIDTH                  2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__REG DENALI_PHY_16
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_0__FLD LPDDR4__DENALI_PHY_16__ON_FLY_GATE_ADJUST_EN_0
+
+#define LPDDR4__DENALI_PHY_17_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__REG DENALI_PHY_17
+#define LPDDR4__PHY_GATE_TRACKING_OBS_0__FLD LPDDR4__DENALI_PHY_17__PHY_GATE_TRACKING_OBS_0
+
+#define LPDDR4__DENALI_PHY_18_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_18_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_MASK              0x00000003U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0_WIDTH                      2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__REG DENALI_PHY_18
+#define LPDDR4__PHY_LP4_PST_AMBLE_0__FLD LPDDR4__DENALI_PHY_18__PHY_LP4_PST_AMBLE_0
+
+#define LPDDR4__DENALI_PHY_19_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0_WIDTH                       32U
+#define LPDDR4__PHY_RDLVL_PATT8_0__REG DENALI_PHY_19
+#define LPDDR4__PHY_RDLVL_PATT8_0__FLD LPDDR4__DENALI_PHY_19__PHY_RDLVL_PATT8_0
+
+#define LPDDR4__DENALI_PHY_20_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0_WIDTH                       32U
+#define LPDDR4__PHY_RDLVL_PATT9_0__REG DENALI_PHY_20
+#define LPDDR4__PHY_RDLVL_PATT9_0__FLD LPDDR4__DENALI_PHY_20__PHY_RDLVL_PATT9_0
+
+#define LPDDR4__DENALI_PHY_21_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT10_0__REG DENALI_PHY_21
+#define LPDDR4__PHY_RDLVL_PATT10_0__FLD LPDDR4__DENALI_PHY_21__PHY_RDLVL_PATT10_0
+
+#define LPDDR4__DENALI_PHY_22_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT11_0__REG DENALI_PHY_22
+#define LPDDR4__PHY_RDLVL_PATT11_0__FLD LPDDR4__DENALI_PHY_22__PHY_RDLVL_PATT11_0
+
+#define LPDDR4__DENALI_PHY_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT12_0__REG DENALI_PHY_23
+#define LPDDR4__PHY_RDLVL_PATT12_0__FLD LPDDR4__DENALI_PHY_23__PHY_RDLVL_PATT12_0
+
+#define LPDDR4__DENALI_PHY_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT13_0__REG DENALI_PHY_24
+#define LPDDR4__PHY_RDLVL_PATT13_0__FLD LPDDR4__DENALI_PHY_24__PHY_RDLVL_PATT13_0
+
+#define LPDDR4__DENALI_PHY_25_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT14_0__REG DENALI_PHY_25
+#define LPDDR4__PHY_RDLVL_PATT14_0__FLD LPDDR4__DENALI_PHY_25__PHY_RDLVL_PATT14_0
+
+#define LPDDR4__DENALI_PHY_26_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT15_0__REG DENALI_PHY_26
+#define LPDDR4__PHY_RDLVL_PATT15_0__FLD LPDDR4__DENALI_PHY_26__PHY_RDLVL_PATT15_0
+
+#define LPDDR4__DENALI_PHY_27_READ_MASK                              0x070F0107U
+#define LPDDR4__DENALI_PHY_27_WRITE_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_MASK      0x00000007U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0_WIDTH              3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_0__FLD LPDDR4__DENALI_PHY_27__PHY_SLAVE_LOOP_CNT_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_MASK    0x00000100U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0_WOSET            0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_0__FLD LPDDR4__DENALI_PHY_27__PHY_SW_FIFO_PTR_RST_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0_WIDTH         4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_MASTER_DLY_LOCK_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_MASK        0x07000000U
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0_WIDTH                3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__REG DENALI_PHY_27
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_27__PHY_RDDQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28_READ_MASK                              0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_28_WRITE_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_MASK    0x0000000FU
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0_WIDTH            4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_RDDQS_DQ_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_MASK          0x00000F00U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0_WIDTH                  4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_WR_ENC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0_WIDTH                4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_WR_SHIFT_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0_WIDTH                4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__REG DENALI_PHY_28
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_28__PHY_FIFO_PTR_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_29_READ_MASK                              0x3F030001U
+#define LPDDR4__DENALI_PHY_29_WRITE_MASK                             0x3F030001U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0_WOSET                     0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_LVL_DEBUG_MODE_0__FLD LPDDR4__DENALI_PHY_29__PHY_LVL_DEBUG_MODE_0
+
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0_WOSET                  0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__REG DENALI_PHY_29
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_0__FLD LPDDR4__DENALI_PHY_29__SC_PHY_LVL_DEBUG_CONT_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_MASK                 0x00030000U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0_WIDTH                         2U
+#define LPDDR4__PHY_WRLVL_ALGO_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WRLVL_ALGO_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_ALGO_0
+
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_MASK          0x3F000000U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__REG DENALI_PHY_29
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_29__PHY_WRLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_30_READ_MASK                              0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_30_WRITE_MASK                             0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_WRLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_SHIFT                            8U
+#define LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0_WIDTH                            8U
+#define LPDDR4__PHY_DQ_MASK_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_DQ_MASK_0__FLD LPDDR4__DENALI_PHY_30__PHY_DQ_MASK_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_MASK          0x003F0000U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_30
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_30__PHY_GTLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31_READ_MASK                              0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31_WRITE_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_MASK          0x0000003FU
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0_WIDTH                  6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_CAPTURE_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0_WIDTH                4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_MASK              0x00030000U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0_WIDTH                      2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_OP_MODE_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_OP_MODE_0
+
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_MASK  0x1F000000U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0_WIDTH          5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__REG DENALI_PHY_31
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_31__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_32_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_32_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0_WIDTH                    8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_DATA_MASK_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_MASK_0
+
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_MASK         0x03FFFF00U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0_WIDTH                18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__REG DENALI_PHY_32
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_0__FLD LPDDR4__DENALI_PHY_32__PHY_RDLVL_DATA_SWIZZLE_0
+
+#define LPDDR4__DENALI_PHY_33_READ_MASK                              0x00073FFFU
+#define LPDDR4__DENALI_PHY_33_WRITE_MASK                             0x00073FFFU
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_CLK_JITTER_TOLERANCE_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0_WIDTH                   6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_BURST_CNT_0
+
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_MASK                0x00070000U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0_WIDTH                        3U
+#define LPDDR4__PHY_WDQLVL_PATT_0__REG DENALI_PHY_33
+#define LPDDR4__PHY_WDQLVL_PATT_0__FLD LPDDR4__DENALI_PHY_33__PHY_WDQLVL_PATT_0
+
+#define LPDDR4__DENALI_PHY_34_READ_MASK                              0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_34_WRITE_MASK                             0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_SHIFT    0U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0_WIDTH   11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_UPDT_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_MASK     0x0F000000U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_SHIFT            24U
+#define LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0_WIDTH             4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__REG DENALI_PHY_34
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_34__PHY_WDQLVL_DQDM_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_35_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_PHY_35_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0_WIDTH         8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_PERIODIC_OBS_SELECT_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0_WIDTH                8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DQ_SLV_DELTA_0
+
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_MASK         0x000F0000U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0_WIDTH                 4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__REG DENALI_PHY_35
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_35__PHY_WDQLVL_DM_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WIDTH         1U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOCLR         0U
+#define LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0_WOSET         0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__REG DENALI_PHY_35
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0__FLD LPDDR4__DENALI_PHY_35__SC_PHY_WDQLVL_CLR_PREV_RESULTS_0
+
+#define LPDDR4__DENALI_PHY_36_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PHY_36_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0_WIDTH                 9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__REG DENALI_PHY_36
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_0__FLD LPDDR4__DENALI_PHY_36__PHY_WDQLVL_DATADM_MASK_0
+
+#define LPDDR4__DENALI_PHY_37_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT0_0__REG DENALI_PHY_37
+#define LPDDR4__PHY_USER_PATT0_0__FLD LPDDR4__DENALI_PHY_37__PHY_USER_PATT0_0
+
+#define LPDDR4__DENALI_PHY_38_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT1_0__REG DENALI_PHY_38
+#define LPDDR4__PHY_USER_PATT1_0__FLD LPDDR4__DENALI_PHY_38__PHY_USER_PATT1_0
+
+#define LPDDR4__DENALI_PHY_39_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT2_0__REG DENALI_PHY_39
+#define LPDDR4__PHY_USER_PATT2_0__FLD LPDDR4__DENALI_PHY_39__PHY_USER_PATT2_0
+
+#define LPDDR4__DENALI_PHY_40_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0_WIDTH                        32U
+#define LPDDR4__PHY_USER_PATT3_0__REG DENALI_PHY_40
+#define LPDDR4__PHY_USER_PATT3_0__FLD LPDDR4__DENALI_PHY_40__PHY_USER_PATT3_0
+
+#define LPDDR4__DENALI_PHY_41_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_41_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0_WIDTH                        16U
+#define LPDDR4__PHY_USER_PATT4_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_USER_PATT4_0__FLD LPDDR4__DENALI_PHY_41__PHY_USER_PATT4_0
+
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_MASK             0x00010000U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0_WOSET                     0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__REG DENALI_PHY_41
+#define LPDDR4__PHY_NTP_MULT_TRAIN_0__FLD LPDDR4__DENALI_PHY_41__PHY_NTP_MULT_TRAIN_0
+
+#define LPDDR4__DENALI_PHY_42_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_MASK        0x000003FFU
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0_WIDTH               10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_MASK       0x03FF0000U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0_WIDTH              10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__REG DENALI_PHY_42
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_42__PHY_NTP_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_43_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_MASK   0x000003FFU
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0_WIDTH          10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MIN_0
+
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_MASK   0x03FF0000U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0_WIDTH          10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__REG DENALI_PHY_43
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_0__FLD LPDDR4__DENALI_PHY_43__PHY_NTP_PERIOD_THRESHOLD_MAX_0
+
+#define LPDDR4__DENALI_PHY_44_READ_MASK                              0x00FF0001U
+#define LPDDR4__DENALI_PHY_44_WRITE_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_MASK   0x00000001U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WIDTH           1U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WOCLR           0U
+#define LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0_WOSET           0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_0__FLD LPDDR4__DENALI_PHY_44__PHY_CALVL_VREF_DRIVING_SLICE_0
+
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0_WIDTH                    6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__REG DENALI_PHY_44
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_44__SC_PHY_MANUAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_MASK               0x00FF0000U
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0_WIDTH                       8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__REG DENALI_PHY_44
+#define LPDDR4__PHY_FIFO_PTR_OBS_0__FLD LPDDR4__DENALI_PHY_44__PHY_FIFO_PTR_OBS_0
+
+#define LPDDR4__DENALI_PHY_45_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0_WIDTH                   32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__REG DENALI_PHY_45
+#define LPDDR4__PHY_LPBK_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_45__PHY_LPBK_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_46_READ_MASK                              0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_46_WRITE_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_MASK       0x0000FFFFU
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0_WIDTH              16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_LPBK_ERROR_COUNT_OBS_0
+
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_MASK        0x07FF0000U
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__REG DENALI_PHY_46
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_0__FLD LPDDR4__DENALI_PHY_46__PHY_MASTER_DLY_LOCK_OBS_0
+
+#define LPDDR4__DENALI_PHY_47_READ_MASK                              0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_47_WRITE_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_MASK       0x0000007FU
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0_WIDTH               7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQ_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_MASK        0x00FF0000U
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0_WIDTH                8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_0__FLD LPDDR4__DENALI_PHY_47__PHY_MEAS_DLY_STEP_VALUE_0
+
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 24U
+#define LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_47
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_47__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48_READ_MASK                              0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_48_WRITE_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_SHIFT 0U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_SHIFT         8U
+#define LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0_WIDTH        11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_SHIFT        24U
+#define LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0_WIDTH         7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_48
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_48__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49_READ_MASK                              0x0007FFFFU
+#define LPDDR4__DENALI_PHY_49_WRITE_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_MASK  0x000000FFU
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0_WIDTH          8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_MASK   0x0000FF00U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0_WIDTH           8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WR_ADDER_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0_WIDTH                       3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__REG DENALI_PHY_49
+#define LPDDR4__PHY_WR_SHIFT_OBS_0__FLD LPDDR4__DENALI_PHY_49__PHY_WR_SHIFT_OBS_0
+
+#define LPDDR4__DENALI_PHY_50_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_50_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_MASK      0x000003FFU
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0_WIDTH             10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0_WIDTH             10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_50
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_50__PHY_WRLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_51_READ_MASK                              0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51_WRITE_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_MASK           0x001FFFFFU
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0_WIDTH                  21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__REG DENALI_PHY_51
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_51__PHY_WRLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_52_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_52_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0_WIDTH        10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0_WIDTH        10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__REG DENALI_PHY_52
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0__FLD LPDDR4__DENALI_PHY_52__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_0
+
+#define LPDDR4__DENALI_PHY_53_READ_MASK                              0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_53_WRITE_MASK                             0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_MASK      0x00003FFFU
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0_WIDTH             14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD0_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_MASK      0x3FFF0000U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_SHIFT             16U
+#define LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0_WIDTH             14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__REG DENALI_PHY_53
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_0__FLD LPDDR4__DENALI_PHY_53__PHY_GTLVL_HARD1_DELAY_OBS_0
+
+#define LPDDR4__DENALI_PHY_54_READ_MASK                              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54_WRITE_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_MASK           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0_WIDTH                  18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG DENALI_PHY_54
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_54__PHY_GTLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_55_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0_WIDTH         10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_SHIFT         16U
+#define LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0_WIDTH         10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__REG DENALI_PHY_55
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_55__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_56_READ_MASK                              0x00000003U
+#define LPDDR4__DENALI_PHY_56_WRITE_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0_WIDTH     2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__REG DENALI_PHY_56
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0__FLD LPDDR4__DENALI_PHY_56__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_0
+
+#define LPDDR4__DENALI_PHY_57_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0_WIDTH                  32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG DENALI_PHY_57
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_57__PHY_RDLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_58_READ_MASK                              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_58_WRITE_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0_WIDTH            11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_LE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0_WIDTH            11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__REG DENALI_PHY_58
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_58__PHY_WDQLVL_DQDM_TE_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_59_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG DENALI_PHY_59
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_0__FLD LPDDR4__DENALI_PHY_59__PHY_WDQLVL_STATUS_OBS_0
+
+#define LPDDR4__DENALI_PHY_60_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0_WIDTH               32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__REG DENALI_PHY_60
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_0__FLD LPDDR4__DENALI_PHY_60__PHY_WDQLVL_PERIODIC_OBS_0
+
+#define LPDDR4__DENALI_PHY_61_READ_MASK                              0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61_WRITE_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_MASK                   0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0_WIDTH                          31U
+#define LPDDR4__PHY_DDL_MODE_0__REG DENALI_PHY_61
+#define LPDDR4__PHY_DDL_MODE_0__FLD LPDDR4__DENALI_PHY_61__PHY_DDL_MODE_0
+
+#define LPDDR4__DENALI_PHY_62_READ_MASK                              0x0000003FU
+#define LPDDR4__DENALI_PHY_62_WRITE_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0_WIDTH                           6U
+#define LPDDR4__PHY_DDL_MASK_0__REG DENALI_PHY_62
+#define LPDDR4__PHY_DDL_MASK_0__FLD LPDDR4__DENALI_PHY_62__PHY_DDL_MASK_0
+
+#define LPDDR4__DENALI_PHY_63_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0_WIDTH                      32U
+#define LPDDR4__PHY_DDL_TEST_OBS_0__REG DENALI_PHY_63
+#define LPDDR4__PHY_DDL_TEST_OBS_0__FLD LPDDR4__DENALI_PHY_63__PHY_DDL_TEST_OBS_0
+
+#define LPDDR4__DENALI_PHY_64_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_MASK      0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0_WIDTH             32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__REG DENALI_PHY_64
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_0__FLD LPDDR4__DENALI_PHY_64__PHY_DDL_TEST_MSTR_DLY_OBS_0
+
+#define LPDDR4__DENALI_PHY_65_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_65_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_MASK    0x000000FFU
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0_WIDTH            8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_65__PHY_DDL_TRACK_UPD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0_WOSET                 0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_0__FLD LPDDR4__DENALI_PHY_65__PHY_LP4_WDQS_OE_EXTEND_0
+
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ0_0__REG DENALI_PHY_65
+#define LPDDR4__PHY_RX_CAL_DQ0_0__FLD LPDDR4__DENALI_PHY_65__PHY_RX_CAL_DQ0_0
+
+#define LPDDR4__DENALI_PHY_66_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_66_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ1_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_RX_CAL_DQ1_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ1_0
+
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ2_0__REG DENALI_PHY_66
+#define LPDDR4__PHY_RX_CAL_DQ2_0__FLD LPDDR4__DENALI_PHY_66__PHY_RX_CAL_DQ2_0
+
+#define LPDDR4__DENALI_PHY_67_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ3_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ3_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ3_0
+
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ4_0__REG DENALI_PHY_67
+#define LPDDR4__PHY_RX_CAL_DQ4_0__FLD LPDDR4__DENALI_PHY_67__PHY_RX_CAL_DQ4_0
+
+#define LPDDR4__DENALI_PHY_68_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ5_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ5_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ5_0
+
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_MASK                 0x01FF0000U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ6_0__REG DENALI_PHY_68
+#define LPDDR4__PHY_RX_CAL_DQ6_0__FLD LPDDR4__DENALI_PHY_68__PHY_RX_CAL_DQ6_0
+
+#define LPDDR4__DENALI_PHY_69_READ_MASK                              0x000001FFU
+#define LPDDR4__DENALI_PHY_69_WRITE_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQ7_0__REG DENALI_PHY_69
+#define LPDDR4__PHY_RX_CAL_DQ7_0__FLD LPDDR4__DENALI_PHY_69__PHY_RX_CAL_DQ7_0
+
+#define LPDDR4__DENALI_PHY_70_READ_MASK                              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70_WRITE_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_MASK                  0x0003FFFFU
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0_WIDTH                         18U
+#define LPDDR4__PHY_RX_CAL_DM_0__REG DENALI_PHY_70
+#define LPDDR4__PHY_RX_CAL_DM_0__FLD LPDDR4__DENALI_PHY_70__PHY_RX_CAL_DM_0
+
+#define LPDDR4__DENALI_PHY_71_READ_MASK                              0x01FF01FFU
+#define LPDDR4__DENALI_PHY_71_WRITE_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_MASK                 0x000001FFU
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0_WIDTH                         9U
+#define LPDDR4__PHY_RX_CAL_DQS_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_DQS_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_DQS_0
+
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_FDBK_0__REG DENALI_PHY_71
+#define LPDDR4__PHY_RX_CAL_FDBK_0__FLD LPDDR4__DENALI_PHY_71__PHY_RX_CAL_FDBK_0
+
+#define LPDDR4__DENALI_PHY_72_READ_MASK                              0x071F07FFU
+#define LPDDR4__DENALI_PHY_72_WRITE_MASK                             0x071F07FFU
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0_WIDTH                    11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_0__FLD LPDDR4__DENALI_PHY_72__PHY_PAD_RX_BIAS_EN_0
+
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_MASK         0x001F0000U
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0_WIDTH                 5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_0__FLD LPDDR4__DENALI_PHY_72__PHY_STATIC_TOG_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_MASK              0x07000000U
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0_WIDTH                      3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__REG DENALI_PHY_72
+#define LPDDR4__PHY_FDBK_PWR_CTRL_0__FLD LPDDR4__DENALI_PHY_72__PHY_FDBK_PWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_73_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_PHY_73_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WIDTH          1U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOCLR          0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0_WOSET          0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_SLV_DLY_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WIDTH                1U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WOCLR                0U
+#define LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0_WOSET                0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_RDPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WIDTH        1U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOCLR        0U
+#define LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0_WOSET        0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WIDTH              1U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WOCLR              0U
+#define LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0_WOSET              0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__REG DENALI_PHY_73
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_0__FLD LPDDR4__DENALI_PHY_73__PHY_SLICE_PWR_RDC_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_74_READ_MASK                              0x07FFFF07U
+#define LPDDR4__DENALI_PHY_74_WRITE_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_MASK             0x00000007U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0_WIDTH                     3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_MASK             0x00FFFF00U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0_WIDTH                    16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQ_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQ_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_MASK            0x07000000U
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0_WIDTH                    3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__REG DENALI_PHY_74
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_0__FLD LPDDR4__DENALI_PHY_74__PHY_DQS_TSEL_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_75_READ_MASK                              0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_75_WRITE_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0_WIDTH                   16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_DQS_TSEL_SELECT_0__FLD LPDDR4__DENALI_PHY_75__PHY_DQS_TSEL_SELECT_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0_WIDTH                   2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_0__FLD LPDDR4__DENALI_PHY_75__PHY_TWO_CYC_PREAMBLE_0
+
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_MASK   0x7F000000U
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__REG DENALI_PHY_75
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_0__FLD LPDDR4__DENALI_PHY_75__PHY_VREF_INITIAL_START_POINT_0
+
+#define LPDDR4__DENALI_PHY_76_READ_MASK                              0xFF01037FU
+#define LPDDR4__DENALI_PHY_76_WRITE_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_MASK    0x0000007FU
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0_WIDTH            7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_0__FLD LPDDR4__DENALI_PHY_76__PHY_VREF_INITIAL_STOP_POINT_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_MASK         0x00000300U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0_WIDTH                 2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_0__FLD LPDDR4__DENALI_PHY_76__PHY_VREF_TRAINING_CTRL_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0_WOSET                       0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_NTP_TRAIN_EN_0__FLD LPDDR4__DENALI_PHY_76__PHY_NTP_TRAIN_EN_0
+
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_MASK          0xFF000000U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0_WIDTH                  8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__REG DENALI_PHY_76
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_0__FLD LPDDR4__DENALI_PHY_76__PHY_NTP_WDQ_STEP_SIZE_0
+
+#define LPDDR4__DENALI_PHY_77_READ_MASK                              0x07FF07FFU
+#define LPDDR4__DENALI_PHY_77_WRITE_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_MASK              0x000007FFU
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0_WIDTH                     11U
+#define LPDDR4__PHY_NTP_WDQ_START_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_NTP_WDQ_START_0__FLD LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_START_0
+
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_MASK               0x07FF0000U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0_WIDTH                      11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__REG DENALI_PHY_77
+#define LPDDR4__PHY_NTP_WDQ_STOP_0__FLD LPDDR4__DENALI_PHY_77__PHY_NTP_WDQ_STOP_0
+
+#define LPDDR4__DENALI_PHY_78_READ_MASK                              0x0103FFFFU
+#define LPDDR4__DENALI_PHY_78_WRITE_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_MASK             0x000000FFU
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0_WIDTH                     8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_0__FLD LPDDR4__DENALI_PHY_78__PHY_NTP_WDQ_BIT_EN_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_MASK             0x0003FF00U
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0_WIDTH                    10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_0__FLD LPDDR4__DENALI_PHY_78__PHY_WDQLVL_DVW_MIN_0
+
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_SHIFT              24U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WIDTH               1U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOCLR               0U
+#define LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0_WOSET               0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__REG DENALI_PHY_78
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_0__FLD LPDDR4__DENALI_PHY_78__PHY_SW_WDQLVL_DVW_MIN_EN_0
+
+#define LPDDR4__DENALI_PHY_79_READ_MASK                              0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_79_WRITE_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_MASK    0x0000003FU
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0_WIDTH            6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_0__FLD LPDDR4__DENALI_PHY_79__PHY_WDQLVL_PER_START_OFFSET_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_MASK                0x00000F00U
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0_WIDTH                        4U
+#define LPDDR4__PHY_FAST_LVL_EN_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_FAST_LVL_EN_0__FLD LPDDR4__DENALI_PHY_79__PHY_FAST_LVL_EN_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_MASK                 0x001F0000U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_SHIFT                        16U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0_WIDTH                         5U
+#define LPDDR4__PHY_PAD_TX_DCD_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_PAD_TX_DCD_0__FLD LPDDR4__DENALI_PHY_79__PHY_PAD_TX_DCD_0
+
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_MASK               0x1F000000U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__REG DENALI_PHY_79
+#define LPDDR4__PHY_PAD_RX_DCD_0_0__FLD LPDDR4__DENALI_PHY_79__PHY_PAD_RX_DCD_0_0
+
+#define LPDDR4__DENALI_PHY_80_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_80_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_MASK               0x0000001FU
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_1_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_1_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_MASK               0x00001F00U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_2_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_2_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_MASK               0x001F0000U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_3_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_3_0
+
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_MASK               0x1F000000U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_SHIFT                      24U
+#define LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__REG DENALI_PHY_80
+#define LPDDR4__PHY_PAD_RX_DCD_4_0__FLD LPDDR4__DENALI_PHY_80__PHY_PAD_RX_DCD_4_0
+
+#define LPDDR4__DENALI_PHY_81_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_81_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_MASK               0x0000001FU
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_5_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_5_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_MASK               0x00001F00U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_6_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_6_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_MASK               0x001F0000U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0_WIDTH                       5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_RX_DCD_7_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_RX_DCD_7_0
+
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0_WIDTH                      5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__REG DENALI_PHY_81
+#define LPDDR4__PHY_PAD_DM_RX_DCD_0__FLD LPDDR4__DENALI_PHY_81__PHY_PAD_DM_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82_READ_MASK                              0x007F1F1FU
+#define LPDDR4__DENALI_PHY_82_WRITE_MASK                             0x007F1F1FU
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_MASK             0x0000001FU
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0_WIDTH                     5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_DQS_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0_WIDTH                    5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_FDBK_RX_DCD_0
+
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_MASK          0x007F0000U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0_WIDTH                  7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__REG DENALI_PHY_82
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_0__FLD LPDDR4__DENALI_PHY_82__PHY_PAD_DSLICE_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_83_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_83_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_83__PHY_RDDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__REG DENALI_PHY_83
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_83__PHY_RDDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_84_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_84_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_84__PHY_RDDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__REG DENALI_PHY_84
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_84__PHY_RDDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_85_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_85_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_85__PHY_RDDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__REG DENALI_PHY_85
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_85__PHY_RDDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_86_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_86_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_86__PHY_RDDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0_WIDTH                 10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__REG DENALI_PHY_86
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_86__PHY_RDDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_87_READ_MASK                              0x1F0703FFU
+#define LPDDR4__DENALI_PHY_87_WRITE_MASK                             0x1F0703FFU
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0_WIDTH                  10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_87__PHY_RDDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_MASK            0x00070000U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0_WIDTH                    3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_0__FLD LPDDR4__DENALI_PHY_87__PHY_RX_PCLK_CLK_SEL_0
+
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0_WIDTH                     5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__REG DENALI_PHY_87
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_0__FLD LPDDR4__DENALI_PHY_87__PHY_RX_CAL_ALL_DLY_0
+
+#define LPDDR4__DENALI_PHY_88_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_88_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_MASK               0x000000FFU
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0_WIDTH                       8U
+#define LPDDR4__PHY_DQ_OE_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_MASK          0x0000FF00U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0_WIDTH                  8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0_WIDTH                  8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQ_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_MASK              0xFF000000U
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0_WIDTH                      8U
+#define LPDDR4__PHY_DQS_OE_TIMING_0__REG DENALI_PHY_88
+#define LPDDR4__PHY_DQS_OE_TIMING_0__FLD LPDDR4__DENALI_PHY_88__PHY_DQS_OE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89_READ_MASK                              0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_89_WRITE_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_MASK        0x0000000FU
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0_WIDTH                4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_IO_PAD_DELAY_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0_WIDTH                 8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_MASK           0x00FF0000U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0_WIDTH                   8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_OE_RD_TIMING_0
+
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0_WIDTH                 8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__REG DENALI_PHY_89
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_0__FLD LPDDR4__DENALI_PHY_89__PHY_DQS_TSEL_WR_TIMING_0
+
+#define LPDDR4__DENALI_PHY_90_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_90_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0_WIDTH                 16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_VREF_SETTING_TIME_0__FLD LPDDR4__DENALI_PHY_90__PHY_VREF_SETTING_TIME_0
+
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_MASK           0x0FFF0000U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0_WIDTH                  12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__REG DENALI_PHY_90
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_0__FLD LPDDR4__DENALI_PHY_90__PHY_PAD_VREF_CTRL_DQ_0
+
+#define LPDDR4__DENALI_PHY_91_READ_MASK                              0x0303FFFFU
+#define LPDDR4__DENALI_PHY_91_WRITE_MASK                             0x0303FFFFU
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_MASK               0x000000FFU
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0_WIDTH                       8U
+#define LPDDR4__PHY_DQ_IE_TIMING_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_DQ_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_91__PHY_DQ_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_MASK              0x0000FF00U
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0_WIDTH                      8U
+#define LPDDR4__PHY_DQS_IE_TIMING_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_DQS_IE_TIMING_0__FLD LPDDR4__DENALI_PHY_91__PHY_DQS_IE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_MASK           0x00030000U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0_WIDTH                   2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_0__FLD LPDDR4__DENALI_PHY_91__PHY_RDDATA_EN_IE_DLY_0
+
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_MASK                    0x03000000U
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_SHIFT                           24U
+#define LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0_WIDTH                            2U
+#define LPDDR4__PHY_IE_MODE_0__REG DENALI_PHY_91
+#define LPDDR4__PHY_IE_MODE_0__FLD LPDDR4__DENALI_PHY_91__PHY_IE_MODE_0
+
+#define LPDDR4__DENALI_PHY_92_READ_MASK                              0x1F1F0103U
+#define LPDDR4__DENALI_PHY_92_WRITE_MASK                             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0_WIDTH                           2U
+#define LPDDR4__PHY_DBI_MODE_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_DBI_MODE_0__FLD LPDDR4__DENALI_PHY_92__PHY_DBI_MODE_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_MASK               0x00000100U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0_WOSET                       0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_IE_ON_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_IE_ON_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_MASK       0x001F0000U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0_WIDTH               5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_MASK  0x1F000000U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0_WIDTH          5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_92
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_92__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_93_READ_MASK                              0x000F1F1FU
+#define LPDDR4__DENALI_PHY_93_WRITE_MASK                             0x000F1F1FU
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_MASK         0x0000001FU
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0_WIDTH                 5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_TSEL_DLY_0
+
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0_WIDTH                   5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_0__FLD LPDDR4__DENALI_PHY_93__PHY_RDDATA_EN_OE_DLY_0
+
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_MASK             0x000F0000U
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0_WIDTH                     4U
+#define LPDDR4__PHY_SW_MASTER_MODE_0__REG DENALI_PHY_93
+#define LPDDR4__PHY_SW_MASTER_MODE_0__FLD LPDDR4__DENALI_PHY_93__PHY_SW_MASTER_MODE_0
+
+#define LPDDR4__DENALI_PHY_94_READ_MASK                              0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_94_WRITE_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0_WIDTH                11U
+#define LPDDR4__PHY_MASTER_DELAY_START_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_START_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_START_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_MASK          0x003F0000U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0_WIDTH                  6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_STEP_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_STEP_0
+
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_MASK          0xFF000000U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0_WIDTH                  8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__REG DENALI_PHY_94
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_0__FLD LPDDR4__DENALI_PHY_94__PHY_MASTER_DELAY_WAIT_0
+
+#define LPDDR4__DENALI_PHY_95_READ_MASK                              0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_95_WRITE_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_MASK  0x000000FFU
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_SHIFT          0U
+#define LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0_WIDTH          8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_0__FLD LPDDR4__DENALI_PHY_95__PHY_MASTER_DELAY_HALF_MEASURE_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_MASK                0x00000F00U
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_SHIFT                        8U
+#define LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0_WIDTH                        4U
+#define LPDDR4__PHY_RPTR_UPDATE_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_RPTR_UPDATE_0__FLD LPDDR4__DENALI_PHY_95__PHY_RPTR_UPDATE_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_MASK             0x00FF0000U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0_WIDTH                     8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_WRLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_MASK        0x0F000000U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_SHIFT               24U
+#define LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0_WIDTH                4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__REG DENALI_PHY_95
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_0__FLD LPDDR4__DENALI_PHY_95__PHY_WRLVL_DLY_FINE_STEP_0
+
+#define LPDDR4__DENALI_PHY_96_READ_MASK                              0x001F0F3FU
+#define LPDDR4__DENALI_PHY_96_WRITE_MASK                             0x001F0F3FU
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_MASK        0x0000003FU
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_SHIFT                0U
+#define LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0_WIDTH                6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_96__PHY_WRLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0_WIDTH                     4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_GTLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_96__PHY_GTLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_SHIFT               16U
+#define LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0_WIDTH                5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__REG DENALI_PHY_96
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_0__FLD LPDDR4__DENALI_PHY_96__PHY_GTLVL_RESP_WAIT_CNT_0
+
+#define LPDDR4__DENALI_PHY_97_READ_MASK                              0x03FF03FFU
+#define LPDDR4__DENALI_PHY_97_WRITE_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0_WIDTH                   10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_GTLVL_BACK_STEP_0__FLD LPDDR4__DENALI_PHY_97__PHY_GTLVL_BACK_STEP_0
+
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_MASK           0x03FF0000U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0_WIDTH                  10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__REG DENALI_PHY_97
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_0__FLD LPDDR4__DENALI_PHY_97__PHY_GTLVL_FINAL_STEP_0
+
+#define LPDDR4__DENALI_PHY_98_READ_MASK                              0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_98_WRITE_MASK                             0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0_WIDTH                    8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_MASK        0x00000F00U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0_WIDTH                4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_QTR_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_MASK     0x01FF0000U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0_WIDTH             9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__REG DENALI_PHY_98
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_0__FLD LPDDR4__DENALI_PHY_98__PHY_WDQLVL_DM_SEARCH_RANGE_0
+
+#define LPDDR4__DENALI_PHY_99_READ_MASK                              0x00000F01U
+#define LPDDR4__DENALI_PHY_99_WRITE_MASK                             0x00000F01U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0_WOSET                 0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_0__FLD LPDDR4__DENALI_PHY_99__PHY_TOGGLE_PRE_SUPPORT_0
+
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0_WIDTH                     4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__REG DENALI_PHY_99
+#define LPDDR4__PHY_RDLVL_DLY_STEP_0__FLD LPDDR4__DENALI_PHY_99__PHY_RDLVL_DLY_STEP_0
+
+#define LPDDR4__DENALI_PHY_100_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_100_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0_WIDTH                   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__REG DENALI_PHY_100
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_0__FLD LPDDR4__DENALI_PHY_100__PHY_RDLVL_MAX_EDGE_0
+
+#define LPDDR4__DENALI_PHY_101_READ_MASK                             0x7F7F0703U
+#define LPDDR4__DENALI_PHY_101_WRITE_MASK                            0x7F7F0703U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_DISABLE_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0_WIDTH                3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_0__FLD LPDDR4__DENALI_PHY_101__PHY_WRPATH_GATE_TIMING_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_MASK             0x007F0000U
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0_WIDTH                     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_WDQ_OSC_DELTA_0__FLD LPDDR4__DENALI_PHY_101__PHY_WDQ_OSC_DELTA_0
+
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_MASK      0x7F000000U
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_SHIFT             24U
+#define LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0_WIDTH              7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__REG DENALI_PHY_101
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_0__FLD LPDDR4__DENALI_PHY_101__PHY_MEAS_DLY_STEP_ENABLE_0
+
+#define LPDDR4__DENALI_PHY_102_READ_MASK                             0x0000001FU
+#define LPDDR4__DENALI_PHY_102_WRITE_MASK                            0x0000001FU
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_MASK             0x0000001FU
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0_WIDTH                     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__REG DENALI_PHY_102
+#define LPDDR4__PHY_RDDATA_EN_DLY_0__FLD LPDDR4__DENALI_PHY_102__PHY_RDDATA_EN_DLY_0
+
+#define LPDDR4__DENALI_PHY_103_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0_WIDTH                   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__REG DENALI_PHY_103
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_0__FLD LPDDR4__DENALI_PHY_103__PHY_DQ_DM_SWIZZLE0_0
+
+#define LPDDR4__DENALI_PHY_104_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_104_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0_WIDTH                    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__REG DENALI_PHY_104
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_0__FLD LPDDR4__DENALI_PHY_104__PHY_DQ_DM_SWIZZLE1_0
+
+#define LPDDR4__DENALI_PHY_105_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_105_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__REG DENALI_PHY_105
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_105__PHY_CLK_WRDQ1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_106_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_106_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__REG DENALI_PHY_106
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_106__PHY_CLK_WRDQ3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_107_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_107_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ4_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__REG DENALI_PHY_107
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_107__PHY_CLK_WRDQ5_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_108_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_108_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ6_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__REG DENALI_PHY_108
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_108__PHY_CLK_WRDQ7_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_109_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_109_WRITE_MASK                            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_109__PHY_CLK_WRDM_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_SHIFT            16U
+#define LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__REG DENALI_PHY_109
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_109__PHY_CLK_WRDQS_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_110_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_110_WRITE_MASK                            0x0003FF03U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_SHIFT            0U
+#define LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_0__FLD LPDDR4__DENALI_PHY_110__PHY_WRLVL_THRESHOLD_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_SHIFT        8U
+#define LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__REG DENALI_PHY_110
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_110__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_111_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_111_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__REG DENALI_PHY_111
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_111__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_112_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_112_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__REG DENALI_PHY_112
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_112__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_113_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_113_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__REG DENALI_PHY_113
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_113__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_114_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__REG DENALI_PHY_114
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_114__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_115_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__REG DENALI_PHY_115
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_115__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_116_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__REG DENALI_PHY_116
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_116__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_117_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__REG DENALI_PHY_117
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_117__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_118_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__REG DENALI_PHY_118
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_118__PHY_RDDQS_DM_RISE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_DM_FALL_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__REG DENALI_PHY_119
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_119__PHY_RDDQS_GATE_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_120_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_120_WRITE_MASK                            0x03FF070FU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_0__FLD LPDDR4__DENALI_PHY_120__PHY_RDDQS_LATENCY_ADJUST_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_SHIFT                8U
+#define LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0_WIDTH                3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_0__FLD LPDDR4__DENALI_PHY_120__PHY_WRITE_PATH_LAT_ADD_0
+
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_SHIFT      16U
+#define LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__REG DENALI_PHY_120
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_120__PHY_WRLVL_DELAY_EARLY_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_121_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_121_WRITE_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_SHIFT      0U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_0
+
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_SHIFT           16U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WIDTH            1U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOCLR            0U
+#define LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__REG DENALI_PHY_121
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_0__FLD LPDDR4__DENALI_PHY_121__PHY_WRLVL_EARLY_FORCE_ZERO_0
+
+#define LPDDR4__DENALI_PHY_122_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_122_WRITE_MASK                            0x000F03FFU
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_122__PHY_GTLVL_RDDQS_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_SHIFT              16U
+#define LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__REG DENALI_PHY_122
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_0__FLD LPDDR4__DENALI_PHY_122__PHY_GTLVL_LAT_ADJ_START_0
+
+#define LPDDR4__DENALI_PHY_123_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_123_WRITE_MASK                            0x010F07FFU
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_SHIFT         0U
+#define LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_123__PHY_WDQLVL_DQDM_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0_WIDTH                   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_NTP_WRLAT_START_0__FLD LPDDR4__DENALI_PHY_123__PHY_NTP_WRLAT_START_0
+
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0_WOSET                          0U
+#define LPDDR4__PHY_NTP_PASS_0__REG DENALI_PHY_123
+#define LPDDR4__PHY_NTP_PASS_0__FLD LPDDR4__DENALI_PHY_123__PHY_NTP_PASS_0
+
+#define LPDDR4__DENALI_PHY_124_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_124_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_SHIFT      0U
+#define LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__REG DENALI_PHY_124
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0__FLD LPDDR4__DENALI_PHY_124__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_0
+
+#define LPDDR4__DENALI_PHY_125_READ_MASK                             0x003FFFFFU
+#define LPDDR4__DENALI_PHY_125_WRITE_MASK                            0x003FFFFFU
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_SHIFT        0U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_0__FLD LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_BOOSTPN_SETTING_0
+
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_SHIFT       16U
+#define LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__REG DENALI_PHY_125
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_0__FLD LPDDR4__DENALI_PHY_125__PHY_DSLICE_PAD_RX_CTLE_SETTING_0
+
+#endif /* REG_LPDDR4_DATA_SLICE_0_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
new file mode 100644
index 000000000000..d60bb6afe828
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_data_slice_1_macros.h
@@ -0,0 +1,2036 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+#define REG_LPDDR4_DATA_SLICE_1_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_256_READ_MASK                             0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256_WRITE_MASK                            0x07FF7F07U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_MASK  0x00000007U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1_WIDTH          3U
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1_WIDTH        7U
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_256__PHY_LP4_BOOT_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_MASK 0x07FF0000U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1_WIDTH        11U
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_256
+#define LPDDR4__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_256__PHY_CLK_WR_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_257_READ_MASK                             0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257_WRITE_MASK                            0x0703FF0FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_MASK 0x0000000FU
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1_WIDTH        4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_IO_PAD_DELAY_TIMING_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_SHIFT      8U
+#define LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1_WIDTH     10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_CLK_WRDQS_SLAVE_DELAY_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1_WIDTH         3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__REG DENALI_PHY_257
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_BYPASS_1__FLD LPDDR4__DENALI_PHY_257__PHY_WRITE_PATH_LAT_ADD_BYPASS_1
+
+#define LPDDR4__DENALI_PHY_258_READ_MASK                             0x010303FFU
+#define LPDDR4__DENALI_PHY_258_WRITE_MASK                            0x010303FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_SHIFT     0U
+#define LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1_WIDTH    10U
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_258__PHY_RDDQS_GATE_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1_WIDTH           2U
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_BYPASS_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_258__PHY_BYPASS_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_MASK       0x01000000U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1_WOSET               0U
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__REG DENALI_PHY_258
+#define LPDDR4__PHY_CLK_BYPASS_OVERRIDE_1__FLD LPDDR4__DENALI_PHY_258__PHY_CLK_BYPASS_OVERRIDE_1
+
+#define LPDDR4__DENALI_PHY_259_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ0_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ1_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ2_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__REG DENALI_PHY_259
+#define LPDDR4__PHY_SW_WRDQ3_SHIFT_1__FLD LPDDR4__DENALI_PHY_259__PHY_SW_WRDQ3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_MASK            0x0000003FU
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ4_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ4_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_MASK            0x00003F00U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ5_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ5_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_MASK            0x003F0000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ6_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ6_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_MASK            0x3F000000U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1_WIDTH                    6U
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__REG DENALI_PHY_260
+#define LPDDR4__PHY_SW_WRDQ7_SHIFT_1__FLD LPDDR4__DENALI_PHY_260__PHY_SW_WRDQ7_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_261_WRITE_MASK                            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_MASK             0x0000003FU
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1_WIDTH                     6U
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDM_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDM_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1_WIDTH                    4U
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_SW_WRDQS_SHIFT_1__FLD LPDDR4__DENALI_PHY_261__PHY_SW_WRDQS_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_MASK 0x00030000U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1_WIDTH         2U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_MASK    0x1F000000U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1_WIDTH            5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__REG DENALI_PHY_261
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_261__PHY_LP4_BOOT_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_262_READ_MASK                             0x030F0F1FU
+#define LPDDR4__DENALI_PHY_262_WRITE_MASK                            0x030F0F1FU
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_SHIFT       0U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1_WIDTH       5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_MASK      0x00000F00U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_SHIFT              8U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1_WIDTH              4U
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_SHIFT    16U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1_WIDTH     4U
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_MASK 0x03000000U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_SHIFT     24U
+#define LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1_WIDTH      2U
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_262
+#define LPDDR4__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_262__PHY_LP4_BOOT_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_263_READ_MASK                             0x01FF031FU
+#define LPDDR4__DENALI_PHY_263_WRITE_MASK                            0x01FF031FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1_WIDTH         5U
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_263__PHY_LP4_BOOT_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_MASK              0x00000300U
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1_WIDTH                      2U
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_CTRL_LPBK_EN_1__FLD LPDDR4__DENALI_PHY_263__PHY_CTRL_LPBK_EN_1
+
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_MASK              0x01FF0000U
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1_WIDTH                      9U
+#define LPDDR4__PHY_LPBK_CONTROL_1__REG DENALI_PHY_263
+#define LPDDR4__PHY_LPBK_CONTROL_1__FLD LPDDR4__DENALI_PHY_263__PHY_LPBK_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_264_READ_MASK                             0x00000101U
+#define LPDDR4__DENALI_PHY_264_WRITE_MASK                            0x00000101U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1_WOSET               0U
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_LPBK_DFX_TIMEOUT_EN_1__FLD LPDDR4__DENALI_PHY_264__PHY_LPBK_DFX_TIMEOUT_EN_1
+
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1_WOSET           0U
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__REG DENALI_PHY_264
+#define LPDDR4__PHY_GATE_DELAY_COMP_DISABLE_1__FLD LPDDR4__DENALI_PHY_264__PHY_GATE_DELAY_COMP_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_265_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_MASK 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1_WIDTH       32U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__REG DENALI_PHY_265
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_CONTROL_1__FLD LPDDR4__DENALI_PHY_265__PHY_AUTO_TIMING_MARGIN_CONTROL_1
+
+#define LPDDR4__DENALI_PHY_266_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_MASK    0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1_WIDTH           28U
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__REG DENALI_PHY_266
+#define LPDDR4__PHY_AUTO_TIMING_MARGIN_OBS_1__FLD LPDDR4__DENALI_PHY_266__PHY_AUTO_TIMING_MARGIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_267_READ_MASK                             0x7F0101FFU
+#define LPDDR4__DENALI_PHY_267_WRITE_MASK                            0x7F0101FFU
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_MASK                   0x000001FFU
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1_WIDTH                           9U
+#define LPDDR4__PHY_DQ_IDLE_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_DQ_IDLE_1__FLD LPDDR4__DENALI_PHY_267__PHY_DQ_IDLE_1
+
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1_WOSET                       0U
+#define LPDDR4__PHY_PDA_MODE_EN_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_PDA_MODE_EN_1__FLD LPDDR4__DENALI_PHY_267__PHY_PDA_MODE_EN_1
+
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_MASK        0x7F000000U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_SHIFT               24U
+#define LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1_WIDTH                7U
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__REG DENALI_PHY_267
+#define LPDDR4__PHY_PRBS_PATTERN_START_1__FLD LPDDR4__DENALI_PHY_267__PHY_PRBS_PATTERN_START_1
+
+#define LPDDR4__DENALI_PHY_268_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_PHY_268_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_MASK         0x000001FFU
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1_WIDTH                 9U
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_PRBS_PATTERN_MASK_1__FLD LPDDR4__DENALI_PHY_268__PHY_PRBS_PATTERN_MASK_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_MASK   0x00010000U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1_WOSET           0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_ENABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_SHIFT     24U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WIDTH      1U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOCLR      0U
+#define LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1_WOSET      0U
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__REG DENALI_PHY_268
+#define LPDDR4__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_268__PHY_RDLVL_MULTI_PATT_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_269_READ_MASK                             0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_269_WRITE_MASK                            0x03FF7F3FU
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_MASK     0x0000003FU
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1_WIDTH             6U
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_VREF_INITIAL_STEPSIZE_1__FLD LPDDR4__DENALI_PHY_269__PHY_VREF_INITIAL_STEPSIZE_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_MASK            0x00007F00U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1_WIDTH                    7U
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_VREF_TRAIN_OBS_1__FLD LPDDR4__DENALI_PHY_269__PHY_VREF_TRAIN_OBS_1
+
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1_WIDTH      10U
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__REG DENALI_PHY_269
+#define LPDDR4__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_269__PHY_RDDQS_DQ_BYPASS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_270_READ_MASK                             0x01FF000FU
+#define LPDDR4__DENALI_PHY_270_WRITE_MASK                            0x01FF000FU
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1_WIDTH           4U
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_GATE_ERROR_DELAY_SELECT_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_ERROR_DELAY_SELECT_1
+
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_MASK          0x00000100U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1_WOSET                  0U
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__REG DENALI_PHY_270
+#define LPDDR4__SC_PHY_SNAP_OBS_REGS_1__FLD LPDDR4__DENALI_PHY_270__SC_PHY_SNAP_OBS_REGS_1
+
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__REG DENALI_PHY_270
+#define LPDDR4__PHY_GATE_SMPL1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_270__PHY_GATE_SMPL1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_271_READ_MASK                             0x01FF0701U
+#define LPDDR4__DENALI_PHY_271_WRITE_MASK                            0x01FF0701U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_MASK                     0x00000001U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_SHIFT                             0U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_271__PHY_LPDDR_1_WOSET                             0U
+#define LPDDR4__PHY_LPDDR_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_LPDDR_1__FLD LPDDR4__DENALI_PHY_271__PHY_LPDDR_1
+
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_MASK                 0x00000700U
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_SHIFT                         8U
+#define LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1_WIDTH                         3U
+#define LPDDR4__PHY_MEM_CLASS_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_MEM_CLASS_1__FLD LPDDR4__DENALI_PHY_271__PHY_MEM_CLASS_1
+
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1_WIDTH            9U
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__REG DENALI_PHY_271
+#define LPDDR4__PHY_GATE_SMPL2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_271__PHY_GATE_SMPL2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_272_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_272_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_MASK         0x00000003U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1_WIDTH                 2U
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__REG DENALI_PHY_272
+#define LPDDR4__ON_FLY_GATE_ADJUST_EN_1__FLD LPDDR4__DENALI_PHY_272__ON_FLY_GATE_ADJUST_EN_1
+
+#define LPDDR4__DENALI_PHY_273_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1_WIDTH                32U
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__REG DENALI_PHY_273
+#define LPDDR4__PHY_GATE_TRACKING_OBS_1__FLD LPDDR4__DENALI_PHY_273__PHY_GATE_TRACKING_OBS_1
+
+#define LPDDR4__DENALI_PHY_274_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_274_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_MASK             0x00000003U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1_WIDTH                     2U
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__REG DENALI_PHY_274
+#define LPDDR4__PHY_LP4_PST_AMBLE_1__FLD LPDDR4__DENALI_PHY_274__PHY_LP4_PST_AMBLE_1
+
+#define LPDDR4__DENALI_PHY_275_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT8_1__REG DENALI_PHY_275
+#define LPDDR4__PHY_RDLVL_PATT8_1__FLD LPDDR4__DENALI_PHY_275__PHY_RDLVL_PATT8_1
+
+#define LPDDR4__DENALI_PHY_276_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1_WIDTH                      32U
+#define LPDDR4__PHY_RDLVL_PATT9_1__REG DENALI_PHY_276
+#define LPDDR4__PHY_RDLVL_PATT9_1__FLD LPDDR4__DENALI_PHY_276__PHY_RDLVL_PATT9_1
+
+#define LPDDR4__DENALI_PHY_277_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT10_1__REG DENALI_PHY_277
+#define LPDDR4__PHY_RDLVL_PATT10_1__FLD LPDDR4__DENALI_PHY_277__PHY_RDLVL_PATT10_1
+
+#define LPDDR4__DENALI_PHY_278_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT11_1__REG DENALI_PHY_278
+#define LPDDR4__PHY_RDLVL_PATT11_1__FLD LPDDR4__DENALI_PHY_278__PHY_RDLVL_PATT11_1
+
+#define LPDDR4__DENALI_PHY_279_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT12_1__REG DENALI_PHY_279
+#define LPDDR4__PHY_RDLVL_PATT12_1__FLD LPDDR4__DENALI_PHY_279__PHY_RDLVL_PATT12_1
+
+#define LPDDR4__DENALI_PHY_280_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT13_1__REG DENALI_PHY_280
+#define LPDDR4__PHY_RDLVL_PATT13_1__FLD LPDDR4__DENALI_PHY_280__PHY_RDLVL_PATT13_1
+
+#define LPDDR4__DENALI_PHY_281_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT14_1__REG DENALI_PHY_281
+#define LPDDR4__PHY_RDLVL_PATT14_1__FLD LPDDR4__DENALI_PHY_281__PHY_RDLVL_PATT14_1
+
+#define LPDDR4__DENALI_PHY_282_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1_WIDTH                     32U
+#define LPDDR4__PHY_RDLVL_PATT15_1__REG DENALI_PHY_282
+#define LPDDR4__PHY_RDLVL_PATT15_1__FLD LPDDR4__DENALI_PHY_282__PHY_RDLVL_PATT15_1
+
+#define LPDDR4__DENALI_PHY_283_READ_MASK                             0x070F0107U
+#define LPDDR4__DENALI_PHY_283_WRITE_MASK                            0x070F0107U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_MASK     0x00000007U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1_WIDTH             3U
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_SLAVE_LOOP_CNT_UPDATE_1__FLD LPDDR4__DENALI_PHY_283__PHY_SLAVE_LOOP_CNT_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WIDTH           1U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOCLR           0U
+#define LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1_WOSET           0U
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_SW_FIFO_PTR_RST_DISABLE_1__FLD LPDDR4__DENALI_PHY_283__PHY_SW_FIFO_PTR_RST_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_MASK 0x000F0000U
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1_WIDTH        4U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_MASTER_DLY_LOCK_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_MASK       0x07000000U
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1_WIDTH               3U
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__REG DENALI_PHY_283
+#define LPDDR4__PHY_RDDQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_283__PHY_RDDQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_284_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_MASK   0x0000000FU
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1_WIDTH           4U
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_RDDQS_DQ_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_RDDQS_DQ_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_MASK         0x00000F00U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1_WIDTH                 4U
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_WR_ENC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_WR_ENC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1_WIDTH               4U
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_WR_SHIFT_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_WR_SHIFT_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1_WIDTH               4U
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__REG DENALI_PHY_284
+#define LPDDR4__PHY_FIFO_PTR_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_284__PHY_FIFO_PTR_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_285_READ_MASK                             0x3F030001U
+#define LPDDR4__DENALI_PHY_285_WRITE_MASK                            0x3F030001U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_MASK            0x00000001U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1_WOSET                    0U
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_LVL_DEBUG_MODE_1__FLD LPDDR4__DENALI_PHY_285__PHY_LVL_DEBUG_MODE_1
+
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1_WOSET                 0U
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__REG DENALI_PHY_285
+#define LPDDR4__SC_PHY_LVL_DEBUG_CONT_1__FLD LPDDR4__DENALI_PHY_285__SC_PHY_LVL_DEBUG_CONT_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_MASK                0x00030000U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1_WIDTH                        2U
+#define LPDDR4__PHY_WRLVL_ALGO_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WRLVL_ALGO_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_ALGO_1
+
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_MASK         0x3F000000U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__REG DENALI_PHY_285
+#define LPDDR4__PHY_WRLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_285__PHY_WRLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_286_READ_MASK                             0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_286_WRITE_MASK                            0x0F3FFF0FU
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_WRLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_WRLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_SHIFT                           8U
+#define LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1_WIDTH                           8U
+#define LPDDR4__PHY_DQ_MASK_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_DQ_MASK_1__FLD LPDDR4__DENALI_PHY_286__PHY_DQ_MASK_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_286
+#define LPDDR4__PHY_GTLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_286__PHY_GTLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287_READ_MASK                             0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287_WRITE_MASK                            0x1F030F3FU
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_MASK         0x0000003FU
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1_WIDTH                 6U
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_CAPTURE_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_CAPTURE_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1_WIDTH               4U
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1_WIDTH                     2U
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_OP_MODE_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_OP_MODE_1
+
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1_WIDTH         5U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__REG DENALI_PHY_287
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_287__PHY_RDLVL_RDDQS_DQ_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_288_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_288_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1_WIDTH                   8U
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_DATA_MASK_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_MASK_1
+
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_MASK        0x03FFFF00U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1_WIDTH               18U
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__REG DENALI_PHY_288
+#define LPDDR4__PHY_RDLVL_DATA_SWIZZLE_1__FLD LPDDR4__DENALI_PHY_288__PHY_RDLVL_DATA_SWIZZLE_1
+
+#define LPDDR4__DENALI_PHY_289_READ_MASK                             0x00073FFFU
+#define LPDDR4__DENALI_PHY_289_WRITE_MASK                            0x00073FFFU
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_SHIFT       0U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1_WIDTH       8U
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_CLK_JITTER_TOLERANCE_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_MASK          0x00003F00U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1_WIDTH                  6U
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_BURST_CNT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_BURST_CNT_1
+
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_MASK               0x00070000U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1_WIDTH                       3U
+#define LPDDR4__PHY_WDQLVL_PATT_1__REG DENALI_PHY_289
+#define LPDDR4__PHY_WDQLVL_PATT_1__FLD LPDDR4__DENALI_PHY_289__PHY_WDQLVL_PATT_1
+
+#define LPDDR4__DENALI_PHY_290_READ_MASK                             0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_290_WRITE_MASK                            0x0F0F07FFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_SHIFT   0U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1_WIDTH  11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_SLV_DLY_JUMP_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_MASK      0x000F0000U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1_WIDTH              4U
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_UPDT_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_UPDT_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_MASK    0x0F000000U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_SHIFT           24U
+#define LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1_WIDTH            4U
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__REG DENALI_PHY_290
+#define LPDDR4__PHY_WDQLVL_DQDM_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_290__PHY_WDQLVL_DQDM_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_291_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_PHY_291_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1_WIDTH        8U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_SELECT_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_PERIODIC_OBS_SELECT_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_MASK       0x0000FF00U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1_WIDTH               8U
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DQ_SLV_DELTA_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DQ_SLV_DELTA_1
+
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_MASK        0x000F0000U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1_WIDTH                4U
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__REG DENALI_PHY_291
+#define LPDDR4__PHY_WDQLVL_DM_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_291__PHY_WDQLVL_DM_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_MASK 0x01000000U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_SHIFT       24U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WIDTH        1U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOCLR        0U
+#define LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1_WOSET        0U
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__REG DENALI_PHY_291
+#define LPDDR4__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1__FLD LPDDR4__DENALI_PHY_291__SC_PHY_WDQLVL_CLR_PREV_RESULTS_1
+
+#define LPDDR4__DENALI_PHY_292_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_292_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_MASK        0x000001FFU
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1_WIDTH                9U
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__REG DENALI_PHY_292
+#define LPDDR4__PHY_WDQLVL_DATADM_MASK_1__FLD LPDDR4__DENALI_PHY_292__PHY_WDQLVL_DATADM_MASK_1
+
+#define LPDDR4__DENALI_PHY_293_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT0_1__REG DENALI_PHY_293
+#define LPDDR4__PHY_USER_PATT0_1__FLD LPDDR4__DENALI_PHY_293__PHY_USER_PATT0_1
+
+#define LPDDR4__DENALI_PHY_294_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT1_1__REG DENALI_PHY_294
+#define LPDDR4__PHY_USER_PATT1_1__FLD LPDDR4__DENALI_PHY_294__PHY_USER_PATT1_1
+
+#define LPDDR4__DENALI_PHY_295_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT2_1__REG DENALI_PHY_295
+#define LPDDR4__PHY_USER_PATT2_1__FLD LPDDR4__DENALI_PHY_295__PHY_USER_PATT2_1
+
+#define LPDDR4__DENALI_PHY_296_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1_WIDTH                       32U
+#define LPDDR4__PHY_USER_PATT3_1__REG DENALI_PHY_296
+#define LPDDR4__PHY_USER_PATT3_1__FLD LPDDR4__DENALI_PHY_296__PHY_USER_PATT3_1
+
+#define LPDDR4__DENALI_PHY_297_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_PHY_297_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1_WIDTH                       16U
+#define LPDDR4__PHY_USER_PATT4_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_USER_PATT4_1__FLD LPDDR4__DENALI_PHY_297__PHY_USER_PATT4_1
+
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_MASK            0x00010000U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WIDTH                    1U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WOCLR                    0U
+#define LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1_WOSET                    0U
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__REG DENALI_PHY_297
+#define LPDDR4__PHY_NTP_MULT_TRAIN_1__FLD LPDDR4__DENALI_PHY_297__PHY_NTP_MULT_TRAIN_1
+
+#define LPDDR4__DENALI_PHY_298_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_MASK       0x000003FFU
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1_WIDTH              10U
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_MASK      0x03FF0000U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1_WIDTH             10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__REG DENALI_PHY_298
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_298__PHY_NTP_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_299_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_MASK  0x000003FFU
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MIN_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MIN_1
+
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_MASK  0x03FF0000U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_SHIFT         16U
+#define LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1_WIDTH         10U
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__REG DENALI_PHY_299
+#define LPDDR4__PHY_NTP_PERIOD_THRESHOLD_MAX_1__FLD LPDDR4__DENALI_PHY_299__PHY_NTP_PERIOD_THRESHOLD_MAX_1
+
+#define LPDDR4__DENALI_PHY_300_READ_MASK                             0x00FF0001U
+#define LPDDR4__DENALI_PHY_300_WRITE_MASK                            0x00FF0001U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_MASK  0x00000001U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WIDTH          1U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WOCLR          0U
+#define LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1_WOSET          0U
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_CALVL_VREF_DRIVING_SLICE_1__FLD LPDDR4__DENALI_PHY_300__PHY_CALVL_VREF_DRIVING_SLICE_1
+
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_MASK           0x00003F00U
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1_WIDTH                   6U
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__REG DENALI_PHY_300
+#define LPDDR4__SC_PHY_MANUAL_CLEAR_1__FLD LPDDR4__DENALI_PHY_300__SC_PHY_MANUAL_CLEAR_1
+
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_MASK              0x00FF0000U
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1_WIDTH                      8U
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__REG DENALI_PHY_300
+#define LPDDR4__PHY_FIFO_PTR_OBS_1__FLD LPDDR4__DENALI_PHY_300__PHY_FIFO_PTR_OBS_1
+
+#define LPDDR4__DENALI_PHY_301_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1_WIDTH                  32U
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__REG DENALI_PHY_301
+#define LPDDR4__PHY_LPBK_RESULT_OBS_1__FLD LPDDR4__DENALI_PHY_301__PHY_LPBK_RESULT_OBS_1
+
+#define LPDDR4__DENALI_PHY_302_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_302_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_MASK      0x0000FFFFU
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1_WIDTH             16U
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_LPBK_ERROR_COUNT_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_LPBK_ERROR_COUNT_OBS_1
+
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_MASK       0x07FF0000U
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1_WIDTH              11U
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__REG DENALI_PHY_302
+#define LPDDR4__PHY_MASTER_DLY_LOCK_OBS_1__FLD LPDDR4__DENALI_PHY_302__PHY_MASTER_DLY_LOCK_OBS_1
+
+#define LPDDR4__DENALI_PHY_303_READ_MASK                             0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_303_WRITE_MASK                            0xFFFF7F7FU
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1_WIDTH              7U
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQ_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQ_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x00007F00U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH        7U
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_MASK       0x00FF0000U
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1_WIDTH               8U
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_MEAS_DLY_STEP_VALUE_1__FLD LPDDR4__DENALI_PHY_303__PHY_MEAS_DLY_STEP_VALUE_1
+
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_MASK 0xFF000000U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 24U
+#define LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_303
+#define LPDDR4__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_303__PHY_RDDQS_DQ_RISE_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304_READ_MASK                             0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_304_WRITE_MASK                            0x7F07FFFFU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_SHIFT 0U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1_WIDTH 8U
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_DQ_FALL_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_MASK 0x0007FF00U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1_WIDTH       11U
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_RDDQS_GATE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_MASK 0x7F000000U
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_SHIFT       24U
+#define LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1_WIDTH        7U
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_304
+#define LPDDR4__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_304__PHY_WRDQS_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_305_WRITE_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1_WIDTH         8U
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WRDQ_BASE_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_MASK  0x0000FF00U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_SHIFT          8U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1_WIDTH          8U
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WR_ADDER_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1_WIDTH                      3U
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__REG DENALI_PHY_305
+#define LPDDR4__PHY_WR_SHIFT_OBS_1__FLD LPDDR4__DENALI_PHY_305__PHY_WR_SHIFT_OBS_1
+
+#define LPDDR4__DENALI_PHY_306_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_306_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_MASK     0x000003FFU
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1_WIDTH            10U
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_306
+#define LPDDR4__PHY_WRLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_306__PHY_WRLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_307_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_MASK          0x001FFFFFU
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1_WIDTH                 21U
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__REG DENALI_PHY_307
+#define LPDDR4__PHY_WRLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_307__PHY_WRLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_308_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_308_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL1_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1_WIDTH       10U
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__REG DENALI_PHY_308
+#define LPDDR4__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1__FLD LPDDR4__DENALI_PHY_308__PHY_GATE_SMPL2_SLV_DLY_ENC_OBS_1
+
+#define LPDDR4__DENALI_PHY_309_READ_MASK                             0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_309_WRITE_MASK                            0x3FFF3FFFU
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_MASK     0x00003FFFU
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GTLVL_HARD0_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD0_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_MASK     0x3FFF0000U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1_WIDTH            14U
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__REG DENALI_PHY_309
+#define LPDDR4__PHY_GTLVL_HARD1_DELAY_OBS_1__FLD LPDDR4__DENALI_PHY_309__PHY_GTLVL_HARD1_DELAY_OBS_1
+
+#define LPDDR4__DENALI_PHY_310_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_MASK          0x0003FFFFU
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1_WIDTH                 18U
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__REG DENALI_PHY_310
+#define LPDDR4__PHY_GTLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_310__PHY_GTLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_311_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1_WIDTH        10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__REG DENALI_PHY_311
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_311__PHY_RDLVL_RDDQS_DQ_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_312_READ_MASK                             0x00000003U
+#define LPDDR4__DENALI_PHY_312_WRITE_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_MASK 0x00000003U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_SHIFT    0U
+#define LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1_WIDTH    2U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__REG DENALI_PHY_312
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1__FLD LPDDR4__DENALI_PHY_312__PHY_RDLVL_RDDQS_DQ_NUM_WINDOWS_OBS_1
+
+#define LPDDR4__DENALI_PHY_313_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1_WIDTH                 32U
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__REG DENALI_PHY_313
+#define LPDDR4__PHY_RDLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_313__PHY_RDLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_314_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_314_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_MASK    0x000007FFU
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_WDQLVL_DQDM_LE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_LE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_MASK    0x07FF0000U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1_WIDTH           11U
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__REG DENALI_PHY_314
+#define LPDDR4__PHY_WDQLVL_DQDM_TE_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_314__PHY_WDQLVL_DQDM_TE_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_315_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1_WIDTH                32U
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__REG DENALI_PHY_315
+#define LPDDR4__PHY_WDQLVL_STATUS_OBS_1__FLD LPDDR4__DENALI_PHY_315__PHY_WDQLVL_STATUS_OBS_1
+
+#define LPDDR4__DENALI_PHY_316_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1_WIDTH              32U
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__REG DENALI_PHY_316
+#define LPDDR4__PHY_WDQLVL_PERIODIC_OBS_1__FLD LPDDR4__DENALI_PHY_316__PHY_WDQLVL_PERIODIC_OBS_1
+
+#define LPDDR4__DENALI_PHY_317_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_MASK                  0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1_WIDTH                         31U
+#define LPDDR4__PHY_DDL_MODE_1__REG DENALI_PHY_317
+#define LPDDR4__PHY_DDL_MODE_1__FLD LPDDR4__DENALI_PHY_317__PHY_DDL_MODE_1
+
+#define LPDDR4__DENALI_PHY_318_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_PHY_318_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_MASK                  0x0000003FU
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1_WIDTH                          6U
+#define LPDDR4__PHY_DDL_MASK_1__REG DENALI_PHY_318
+#define LPDDR4__PHY_DDL_MASK_1__FLD LPDDR4__DENALI_PHY_318__PHY_DDL_MASK_1
+
+#define LPDDR4__DENALI_PHY_319_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1_WIDTH                     32U
+#define LPDDR4__PHY_DDL_TEST_OBS_1__REG DENALI_PHY_319
+#define LPDDR4__PHY_DDL_TEST_OBS_1__FLD LPDDR4__DENALI_PHY_319__PHY_DDL_TEST_OBS_1
+
+#define LPDDR4__DENALI_PHY_320_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_MASK     0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1_WIDTH            32U
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__REG DENALI_PHY_320
+#define LPDDR4__PHY_DDL_TEST_MSTR_DLY_OBS_1__FLD LPDDR4__DENALI_PHY_320__PHY_DDL_TEST_MSTR_DLY_OBS_1
+
+#define LPDDR4__DENALI_PHY_321_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_321_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1_WIDTH           8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_321__PHY_DDL_TRACK_UPD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_MASK        0x00000100U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1_WOSET                0U
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_LP4_WDQS_OE_EXTEND_1__FLD LPDDR4__DENALI_PHY_321__PHY_LP4_WDQS_OE_EXTEND_1
+
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ0_1__REG DENALI_PHY_321
+#define LPDDR4__PHY_RX_CAL_DQ0_1__FLD LPDDR4__DENALI_PHY_321__PHY_RX_CAL_DQ0_1
+
+#define LPDDR4__DENALI_PHY_322_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_322_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ1_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_RX_CAL_DQ1_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ1_1
+
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ2_1__REG DENALI_PHY_322
+#define LPDDR4__PHY_RX_CAL_DQ2_1__FLD LPDDR4__DENALI_PHY_322__PHY_RX_CAL_DQ2_1
+
+#define LPDDR4__DENALI_PHY_323_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ3_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ3_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ3_1
+
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ4_1__REG DENALI_PHY_323
+#define LPDDR4__PHY_RX_CAL_DQ4_1__FLD LPDDR4__DENALI_PHY_323__PHY_RX_CAL_DQ4_1
+
+#define LPDDR4__DENALI_PHY_324_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ5_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ5_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ5_1
+
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_MASK                0x01FF0000U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ6_1__REG DENALI_PHY_324
+#define LPDDR4__PHY_RX_CAL_DQ6_1__FLD LPDDR4__DENALI_PHY_324__PHY_RX_CAL_DQ6_1
+
+#define LPDDR4__DENALI_PHY_325_READ_MASK                             0x000001FFU
+#define LPDDR4__DENALI_PHY_325_WRITE_MASK                            0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQ7_1__REG DENALI_PHY_325
+#define LPDDR4__PHY_RX_CAL_DQ7_1__FLD LPDDR4__DENALI_PHY_325__PHY_RX_CAL_DQ7_1
+
+#define LPDDR4__DENALI_PHY_326_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_MASK                 0x0003FFFFU
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1_WIDTH                        18U
+#define LPDDR4__PHY_RX_CAL_DM_1__REG DENALI_PHY_326
+#define LPDDR4__PHY_RX_CAL_DM_1__FLD LPDDR4__DENALI_PHY_326__PHY_RX_CAL_DM_1
+
+#define LPDDR4__DENALI_PHY_327_READ_MASK                             0x01FF01FFU
+#define LPDDR4__DENALI_PHY_327_WRITE_MASK                            0x01FF01FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_MASK                0x000001FFU
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1_WIDTH                        9U
+#define LPDDR4__PHY_RX_CAL_DQS_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_DQS_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_DQS_1
+
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_MASK               0x01FF0000U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1_WIDTH                       9U
+#define LPDDR4__PHY_RX_CAL_FDBK_1__REG DENALI_PHY_327
+#define LPDDR4__PHY_RX_CAL_FDBK_1__FLD LPDDR4__DENALI_PHY_327__PHY_RX_CAL_FDBK_1
+
+#define LPDDR4__DENALI_PHY_328_READ_MASK                             0x071F07FFU
+#define LPDDR4__DENALI_PHY_328_WRITE_MASK                            0x071F07FFU
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_MASK            0x000007FFU
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1_WIDTH                   11U
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_PAD_RX_BIAS_EN_1__FLD LPDDR4__DENALI_PHY_328__PHY_PAD_RX_BIAS_EN_1
+
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_SHIFT               16U
+#define LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1_WIDTH                5U
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_STATIC_TOG_DISABLE_1__FLD LPDDR4__DENALI_PHY_328__PHY_STATIC_TOG_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_MASK             0x07000000U
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1_WIDTH                     3U
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__REG DENALI_PHY_328
+#define LPDDR4__PHY_FDBK_PWR_CTRL_1__FLD LPDDR4__DENALI_PHY_328__PHY_FDBK_PWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_329_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_PHY_329_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WIDTH         1U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOCLR         0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1_WOSET         0U
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_SLV_DLY_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_SLV_DLY_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_MASK       0x00000100U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WIDTH               1U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WOCLR               0U
+#define LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1_WOSET               0U
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_RDPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_RDPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WIDTH       1U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOCLR       0U
+#define LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1_WOSET       0U
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_DCC_RXCAL_CTRL_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_MASK     0x01000000U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_SHIFT            24U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WIDTH             1U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WOCLR             0U
+#define LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1_WOSET             0U
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__REG DENALI_PHY_329
+#define LPDDR4__PHY_SLICE_PWR_RDC_DISABLE_1__FLD LPDDR4__DENALI_PHY_329__PHY_SLICE_PWR_RDC_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_330_READ_MASK                             0x07FFFF07U
+#define LPDDR4__DENALI_PHY_330_WRITE_MASK                            0x07FFFF07U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_MASK            0x00000007U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1_WIDTH                    3U
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQ_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_MASK            0x00FFFF00U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1_WIDTH                   16U
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQ_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQ_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_MASK           0x07000000U
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1_WIDTH                   3U
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__REG DENALI_PHY_330
+#define LPDDR4__PHY_DQS_TSEL_ENABLE_1__FLD LPDDR4__DENALI_PHY_330__PHY_DQS_TSEL_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_331_READ_MASK                             0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_331_WRITE_MASK                            0x7F03FFFFU
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_MASK           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1_WIDTH                  16U
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_DQS_TSEL_SELECT_1__FLD LPDDR4__DENALI_PHY_331__PHY_DQS_TSEL_SELECT_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1_WIDTH                  2U
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_TWO_CYC_PREAMBLE_1__FLD LPDDR4__DENALI_PHY_331__PHY_TWO_CYC_PREAMBLE_1
+
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_MASK  0x7F000000U
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_SHIFT         24U
+#define LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1_WIDTH          7U
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__REG DENALI_PHY_331
+#define LPDDR4__PHY_VREF_INITIAL_START_POINT_1__FLD LPDDR4__DENALI_PHY_331__PHY_VREF_INITIAL_START_POINT_1
+
+#define LPDDR4__DENALI_PHY_332_READ_MASK                             0xFF01037FU
+#define LPDDR4__DENALI_PHY_332_WRITE_MASK                            0xFF01037FU
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_MASK   0x0000007FU
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1_WIDTH           7U
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_VREF_INITIAL_STOP_POINT_1__FLD LPDDR4__DENALI_PHY_332__PHY_VREF_INITIAL_STOP_POINT_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_MASK        0x00000300U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1_WIDTH                2U
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_VREF_TRAINING_CTRL_1__FLD LPDDR4__DENALI_PHY_332__PHY_VREF_TRAINING_CTRL_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_MASK              0x00010000U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1_WOSET                      0U
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_NTP_TRAIN_EN_1__FLD LPDDR4__DENALI_PHY_332__PHY_NTP_TRAIN_EN_1
+
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1_WIDTH                 8U
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__REG DENALI_PHY_332
+#define LPDDR4__PHY_NTP_WDQ_STEP_SIZE_1__FLD LPDDR4__DENALI_PHY_332__PHY_NTP_WDQ_STEP_SIZE_1
+
+#define LPDDR4__DENALI_PHY_333_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_333_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_MASK             0x000007FFU
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1_WIDTH                    11U
+#define LPDDR4__PHY_NTP_WDQ_START_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_NTP_WDQ_START_1__FLD LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_START_1
+
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_MASK              0x07FF0000U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1_WIDTH                     11U
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__REG DENALI_PHY_333
+#define LPDDR4__PHY_NTP_WDQ_STOP_1__FLD LPDDR4__DENALI_PHY_333__PHY_NTP_WDQ_STOP_1
+
+#define LPDDR4__DENALI_PHY_334_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_PHY_334_WRITE_MASK                            0x0103FFFFU
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_MASK            0x000000FFU
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1_WIDTH                    8U
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_NTP_WDQ_BIT_EN_1__FLD LPDDR4__DENALI_PHY_334__PHY_NTP_WDQ_BIT_EN_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_MASK            0x0003FF00U
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1_WIDTH                   10U
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_WDQLVL_DVW_MIN_1__FLD LPDDR4__DENALI_PHY_334__PHY_WDQLVL_DVW_MIN_1
+
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_MASK      0x01000000U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WIDTH              1U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOCLR              0U
+#define LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1_WOSET              0U
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__REG DENALI_PHY_334
+#define LPDDR4__PHY_SW_WDQLVL_DVW_MIN_EN_1__FLD LPDDR4__DENALI_PHY_334__PHY_SW_WDQLVL_DVW_MIN_EN_1
+
+#define LPDDR4__DENALI_PHY_335_READ_MASK                             0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_335_WRITE_MASK                            0x1F1F0F3FU
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_MASK   0x0000003FU
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1_WIDTH           6U
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_WDQLVL_PER_START_OFFSET_1__FLD LPDDR4__DENALI_PHY_335__PHY_WDQLVL_PER_START_OFFSET_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1_WIDTH                       4U
+#define LPDDR4__PHY_FAST_LVL_EN_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_FAST_LVL_EN_1__FLD LPDDR4__DENALI_PHY_335__PHY_FAST_LVL_EN_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_MASK                0x001F0000U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1_WIDTH                        5U
+#define LPDDR4__PHY_PAD_TX_DCD_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_PAD_TX_DCD_1__FLD LPDDR4__DENALI_PHY_335__PHY_PAD_TX_DCD_1
+
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__REG DENALI_PHY_335
+#define LPDDR4__PHY_PAD_RX_DCD_0_1__FLD LPDDR4__DENALI_PHY_335__PHY_PAD_RX_DCD_0_1
+
+#define LPDDR4__DENALI_PHY_336_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_336_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_1_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_1_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_2_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_2_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_3_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_3_1
+
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_MASK              0x1F000000U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__REG DENALI_PHY_336
+#define LPDDR4__PHY_PAD_RX_DCD_4_1__FLD LPDDR4__DENALI_PHY_336__PHY_PAD_RX_DCD_4_1
+
+#define LPDDR4__DENALI_PHY_337_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_337_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_MASK              0x0000001FU
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_5_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_5_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_MASK              0x00001F00U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_6_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_6_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_MASK              0x001F0000U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1_WIDTH                      5U
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_RX_DCD_7_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_RX_DCD_7_1
+
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_MASK             0x1F000000U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1_WIDTH                     5U
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__REG DENALI_PHY_337
+#define LPDDR4__PHY_PAD_DM_RX_DCD_1__FLD LPDDR4__DENALI_PHY_337__PHY_PAD_DM_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338_READ_MASK                             0x007F1F1FU
+#define LPDDR4__DENALI_PHY_338_WRITE_MASK                            0x007F1F1FU
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1_WIDTH                    5U
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_DQS_RX_DCD_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_DQS_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1_WIDTH                   5U
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_FDBK_RX_DCD_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_FDBK_RX_DCD_1
+
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_MASK         0x007F0000U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1_WIDTH                 7U
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__REG DENALI_PHY_338
+#define LPDDR4__PHY_PAD_DSLICE_IO_CFG_1__FLD LPDDR4__DENALI_PHY_338__PHY_PAD_DSLICE_IO_CFG_1
+
+#define LPDDR4__DENALI_PHY_339_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_339_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_RDDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_339__PHY_RDDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__REG DENALI_PHY_339
+#define LPDDR4__PHY_RDDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_339__PHY_RDDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_340_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_340_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_RDDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_340__PHY_RDDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__REG DENALI_PHY_340
+#define LPDDR4__PHY_RDDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_340__PHY_RDDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_341_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_341_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_RDDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_341__PHY_RDDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__REG DENALI_PHY_341
+#define LPDDR4__PHY_RDDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_341__PHY_RDDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_342_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_342_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_MASK         0x000003FFU
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_RDDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_342__PHY_RDDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_MASK         0x03FF0000U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1_WIDTH                10U
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__REG DENALI_PHY_342
+#define LPDDR4__PHY_RDDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_342__PHY_RDDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_343_READ_MASK                             0x1F0703FFU
+#define LPDDR4__DENALI_PHY_343_WRITE_MASK                            0x1F0703FFU
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_MASK          0x000003FFU
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1_WIDTH                 10U
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RDDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_343__PHY_RDDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_MASK           0x00070000U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1_WIDTH                   3U
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RX_PCLK_CLK_SEL_1__FLD LPDDR4__DENALI_PHY_343__PHY_RX_PCLK_CLK_SEL_1
+
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1_WIDTH                    5U
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__REG DENALI_PHY_343
+#define LPDDR4__PHY_RX_CAL_ALL_DLY_1__FLD LPDDR4__DENALI_PHY_343__PHY_RX_CAL_ALL_DLY_1
+
+#define LPDDR4__DENALI_PHY_344_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_344_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1_WIDTH                      8U
+#define LPDDR4__PHY_DQ_OE_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_MASK         0x0000FF00U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1_WIDTH                 8U
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQ_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQ_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_MASK             0xFF000000U
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1_WIDTH                     8U
+#define LPDDR4__PHY_DQS_OE_TIMING_1__REG DENALI_PHY_344
+#define LPDDR4__PHY_DQS_OE_TIMING_1__FLD LPDDR4__DENALI_PHY_344__PHY_DQS_OE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_345_WRITE_MASK                            0xFFFFFF0FU
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_MASK       0x0000000FU
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1_WIDTH               4U
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_IO_PAD_DELAY_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_IO_PAD_DELAY_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_MASK        0x0000FF00U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_TSEL_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_MASK          0x00FF0000U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1_WIDTH                  8U
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_OE_RD_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_OE_RD_TIMING_1
+
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_MASK        0xFF000000U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_SHIFT               24U
+#define LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1_WIDTH                8U
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__REG DENALI_PHY_345
+#define LPDDR4__PHY_DQS_TSEL_WR_TIMING_1__FLD LPDDR4__DENALI_PHY_345__PHY_DQS_TSEL_WR_TIMING_1
+
+#define LPDDR4__DENALI_PHY_346_READ_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_346_WRITE_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1_WIDTH                16U
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_VREF_SETTING_TIME_1__FLD LPDDR4__DENALI_PHY_346__PHY_VREF_SETTING_TIME_1
+
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_MASK          0x0FFF0000U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1_WIDTH                 12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__REG DENALI_PHY_346
+#define LPDDR4__PHY_PAD_VREF_CTRL_DQ_1__FLD LPDDR4__DENALI_PHY_346__PHY_PAD_VREF_CTRL_DQ_1
+
+#define LPDDR4__DENALI_PHY_347_READ_MASK                             0x0303FFFFU
+#define LPDDR4__DENALI_PHY_347_WRITE_MASK                            0x0303FFFFU
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_MASK              0x000000FFU
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1_WIDTH                      8U
+#define LPDDR4__PHY_DQ_IE_TIMING_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_DQ_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_347__PHY_DQ_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_MASK             0x0000FF00U
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1_WIDTH                     8U
+#define LPDDR4__PHY_DQS_IE_TIMING_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_DQS_IE_TIMING_1__FLD LPDDR4__DENALI_PHY_347__PHY_DQS_IE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_MASK          0x00030000U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1_WIDTH                  2U
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_RDDATA_EN_IE_DLY_1__FLD LPDDR4__DENALI_PHY_347__PHY_RDDATA_EN_IE_DLY_1
+
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_MASK                   0x03000000U
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_SHIFT                          24U
+#define LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1_WIDTH                           2U
+#define LPDDR4__PHY_IE_MODE_1__REG DENALI_PHY_347
+#define LPDDR4__PHY_IE_MODE_1__FLD LPDDR4__DENALI_PHY_347__PHY_IE_MODE_1
+
+#define LPDDR4__DENALI_PHY_348_READ_MASK                             0x1F1F0103U
+#define LPDDR4__DENALI_PHY_348_WRITE_MASK                            0x1F1F0103U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_MASK                  0x00000003U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1_WIDTH                          2U
+#define LPDDR4__PHY_DBI_MODE_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_DBI_MODE_1__FLD LPDDR4__DENALI_PHY_348__PHY_DBI_MODE_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_MASK              0x00000100U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_SHIFT                      8U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1_WOSET                      0U
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_IE_ON_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_IE_ON_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_MASK      0x001F0000U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_SHIFT             16U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1_WIDTH              5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_SHIFT        24U
+#define LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1_WIDTH         5U
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_348
+#define LPDDR4__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_348__PHY_WDQLVL_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_349_READ_MASK                             0x000F1F1FU
+#define LPDDR4__DENALI_PHY_349_WRITE_MASK                            0x000F1F1FU
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_MASK        0x0000001FU
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1_WIDTH                5U
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_RDDATA_EN_TSEL_DLY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_TSEL_DLY_1
+
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_MASK          0x00001F00U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1_WIDTH                  5U
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_RDDATA_EN_OE_DLY_1__FLD LPDDR4__DENALI_PHY_349__PHY_RDDATA_EN_OE_DLY_1
+
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1_WIDTH                    4U
+#define LPDDR4__PHY_SW_MASTER_MODE_1__REG DENALI_PHY_349
+#define LPDDR4__PHY_SW_MASTER_MODE_1__FLD LPDDR4__DENALI_PHY_349__PHY_SW_MASTER_MODE_1
+
+#define LPDDR4__DENALI_PHY_350_READ_MASK                             0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_350_WRITE_MASK                            0xFF3F07FFU
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1_WIDTH               11U
+#define LPDDR4__PHY_MASTER_DELAY_START_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_START_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_START_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_MASK         0x003F0000U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1_WIDTH                 6U
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_STEP_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_STEP_1
+
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_MASK         0xFF000000U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_SHIFT                24U
+#define LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1_WIDTH                 8U
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__REG DENALI_PHY_350
+#define LPDDR4__PHY_MASTER_DELAY_WAIT_1__FLD LPDDR4__DENALI_PHY_350__PHY_MASTER_DELAY_WAIT_1
+
+#define LPDDR4__DENALI_PHY_351_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_351_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_MASK 0x000000FFU
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1_WIDTH         8U
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_MASTER_DELAY_HALF_MEASURE_1__FLD LPDDR4__DENALI_PHY_351__PHY_MASTER_DELAY_HALF_MEASURE_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_MASK               0x00000F00U
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_SHIFT                       8U
+#define LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1_WIDTH                       4U
+#define LPDDR4__PHY_RPTR_UPDATE_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_RPTR_UPDATE_1__FLD LPDDR4__DENALI_PHY_351__PHY_RPTR_UPDATE_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_MASK            0x00FF0000U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1_WIDTH                    8U
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_WRLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_SHIFT              24U
+#define LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__REG DENALI_PHY_351
+#define LPDDR4__PHY_WRLVL_DLY_FINE_STEP_1__FLD LPDDR4__DENALI_PHY_351__PHY_WRLVL_DLY_FINE_STEP_1
+
+#define LPDDR4__DENALI_PHY_352_READ_MASK                             0x001F0F3FU
+#define LPDDR4__DENALI_PHY_352_WRITE_MASK                            0x001F0F3FU
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_MASK       0x0000003FU
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1_WIDTH               6U
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_WRLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_352__PHY_WRLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1_WIDTH                    4U
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_GTLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_352__PHY_GTLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_MASK       0x001F0000U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1_WIDTH               5U
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__REG DENALI_PHY_352
+#define LPDDR4__PHY_GTLVL_RESP_WAIT_CNT_1__FLD LPDDR4__DENALI_PHY_352__PHY_GTLVL_RESP_WAIT_CNT_1
+
+#define LPDDR4__DENALI_PHY_353_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_353_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1_WIDTH                  10U
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_GTLVL_BACK_STEP_1__FLD LPDDR4__DENALI_PHY_353__PHY_GTLVL_BACK_STEP_1
+
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_MASK          0x03FF0000U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1_WIDTH                 10U
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__REG DENALI_PHY_353
+#define LPDDR4__PHY_GTLVL_FINAL_STEP_1__FLD LPDDR4__DENALI_PHY_353__PHY_GTLVL_FINAL_STEP_1
+
+#define LPDDR4__DENALI_PHY_354_READ_MASK                             0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_354_WRITE_MASK                            0x01FF0FFFU
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1_WIDTH                   8U
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_SHIFT               8U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1_WIDTH               4U
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_QTR_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_QTR_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_MASK    0x01FF0000U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1_WIDTH            9U
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__REG DENALI_PHY_354
+#define LPDDR4__PHY_WDQLVL_DM_SEARCH_RANGE_1__FLD LPDDR4__DENALI_PHY_354__PHY_WDQLVL_DM_SEARCH_RANGE_1
+
+#define LPDDR4__DENALI_PHY_355_READ_MASK                             0x00000F01U
+#define LPDDR4__DENALI_PHY_355_WRITE_MASK                            0x00000F01U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_SHIFT                0U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WIDTH                1U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WOCLR                0U
+#define LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1_WOSET                0U
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_TOGGLE_PRE_SUPPORT_1__FLD LPDDR4__DENALI_PHY_355__PHY_TOGGLE_PRE_SUPPORT_1
+
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1_WIDTH                    4U
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__REG DENALI_PHY_355
+#define LPDDR4__PHY_RDLVL_DLY_STEP_1__FLD LPDDR4__DENALI_PHY_355__PHY_RDLVL_DLY_STEP_1
+
+#define LPDDR4__DENALI_PHY_356_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_356_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_MASK            0x000003FFU
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1_WIDTH                   10U
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__REG DENALI_PHY_356
+#define LPDDR4__PHY_RDLVL_MAX_EDGE_1__FLD LPDDR4__DENALI_PHY_356__PHY_RDLVL_MAX_EDGE_1
+
+#define LPDDR4__DENALI_PHY_357_READ_MASK                             0x7F7F0703U
+#define LPDDR4__DENALI_PHY_357_WRITE_MASK                            0x7F7F0703U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_MASK       0x00000003U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_SHIFT               0U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1_WIDTH               2U
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRPATH_GATE_DISABLE_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_DISABLE_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1_WIDTH                3U
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WRPATH_GATE_TIMING_1__FLD LPDDR4__DENALI_PHY_357__PHY_WRPATH_GATE_TIMING_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_MASK             0x007F0000U
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1_WIDTH                     7U
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_WDQ_OSC_DELTA_1__FLD LPDDR4__DENALI_PHY_357__PHY_WDQ_OSC_DELTA_1
+
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_MASK      0x7F000000U
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_SHIFT             24U
+#define LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1_WIDTH              7U
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__REG DENALI_PHY_357
+#define LPDDR4__PHY_MEAS_DLY_STEP_ENABLE_1__FLD LPDDR4__DENALI_PHY_357__PHY_MEAS_DLY_STEP_ENABLE_1
+
+#define LPDDR4__DENALI_PHY_358_READ_MASK                             0x0000001FU
+#define LPDDR4__DENALI_PHY_358_WRITE_MASK                            0x0000001FU
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_MASK             0x0000001FU
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1_WIDTH                     5U
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__REG DENALI_PHY_358
+#define LPDDR4__PHY_RDDATA_EN_DLY_1__FLD LPDDR4__DENALI_PHY_358__PHY_RDDATA_EN_DLY_1
+
+#define LPDDR4__DENALI_PHY_359_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1_WIDTH                   32U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__REG DENALI_PHY_359
+#define LPDDR4__PHY_DQ_DM_SWIZZLE0_1__FLD LPDDR4__DENALI_PHY_359__PHY_DQ_DM_SWIZZLE0_1
+
+#define LPDDR4__DENALI_PHY_360_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_PHY_360_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1_WIDTH                    4U
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__REG DENALI_PHY_360
+#define LPDDR4__PHY_DQ_DM_SWIZZLE1_1__FLD LPDDR4__DENALI_PHY_360__PHY_DQ_DM_SWIZZLE1_1
+
+#define LPDDR4__DENALI_PHY_361_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_361_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_CLK_WRDQ0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__REG DENALI_PHY_361
+#define LPDDR4__PHY_CLK_WRDQ1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_361__PHY_CLK_WRDQ1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_362_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_362_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_CLK_WRDQ2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__REG DENALI_PHY_362
+#define LPDDR4__PHY_CLK_WRDQ3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_362__PHY_CLK_WRDQ3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_363_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_363_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_CLK_WRDQ4_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ4_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__REG DENALI_PHY_363
+#define LPDDR4__PHY_CLK_WRDQ5_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_363__PHY_CLK_WRDQ5_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_364_READ_MASK                             0x07FF07FFU
+#define LPDDR4__DENALI_PHY_364_WRITE_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_SHIFT             0U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_CLK_WRDQ6_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ6_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_MASK     0x07FF0000U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1_WIDTH            11U
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__REG DENALI_PHY_364
+#define LPDDR4__PHY_CLK_WRDQ7_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_364__PHY_CLK_WRDQ7_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_365_READ_MASK                             0x03FF07FFU
+#define LPDDR4__DENALI_PHY_365_WRITE_MASK                            0x03FF07FFU
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_MASK      0x000007FFU
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1_WIDTH             11U
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_CLK_WRDM_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_365__PHY_CLK_WRDM_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_MASK     0x03FF0000U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_SHIFT            16U
+#define LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1_WIDTH            10U
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__REG DENALI_PHY_365
+#define LPDDR4__PHY_CLK_WRDQS_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_365__PHY_CLK_WRDQS_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_366_READ_MASK                             0x0003FF03U
+#define LPDDR4__DENALI_PHY_366_WRITE_MASK                            0x0003FF03U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_MASK    0x00000003U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_SHIFT            0U
+#define LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1_WIDTH            2U
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_WRLVL_THRESHOLD_ADJUST_1__FLD LPDDR4__DENALI_PHY_366__PHY_WRLVL_THRESHOLD_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_MASK 0x0003FF00U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_SHIFT        8U
+#define LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__REG DENALI_PHY_366
+#define LPDDR4__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_366__PHY_RDDQS_DQ0_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_367_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_367_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ0_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__REG DENALI_PHY_367
+#define LPDDR4__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_367__PHY_RDDQS_DQ1_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_368_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_368_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ1_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__REG DENALI_PHY_368
+#define LPDDR4__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_368__PHY_RDDQS_DQ2_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_369_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_369_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ2_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__REG DENALI_PHY_369
+#define LPDDR4__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_369__PHY_RDDQS_DQ3_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_370_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ3_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__REG DENALI_PHY_370
+#define LPDDR4__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_370__PHY_RDDQS_DQ4_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_371_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ4_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__REG DENALI_PHY_371
+#define LPDDR4__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_371__PHY_RDDQS_DQ5_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_372_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ5_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__REG DENALI_PHY_372
+#define LPDDR4__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_372__PHY_RDDQS_DQ6_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_373_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ6_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__REG DENALI_PHY_373
+#define LPDDR4__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_373__PHY_RDDQS_DQ7_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_374_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1_WIDTH       10U
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DQ7_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__REG DENALI_PHY_374
+#define LPDDR4__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_374__PHY_RDDQS_DM_RISE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1_WIDTH        10U
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_DM_FALL_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_MASK    0x03FF0000U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1_WIDTH           10U
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__REG DENALI_PHY_375
+#define LPDDR4__PHY_RDDQS_GATE_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_375__PHY_RDDQS_GATE_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_376_READ_MASK                             0x03FF070FU
+#define LPDDR4__DENALI_PHY_376_WRITE_MASK                            0x03FF070FU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_MASK      0x0000000FU
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_SHIFT              0U
+#define LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1_WIDTH              4U
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_RDDQS_LATENCY_ADJUST_1__FLD LPDDR4__DENALI_PHY_376__PHY_RDDQS_LATENCY_ADJUST_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_MASK        0x00000700U
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_SHIFT                8U
+#define LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1_WIDTH                3U
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_WRITE_PATH_LAT_ADD_1__FLD LPDDR4__DENALI_PHY_376__PHY_WRITE_PATH_LAT_ADD_1
+
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_MASK 0x03FF0000U
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_SHIFT      16U
+#define LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1_WIDTH      10U
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__REG DENALI_PHY_376
+#define LPDDR4__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_376__PHY_WRLVL_DELAY_EARLY_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_377_READ_MASK                             0x000103FFU
+#define LPDDR4__DENALI_PHY_377_WRITE_MASK                            0x000103FFU
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1_WIDTH     10U
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_DELAY_PERIOD_THRESHOLD_1
+
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_MASK    0x00010000U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_SHIFT           16U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WIDTH            1U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOCLR            0U
+#define LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1_WOSET            0U
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__REG DENALI_PHY_377
+#define LPDDR4__PHY_WRLVL_EARLY_FORCE_ZERO_1__FLD LPDDR4__DENALI_PHY_377__PHY_WRLVL_EARLY_FORCE_ZERO_1
+
+#define LPDDR4__DENALI_PHY_378_READ_MASK                             0x000F03FFU
+#define LPDDR4__DENALI_PHY_378_WRITE_MASK                            0x000F03FFU
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1_WIDTH        10U
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_GTLVL_RDDQS_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_378__PHY_GTLVL_RDDQS_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_MASK       0x000F0000U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_SHIFT              16U
+#define LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1_WIDTH               4U
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__REG DENALI_PHY_378
+#define LPDDR4__PHY_GTLVL_LAT_ADJ_START_1__FLD LPDDR4__DENALI_PHY_378__PHY_GTLVL_LAT_ADJ_START_1
+
+#define LPDDR4__DENALI_PHY_379_READ_MASK                             0x010F07FFU
+#define LPDDR4__DENALI_PHY_379_WRITE_MASK                            0x010F07FFU
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_MASK 0x000007FFU
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_SHIFT         0U
+#define LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1_WIDTH        11U
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_WDQLVL_DQDM_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_379__PHY_WDQLVL_DQDM_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_MASK           0x000F0000U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1_WIDTH                   4U
+#define LPDDR4__PHY_NTP_WRLAT_START_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_NTP_WRLAT_START_1__FLD LPDDR4__DENALI_PHY_379__PHY_NTP_WRLAT_START_1
+
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_MASK                  0x01000000U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1_WOSET                          0U
+#define LPDDR4__PHY_NTP_PASS_1__REG DENALI_PHY_379
+#define LPDDR4__PHY_NTP_PASS_1__FLD LPDDR4__DENALI_PHY_379__PHY_NTP_PASS_1
+
+#define LPDDR4__DENALI_PHY_380_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_PHY_380_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_MASK 0x000003FFU
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_SHIFT      0U
+#define LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1_WIDTH     10U
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__REG DENALI_PHY_380
+#define LPDDR4__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1__FLD LPDDR4__DENALI_PHY_380__PHY_RDLVL_RDDQS_DQ_SLV_DLY_START_1
+
+#define LPDDR4__DENALI_PHY_381_READ_MASK                             0x003FFFFFU
+#define LPDDR4__DENALI_PHY_381_WRITE_MASK                            0x003FFFFFU
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_SHIFT        0U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1_WIDTH       16U
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_DSLICE_PAD_BOOSTPN_SETTING_1__FLD LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_BOOSTPN_SETTING_1
+
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_SHIFT       16U
+#define LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1_WIDTH        6U
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__REG DENALI_PHY_381
+#define LPDDR4__PHY_DSLICE_PAD_RX_CTLE_SETTING_1__FLD LPDDR4__DENALI_PHY_381__PHY_DSLICE_PAD_RX_CTLE_SETTING_1
+
+#endif /* REG_LPDDR4_DATA_SLICE_1_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
new file mode 100644
index 000000000000..3df803e9ef78
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_ddr_controller_macros.h
@@ -0,0 +1,6436 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+#define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
+
+#define LPDDR4__DENALI_CTL_0_READ_MASK                               0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK                              0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH                                     1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET                                     0U
+#define LPDDR4__START__REG DENALI_CTL_0
+#define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
+
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH                                4U
+#define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
+#define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
+
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK                     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH                            16U
+#define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
+#define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
+
+#define LPDDR4__DENALI_CTL_1_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH                     32U
+#define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
+#define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
+
+#define LPDDR4__DENALI_CTL_2_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH                     32U
+#define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
+#define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
+
+#define LPDDR4__DENALI_CTL_3_READ_MASK                               0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK                              0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH                               5U
+#define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK                       0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH                               4U
+#define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
+
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH                                2U
+#define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
+#define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
+
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK              0xFF000000U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH                      8U
+#define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
+#define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK          0x000000FFU
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH                  8U
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK             0x0000FF00U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH                     8U
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK         0x00FF0000U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT                16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH                 8U
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
+#define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH                   16U
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
+
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK        0x00FF0000U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT               16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH                8U
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
+#define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
+
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH                          8U
+#define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
+#define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
+
+#define LPDDR4__DENALI_CTL_6_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK           0x000000FFU
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH                   8U
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK            0x0000FF00U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH                    8U
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK          0x00FF0000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH                  8U
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_MASK   0xFF000000U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_SHIFT          24U
+#define LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH_WIDTH           8U
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
+#define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
+
+#define LPDDR4__DENALI_CTL_7_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK                          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH                                 24U
+#define LPDDR4__TINIT_F0__REG DENALI_CTL_7
+#define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
+
+#define LPDDR4__DENALI_CTL_8_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH                                24U
+#define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
+#define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
+
+#define LPDDR4__DENALI_CTL_9_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH                                24U
+#define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
+#define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
+
+#define LPDDR4__DENALI_CTL_10_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH                               24U
+#define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
+#define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
+
+#define LPDDR4__DENALI_CTL_11_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH                                24U
+#define LPDDR4__TINIT_F1__REG DENALI_CTL_11
+#define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
+
+#define LPDDR4__DENALI_CTL_12_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH                               24U
+#define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
+#define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
+
+#define LPDDR4__DENALI_CTL_13_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH                               24U
+#define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
+#define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
+
+#define LPDDR4__DENALI_CTL_14_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH                               24U
+#define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
+#define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
+
+#define LPDDR4__DENALI_CTL_15_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH                                24U
+#define LPDDR4__TINIT_F2__REG DENALI_CTL_15
+#define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
+
+#define LPDDR4__DENALI_CTL_16_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH                               24U
+#define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
+#define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
+
+#define LPDDR4__DENALI_CTL_17_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH                               24U
+#define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
+#define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
+
+#define LPDDR4__DENALI_CTL_18_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH                               24U
+#define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
+#define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
+
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET                         0U
+#define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
+#define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
+
+#define LPDDR4__DENALI_CTL_19_READ_MASK                              0x03030301U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK                             0x03030301U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET                         0U
+#define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
+#define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F0__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F0__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F0
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_MASK                0x00030000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F1__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F1__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F1
+
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2_WIDTH                        2U
+#define LPDDR4__DFI_FREQ_RATIO_F2__REG DENALI_CTL_19
+#define LPDDR4__DFI_FREQ_RATIO_F2__FLD LPDDR4__DENALI_CTL_19__DFI_FREQ_RATIO_F2
+
+#define LPDDR4__DENALI_CTL_20_READ_MASK                              0x01030101U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK                             0x01030101U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO_WOSET                            0U
+#define LPDDR4__DFI_CMD_RATIO__REG DENALI_CTL_20
+#define LPDDR4__DFI_CMD_RATIO__FLD LPDDR4__DENALI_CTL_20__DFI_CMD_RATIO
+
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_20__NO_MRW_INIT_WOSET                              0U
+#define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_20
+#define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_20__NO_MRW_INIT
+
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_20__ODT_VALUE_WIDTH                                2U
+#define LPDDR4__ODT_VALUE__REG DENALI_CTL_20
+#define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_20__ODT_VALUE
+
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK             0x01000000U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET                     0U
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
+#define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
+
+#define LPDDR4__DENALI_CTL_21_READ_MASK                              0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK                             0x1F1F013FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_MASK                    0x0000003FU
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR_WIDTH                            6U
+#define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_21
+#define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_21__TSREF2PHYMSTR
+
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_MASK              0x00000100U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE_WOSET                      0U
+#define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_21
+#define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_21__PHY_INDEP_INIT_MODE
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
+
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
+#define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
+
+#define LPDDR4__DENALI_CTL_22_READ_MASK                              0x0303031FU
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK                             0x0303031FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_MASK                   0x0000001FU
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2_WIDTH                           5U
+#define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_22
+#define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_22__DFIBUS_FREQ_F2
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
+
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK              0x03000000U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH                      2U
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
+#define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
+
+#define LPDDR4__DENALI_CTL_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH                              32U
+#define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
+#define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
+
+#define LPDDR4__DENALI_CTL_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK                     0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH                            32U
+#define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
+#define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
+
+#define LPDDR4__DENALI_CTL_25_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_25__TDLL_F0_WIDTH                                 16U
+#define LPDDR4__TDLL_F0__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F0__FLD LPDDR4__DENALI_CTL_25__TDLL_F0
+
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_25__TDLL_F1_WIDTH                                 16U
+#define LPDDR4__TDLL_F1__REG DENALI_CTL_25
+#define LPDDR4__TDLL_F1__FLD LPDDR4__DENALI_CTL_25__TDLL_F1
+
+#define LPDDR4__DENALI_CTL_26_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_26__TDLL_F2_WIDTH                                 16U
+#define LPDDR4__TDLL_F2__REG DENALI_CTL_26
+#define LPDDR4__TDLL_F2__FLD LPDDR4__DENALI_CTL_26__TDLL_F2
+
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_SHIFT 16U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WIDTH 1U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOCLR 0U
+#define LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS_WOSET 0U
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__REG DENALI_CTL_26
+#define LPDDR4__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS__FLD LPDDR4__DENALI_CTL_26__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS
+
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_SHIFT      24U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS_WIDTH       2U
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__REG DENALI_CTL_26
+#define LPDDR4__DQS_OSC_PER_CS_OOV_TRAINING_STATUS__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_PER_CS_OOV_TRAINING_STATUS
+
+#define LPDDR4__DENALI_CTL_27_READ_MASK                              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK                             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_TST_WOSET                              0U
+#define LPDDR4__DQS_OSC_TST__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_TST__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_TST
+
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_MASK                  0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD_WIDTH                         24U
+#define LPDDR4__DQS_OSC_MPC_CMD__REG DENALI_CTL_27
+#define LPDDR4__DQS_OSC_MPC_CMD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_MPC_CMD
+
+#define LPDDR4__DENALI_CTL_28_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_28__MRR_LSB_REG_WIDTH                              8U
+#define LPDDR4__MRR_LSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_LSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_LSB_REG
+
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_28__MRR_MSB_REG_WIDTH                              8U
+#define LPDDR4__MRR_MSB_REG__REG DENALI_CTL_28
+#define LPDDR4__MRR_MSB_REG__FLD LPDDR4__DENALI_CTL_28__MRR_MSB_REG
+
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE_WOSET                           0U
+#define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_28
+#define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_ENABLE
+
+#define LPDDR4__DENALI_CTL_29_READ_MASK                              0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK                             0x000F7FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_MASK                   0x00007FFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD_WIDTH                          15U
+#define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_29
+#define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PERIOD
+
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES_WIDTH                        4U
+#define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_29
+#define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_29__FUNC_VALID_CYCLES
+
+#define LPDDR4__DENALI_CTL_30_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD_WIDTH                  32U
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_30
+#define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_31_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD_WIDTH                  32U
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_31
+#define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_31__DQS_OSC_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_32_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT_WIDTH                         32U
+#define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_32
+#define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_32__DQS_OSC_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_33_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_SHIFT                0U
+#define LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD_WIDTH               32U
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_33
+#define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_33__DQS_OSC_PROMOTE_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_34_READ_MASK                              0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK                             0xFF00FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_MASK               0x0000FFFFU
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT_WIDTH                      16U
+#define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_34
+#define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_34__OSC_VARIANCE_LIMIT
+
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST_WOSET                          0U
+#define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_34
+#define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_34__DQS_OSC_REQUEST
+
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_MASK                         0xFF000000U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_34__TOSCO_F0_WIDTH                                 8U
+#define LPDDR4__TOSCO_F0__REG DENALI_CTL_34
+#define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_34__TOSCO_F0
+
+#define LPDDR4__DENALI_CTL_35_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F1_WIDTH                                 8U
+#define LPDDR4__TOSCO_F1__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_35__TOSCO_F1
+
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_MASK                         0x0000FF00U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_35__TOSCO_F2_WIDTH                                 8U
+#define LPDDR4__TOSCO_F2__REG DENALI_CTL_35
+#define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_35__TOSCO_F2
+
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_35
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_35__DQS_OSC_BASE_VALUE_0_CS0
+
+#define LPDDR4__DENALI_CTL_36_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_1_CS0
+
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_36
+#define LPDDR4__DQS_OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_36__DQS_OSC_BASE_VALUE_0_CS1
+
+#define LPDDR4__DENALI_CTL_37_READ_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1_WIDTH                16U
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_BASE_VALUE_1_CS1
+
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS_WIDTH                           4U
+#define LPDDR4__DQS_OSC_STATUS__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_STATUS__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_STATUS
+
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_MASK       0x01000000U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_SHIFT              24U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WIDTH               1U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WOCLR               0U
+#define LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS_WOSET               0U
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__REG DENALI_CTL_37
+#define LPDDR4__DQS_OSC_IN_PROGRESS_STATUS__FLD LPDDR4__DENALI_CTL_37__DQS_OSC_IN_PROGRESS_STATUS
+
+#define LPDDR4__DENALI_CTL_38_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_38
+#define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_38__CASLAT_LIN_F0
+
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_38__WRLAT_F0_WIDTH                                 7U
+#define LPDDR4__WRLAT_F0__REG DENALI_CTL_38
+#define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_38__WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F0__REG DENALI_CTL_38
+#define LPDDR4__ADDITIVE_LAT_F0__FLD LPDDR4__DENALI_CTL_38__ADDITIVE_LAT_F0
+
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F0__REG DENALI_CTL_38
+#define LPDDR4__CA_PARITY_LAT_F0__FLD LPDDR4__DENALI_CTL_38__CA_PARITY_LAT_F0
+
+#define LPDDR4__DENALI_CTL_39_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_F0_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F0__REG DENALI_CTL_39
+#define LPDDR4__TMOD_PAR_F0__FLD LPDDR4__DENALI_CTL_39__TMOD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_F0_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F0__REG DENALI_CTL_39
+#define LPDDR4__TMRD_PAR_F0__FLD LPDDR4__DENALI_CTL_39__TMRD_PAR_F0
+
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__REG DENALI_CTL_39
+#define LPDDR4__TMOD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_39__TMOD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__REG DENALI_CTL_39
+#define LPDDR4__TMRD_PAR_MAX_PL_F0__FLD LPDDR4__DENALI_CTL_39__TMRD_PAR_MAX_PL_F0
+
+#define LPDDR4__DENALI_CTL_40_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_40
+#define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_40__CASLAT_LIN_F1
+
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_40__WRLAT_F1_WIDTH                                 7U
+#define LPDDR4__WRLAT_F1__REG DENALI_CTL_40
+#define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_40__WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F1__REG DENALI_CTL_40
+#define LPDDR4__ADDITIVE_LAT_F1__FLD LPDDR4__DENALI_CTL_40__ADDITIVE_LAT_F1
+
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F1__REG DENALI_CTL_40
+#define LPDDR4__CA_PARITY_LAT_F1__FLD LPDDR4__DENALI_CTL_40__CA_PARITY_LAT_F1
+
+#define LPDDR4__DENALI_CTL_41_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_F1_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F1__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_F1__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_F1_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F1__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_F1__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_F1
+
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__REG DENALI_CTL_41
+#define LPDDR4__TMOD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_41__TMOD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__REG DENALI_CTL_41
+#define LPDDR4__TMRD_PAR_MAX_PL_F1__FLD LPDDR4__DENALI_CTL_41__TMRD_PAR_MAX_PL_F1
+
+#define LPDDR4__DENALI_CTL_42_READ_MASK                              0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK                             0x0F3F7F7FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2_WIDTH                            7U
+#define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_42
+#define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_42__CASLAT_LIN_F2
+
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_42__WRLAT_F2_WIDTH                                 7U
+#define LPDDR4__WRLAT_F2__REG DENALI_CTL_42
+#define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_42__WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_MASK                  0x003F0000U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2_WIDTH                          6U
+#define LPDDR4__ADDITIVE_LAT_F2__REG DENALI_CTL_42
+#define LPDDR4__ADDITIVE_LAT_F2__FLD LPDDR4__DENALI_CTL_42__ADDITIVE_LAT_F2
+
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2_WIDTH                         4U
+#define LPDDR4__CA_PARITY_LAT_F2__REG DENALI_CTL_42
+#define LPDDR4__CA_PARITY_LAT_F2__FLD LPDDR4__DENALI_CTL_42__CA_PARITY_LAT_F2
+
+#define LPDDR4__DENALI_CTL_43_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_F2_WIDTH                              8U
+#define LPDDR4__TMOD_PAR_F2__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_F2__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_F2_WIDTH                              8U
+#define LPDDR4__TMRD_PAR_F2__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_F2__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_F2
+
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2_WIDTH                       8U
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__REG DENALI_CTL_43
+#define LPDDR4__TMOD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_43__TMOD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2_WIDTH                       8U
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__REG DENALI_CTL_43
+#define LPDDR4__TMRD_PAR_MAX_PL_F2__FLD LPDDR4__DENALI_CTL_43__TMRD_PAR_MAX_PL_F2
+
+#define LPDDR4__DENALI_CTL_44_READ_MASK                              0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK                             0xFF1F1F07U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL_WIDTH                        3U
+#define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_44
+#define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_44__TBST_INT_INTERVAL
+
+#define LPDDR4__DENALI_CTL_44__TCCD_MASK                             0x00001F00U
+#define LPDDR4__DENALI_CTL_44__TCCD_SHIFT                                     8U
+#define LPDDR4__DENALI_CTL_44__TCCD_WIDTH                                     5U
+#define LPDDR4__TCCD__REG DENALI_CTL_44
+#define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_44__TCCD
+
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_MASK                        0x001F0000U
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_44__TCCD_L_F0_WIDTH                                5U
+#define LPDDR4__TCCD_L_F0__REG DENALI_CTL_44
+#define LPDDR4__TCCD_L_F0__FLD LPDDR4__DENALI_CTL_44__TCCD_L_F0
+
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_44__TRRD_F0_WIDTH                                  8U
+#define LPDDR4__TRRD_F0__REG DENALI_CTL_44
+#define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_44__TRRD_F0
+
+#define LPDDR4__DENALI_CTL_45_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_45__TRRD_L_F0_WIDTH                                8U
+#define LPDDR4__TRRD_L_F0__REG DENALI_CTL_45
+#define LPDDR4__TRRD_L_F0__FLD LPDDR4__DENALI_CTL_45__TRRD_L_F0
+
+#define LPDDR4__DENALI_CTL_45__TRC_F0_MASK                           0x0001FF00U
+#define LPDDR4__DENALI_CTL_45__TRC_F0_SHIFT                                   8U
+#define LPDDR4__DENALI_CTL_45__TRC_F0_WIDTH                                   9U
+#define LPDDR4__TRC_F0__REG DENALI_CTL_45
+#define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_45__TRC_F0
+
+#define LPDDR4__DENALI_CTL_46_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_46__TRAS_MIN_F0_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_46
+#define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_46__TRAS_MIN_F0
+
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_46__TWTR_F0_WIDTH                                  6U
+#define LPDDR4__TWTR_F0__REG DENALI_CTL_46
+#define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_46__TWTR_F0
+
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_46__TWTR_L_F0_WIDTH                                6U
+#define LPDDR4__TWTR_L_F0__REG DENALI_CTL_46
+#define LPDDR4__TWTR_L_F0__FLD LPDDR4__DENALI_CTL_46__TWTR_L_F0
+
+#define LPDDR4__DENALI_CTL_47_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_47__TRP_F0_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TRP_F0_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_47__TRP_F0_WIDTH                                   8U
+#define LPDDR4__TRP_F0__REG DENALI_CTL_47
+#define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_47__TRP_F0
+
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_47__TFAW_F0_WIDTH                                  9U
+#define LPDDR4__TFAW_F0__REG DENALI_CTL_47
+#define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_47__TFAW_F0
+
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_47__TCCD_L_F1_WIDTH                                5U
+#define LPDDR4__TCCD_L_F1__REG DENALI_CTL_47
+#define LPDDR4__TCCD_L_F1__FLD LPDDR4__DENALI_CTL_47__TCCD_L_F1
+
+#define LPDDR4__DENALI_CTL_48_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_48__TRRD_F1_WIDTH                                  8U
+#define LPDDR4__TRRD_F1__REG DENALI_CTL_48
+#define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_48__TRRD_F1
+
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_48__TRRD_L_F1_WIDTH                                8U
+#define LPDDR4__TRRD_L_F1__REG DENALI_CTL_48
+#define LPDDR4__TRRD_L_F1__FLD LPDDR4__DENALI_CTL_48__TRRD_L_F1
+
+#define LPDDR4__DENALI_CTL_48__TRC_F1_MASK                           0x01FF0000U
+#define LPDDR4__DENALI_CTL_48__TRC_F1_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_48__TRC_F1_WIDTH                                   9U
+#define LPDDR4__TRC_F1__REG DENALI_CTL_48
+#define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_48__TRC_F1
+
+#define LPDDR4__DENALI_CTL_49_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_49__TRAS_MIN_F1_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_49
+#define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_49__TRAS_MIN_F1
+
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_49__TWTR_F1_WIDTH                                  6U
+#define LPDDR4__TWTR_F1__REG DENALI_CTL_49
+#define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_49__TWTR_F1
+
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_49__TWTR_L_F1_WIDTH                                6U
+#define LPDDR4__TWTR_L_F1__REG DENALI_CTL_49
+#define LPDDR4__TWTR_L_F1__FLD LPDDR4__DENALI_CTL_49__TWTR_L_F1
+
+#define LPDDR4__DENALI_CTL_50_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_50__TRP_F1_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_50__TRP_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_50__TRP_F1_WIDTH                                   8U
+#define LPDDR4__TRP_F1__REG DENALI_CTL_50
+#define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_50__TRP_F1
+
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_50__TFAW_F1_WIDTH                                  9U
+#define LPDDR4__TFAW_F1__REG DENALI_CTL_50
+#define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_50__TFAW_F1
+
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_50__TCCD_L_F2_WIDTH                                5U
+#define LPDDR4__TCCD_L_F2__REG DENALI_CTL_50
+#define LPDDR4__TCCD_L_F2__FLD LPDDR4__DENALI_CTL_50__TCCD_L_F2
+
+#define LPDDR4__DENALI_CTL_51_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_51__TRRD_F2_WIDTH                                  8U
+#define LPDDR4__TRRD_F2__REG DENALI_CTL_51
+#define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_51__TRRD_F2
+
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_51__TRRD_L_F2_WIDTH                                8U
+#define LPDDR4__TRRD_L_F2__REG DENALI_CTL_51
+#define LPDDR4__TRRD_L_F2__FLD LPDDR4__DENALI_CTL_51__TRRD_L_F2
+
+#define LPDDR4__DENALI_CTL_51__TRC_F2_MASK                           0x01FF0000U
+#define LPDDR4__DENALI_CTL_51__TRC_F2_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_51__TRC_F2_WIDTH                                   9U
+#define LPDDR4__TRC_F2__REG DENALI_CTL_51
+#define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_51__TRC_F2
+
+#define LPDDR4__DENALI_CTL_52_READ_MASK                              0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK                             0x3F3F01FFU
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_MASK                      0x000001FFU
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_52__TRAS_MIN_F2_WIDTH                              9U
+#define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_52
+#define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_52__TRAS_MIN_F2
+
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_MASK                          0x003F0000U
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_52__TWTR_F2_WIDTH                                  6U
+#define LPDDR4__TWTR_F2__REG DENALI_CTL_52
+#define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_52__TWTR_F2
+
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_MASK                        0x3F000000U
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_52__TWTR_L_F2_WIDTH                                6U
+#define LPDDR4__TWTR_L_F2__REG DENALI_CTL_52
+#define LPDDR4__TWTR_L_F2__FLD LPDDR4__DENALI_CTL_52__TWTR_L_F2
+
+#define LPDDR4__DENALI_CTL_53_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_53__TRP_F2_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_53__TRP_F2_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_53__TRP_F2_WIDTH                                   8U
+#define LPDDR4__TRP_F2__REG DENALI_CTL_53
+#define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_53__TRP_F2
+
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_53__TFAW_F2_WIDTH                                  9U
+#define LPDDR4__TFAW_F2__REG DENALI_CTL_53
+#define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_53__TFAW_F2
+
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_53__TRTP_F0_WIDTH                                  8U
+#define LPDDR4__TRTP_F0__REG DENALI_CTL_53
+#define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_53__TRTP_F0
+
+#define LPDDR4__DENALI_CTL_54_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_54__TRTP_AP_F0_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F0__REG DENALI_CTL_54
+#define LPDDR4__TRTP_AP_F0__FLD LPDDR4__DENALI_CTL_54__TRTP_AP_F0
+
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_54__TMRD_F0_WIDTH                                  8U
+#define LPDDR4__TMRD_F0__REG DENALI_CTL_54
+#define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_54__TMRD_F0
+
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_54__TMOD_F0_WIDTH                                  8U
+#define LPDDR4__TMOD_F0__REG DENALI_CTL_54
+#define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_54__TMOD_F0
+
+#define LPDDR4__DENALI_CTL_55_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_55__TRAS_MAX_F0_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_55
+#define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_55__TRAS_MAX_F0
+
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_55__TCKE_F0_WIDTH                                  5U
+#define LPDDR4__TCKE_F0__REG DENALI_CTL_55
+#define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_55__TCKE_F0
+
+#define LPDDR4__DENALI_CTL_56_READ_MASK                              0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK                             0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_56__TCKESR_F0_WIDTH                                8U
+#define LPDDR4__TCKESR_F0__REG DENALI_CTL_56
+#define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_56__TCKESR_F0
+
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_56__TCCDMW_F0_WIDTH                                6U
+#define LPDDR4__TCCDMW_F0__REG DENALI_CTL_56
+#define LPDDR4__TCCDMW_F0__FLD LPDDR4__DENALI_CTL_56__TCCDMW_F0
+
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_56__TRTP_F1_WIDTH                                  8U
+#define LPDDR4__TRTP_F1__REG DENALI_CTL_56
+#define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_56__TRTP_F1
+
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_MASK                       0xFF000000U
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_56__TRTP_AP_F1_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F1__REG DENALI_CTL_56
+#define LPDDR4__TRTP_AP_F1__FLD LPDDR4__DENALI_CTL_56__TRTP_AP_F1
+
+#define LPDDR4__DENALI_CTL_57_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_57__TMRD_F1_WIDTH                                  8U
+#define LPDDR4__TMRD_F1__REG DENALI_CTL_57
+#define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_57__TMRD_F1
+
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_57__TMOD_F1_WIDTH                                  8U
+#define LPDDR4__TMOD_F1__REG DENALI_CTL_57
+#define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_57__TMOD_F1
+
+#define LPDDR4__DENALI_CTL_58_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_58__TRAS_MAX_F1_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_58
+#define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_58__TRAS_MAX_F1
+
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_58__TCKE_F1_WIDTH                                  5U
+#define LPDDR4__TCKE_F1__REG DENALI_CTL_58
+#define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_58__TCKE_F1
+
+#define LPDDR4__DENALI_CTL_59_READ_MASK                              0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK                             0xFFFF3FFFU
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_59__TCKESR_F1_WIDTH                                8U
+#define LPDDR4__TCKESR_F1__REG DENALI_CTL_59
+#define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_59__TCKESR_F1
+
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_59__TCCDMW_F1_WIDTH                                6U
+#define LPDDR4__TCCDMW_F1__REG DENALI_CTL_59
+#define LPDDR4__TCCDMW_F1__FLD LPDDR4__DENALI_CTL_59__TCCDMW_F1
+
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_59__TRTP_F2_WIDTH                                  8U
+#define LPDDR4__TRTP_F2__REG DENALI_CTL_59
+#define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_59__TRTP_F2
+
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_MASK                       0xFF000000U
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_59__TRTP_AP_F2_WIDTH                               8U
+#define LPDDR4__TRTP_AP_F2__REG DENALI_CTL_59
+#define LPDDR4__TRTP_AP_F2__FLD LPDDR4__DENALI_CTL_59__TRTP_AP_F2
+
+#define LPDDR4__DENALI_CTL_60_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_60__TMRD_F2_WIDTH                                  8U
+#define LPDDR4__TMRD_F2__REG DENALI_CTL_60
+#define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_60__TMRD_F2
+
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_60__TMOD_F2_WIDTH                                  8U
+#define LPDDR4__TMOD_F2__REG DENALI_CTL_60
+#define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_60__TMOD_F2
+
+#define LPDDR4__DENALI_CTL_61_READ_MASK                              0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK                             0x1F0FFFFFU
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_61__TRAS_MAX_F2_WIDTH                             20U
+#define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_61
+#define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_61__TRAS_MAX_F2
+
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_61__TCKE_F2_WIDTH                                  5U
+#define LPDDR4__TCKE_F2__REG DENALI_CTL_61
+#define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_61__TCKE_F2
+
+#define LPDDR4__DENALI_CTL_62_READ_MASK                              0x07073FFFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK                             0x07073FFFU
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_62__TCKESR_F2_WIDTH                                8U
+#define LPDDR4__TCKESR_F2__REG DENALI_CTL_62
+#define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_62__TCKESR_F2
+
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_62__TCCDMW_F2_WIDTH                                6U
+#define LPDDR4__TCCDMW_F2__REG DENALI_CTL_62
+#define LPDDR4__TCCDMW_F2__FLD LPDDR4__DENALI_CTL_62__TCCDMW_F2
+
+#define LPDDR4__DENALI_CTL_62__TPPD_MASK                             0x00070000U
+#define LPDDR4__DENALI_CTL_62__TPPD_SHIFT                                    16U
+#define LPDDR4__DENALI_CTL_62__TPPD_WIDTH                                     3U
+#define LPDDR4__TPPD__REG DENALI_CTL_62
+#define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_62__TPPD
+
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_62__MC_RESERVED0_WIDTH                             3U
+#define LPDDR4__MC_RESERVED0__REG DENALI_CTL_62
+#define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_62__MC_RESERVED0
+
+#define LPDDR4__DENALI_CTL_63_READ_MASK                              0xFFFF0107U
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK                             0xFFFF0107U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_63__MC_RESERVED1_WIDTH                             3U
+#define LPDDR4__MC_RESERVED1__REG DENALI_CTL_63
+#define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_63__MC_RESERVED1
+
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_63__WRITEINTERP_WOSET                              0U
+#define LPDDR4__WRITEINTERP__REG DENALI_CTL_63
+#define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_63__WRITEINTERP
+
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_63__TRCD_F0_WIDTH                                  8U
+#define LPDDR4__TRCD_F0__REG DENALI_CTL_63
+#define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_63__TRCD_F0
+
+#define LPDDR4__DENALI_CTL_63__TWR_F0_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_63__TWR_F0_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_63__TWR_F0_WIDTH                                   8U
+#define LPDDR4__TWR_F0__REG DENALI_CTL_63
+#define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_63__TWR_F0
+
+#define LPDDR4__DENALI_CTL_64_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_64__TRCD_F1_WIDTH                                  8U
+#define LPDDR4__TRCD_F1__REG DENALI_CTL_64
+#define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_64__TRCD_F1
+
+#define LPDDR4__DENALI_CTL_64__TWR_F1_MASK                           0x0000FF00U
+#define LPDDR4__DENALI_CTL_64__TWR_F1_SHIFT                                   8U
+#define LPDDR4__DENALI_CTL_64__TWR_F1_WIDTH                                   8U
+#define LPDDR4__TWR_F1__REG DENALI_CTL_64
+#define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_64__TWR_F1
+
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_64__TRCD_F2_WIDTH                                  8U
+#define LPDDR4__TRCD_F2__REG DENALI_CTL_64
+#define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_64__TRCD_F2
+
+#define LPDDR4__DENALI_CTL_64__TWR_F2_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_64__TWR_F2_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_64__TWR_F2_WIDTH                                   8U
+#define LPDDR4__TWR_F2__REG DENALI_CTL_64
+#define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_64__TWR_F2
+
+#define LPDDR4__DENALI_CTL_65_READ_MASK                              0x0101010FU
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK                             0x0101010FU
+#define LPDDR4__DENALI_CTL_65__TMRR_MASK                             0x0000000FU
+#define LPDDR4__DENALI_CTL_65__TMRR_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_65__TMRR_WIDTH                                     4U
+#define LPDDR4__TMRR__REG DENALI_CTL_65
+#define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_65__TMRR
+
+#define LPDDR4__DENALI_CTL_65__AP_MASK                               0x00000100U
+#define LPDDR4__DENALI_CTL_65__AP_SHIFT                                       8U
+#define LPDDR4__DENALI_CTL_65__AP_WIDTH                                       1U
+#define LPDDR4__DENALI_CTL_65__AP_WOCLR                                       0U
+#define LPDDR4__DENALI_CTL_65__AP_WOSET                                       0U
+#define LPDDR4__AP__REG DENALI_CTL_65
+#define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_65__AP
+
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_65__CONCURRENTAP_WOSET                             0U
+#define LPDDR4__CONCURRENTAP__REG DENALI_CTL_65
+#define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_65__CONCURRENTAP
+
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT_WOSET                             0U
+#define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_65
+#define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_65__TRAS_LOCKOUT
+
+#define LPDDR4__DENALI_CTL_66_READ_MASK                              0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK                             0x3FFFFFFFU
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_66__TDAL_F0_WIDTH                                  8U
+#define LPDDR4__TDAL_F0__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_66__TDAL_F0
+
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_66__TDAL_F1_WIDTH                                  8U
+#define LPDDR4__TDAL_F1__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_66__TDAL_F1
+
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_66__TDAL_F2_WIDTH                                  8U
+#define LPDDR4__TDAL_F2__REG DENALI_CTL_66
+#define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_66__TDAL_F2
+
+#define LPDDR4__DENALI_CTL_66__BSTLEN_MASK                           0x3F000000U
+#define LPDDR4__DENALI_CTL_66__BSTLEN_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_66__BSTLEN_WIDTH                                   6U
+#define LPDDR4__BSTLEN__REG DENALI_CTL_66
+#define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_66__BSTLEN
+
+#define LPDDR4__DENALI_CTL_67_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F0_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F1_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F1_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F2_0_WIDTH                              8U
+#define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F2_0
+
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_67__TRP_AB_F0_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_67
+#define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_67__TRP_AB_F0_1
+
+#define LPDDR4__DENALI_CTL_68_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F1_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_68
+#define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_68__TRP_AB_F1_1
+
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_68__TRP_AB_F2_1_WIDTH                              8U
+#define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_68
+#define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_68__TRP_AB_F2_1
+
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE_WOSET                          0U
+#define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_68
+#define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_68__REG_DIMM_ENABLE
+
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING_WIDTH                        2U
+#define LPDDR4__ADDRESS_MIRRORING__REG DENALI_CTL_68
+#define LPDDR4__ADDRESS_MIRRORING__FLD LPDDR4__DENALI_CTL_68__ADDRESS_MIRRORING
+
+#define LPDDR4__DENALI_CTL_69_READ_MASK                              0x00010101U
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN_WOSET                         0U
+#define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_69
+#define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_69__OPTIMAL_RMODW_EN
+
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_69__MC_RESERVED2_WOSET                             0U
+#define LPDDR4__MC_RESERVED2__REG DENALI_CTL_69
+#define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_69__MC_RESERVED2
+
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_69__NO_MEMORY_DM_WOSET                             0U
+#define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_69
+#define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_69__NO_MEMORY_DM
+
+#define LPDDR4__DENALI_CTL_70_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_MASK           0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT_WIDTH                  26U
+#define LPDDR4__CA_PARITY_ERROR_INJECT__REG DENALI_CTL_70
+#define LPDDR4__CA_PARITY_ERROR_INJECT__FLD LPDDR4__DENALI_CTL_70__CA_PARITY_ERROR_INJECT
+
+#define LPDDR4__DENALI_CTL_71_READ_MASK                              0x01010001U
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK                             0x01010001U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR_WOSET                          0U
+#define LPDDR4__CA_PARITY_ERROR__REG DENALI_CTL_71
+#define LPDDR4__CA_PARITY_ERROR__FLD LPDDR4__DENALI_CTL_71__CA_PARITY_ERROR
+
+#define LPDDR4__DENALI_CTL_71__AREFRESH_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_71__AREFRESH_WOSET                                 0U
+#define LPDDR4__AREFRESH__REG DENALI_CTL_71
+#define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_71__AREFRESH
+
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_71__AREF_STATUS_WOSET                              0U
+#define LPDDR4__AREF_STATUS__REG DENALI_CTL_71
+#define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_71__AREF_STATUS
+
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_71__TREF_ENABLE_WOSET                              0U
+#define LPDDR4__TREF_ENABLE__REG DENALI_CTL_71
+#define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_71__TREF_ENABLE
+
+#define LPDDR4__DENALI_CTL_72_READ_MASK                              0x03FF3F07U
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK                             0x03FF3F07U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_MASK               0x00000007U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD_WIDTH                       3U
+#define LPDDR4__TRFC_OPT_THRESHOLD__REG DENALI_CTL_72
+#define LPDDR4__TRFC_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_72__TRFC_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK  0x00003F00U
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT          8U
+#define LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH          6U
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_72
+#define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_72__CS_COMPARISON_FOR_REFRESH_DEPTH
+
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_MASK                          0x03FF0000U
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_72__TRFC_F0_WIDTH                                 10U
+#define LPDDR4__TRFC_F0__REG DENALI_CTL_72
+#define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_72__TRFC_F0
+
+#define LPDDR4__DENALI_CTL_73_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73__TREF_F0_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_73__TREF_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_73__TREF_F0_WIDTH                                 20U
+#define LPDDR4__TREF_F0__REG DENALI_CTL_73
+#define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_73__TREF_F0
+
+#define LPDDR4__DENALI_CTL_74_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_74__TRFC_F1_WIDTH                                 10U
+#define LPDDR4__TRFC_F1__REG DENALI_CTL_74
+#define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_74__TRFC_F1
+
+#define LPDDR4__DENALI_CTL_75_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F1_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_75__TREF_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_75__TREF_F1_WIDTH                                 20U
+#define LPDDR4__TREF_F1__REG DENALI_CTL_75
+#define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_75__TREF_F1
+
+#define LPDDR4__DENALI_CTL_76_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_76__TRFC_F2_WIDTH                                 10U
+#define LPDDR4__TRFC_F2__REG DENALI_CTL_76
+#define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_76__TRFC_F2
+
+#define LPDDR4__DENALI_CTL_77_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F2_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_77__TREF_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_77__TREF_F2_WIDTH                                 20U
+#define LPDDR4__TREF_F2__REG DENALI_CTL_77
+#define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_77__TREF_F2
+
+#define LPDDR4__DENALI_CTL_78_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_MASK                    0x000FFFFFU
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_78__TREF_INTERVAL_WIDTH                           20U
+#define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_78
+#define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_78__TREF_INTERVAL
+
+#define LPDDR4__DENALI_CTL_79_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_79__TRFC_PB_F0_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_79
+#define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_79__TRFC_PB_F0
+
+#define LPDDR4__DENALI_CTL_80_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_80__TREFI_PB_F0_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_80
+#define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_80__TREFI_PB_F0
+
+#define LPDDR4__DENALI_CTL_81_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_81__TRFC_PB_F1_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_81
+#define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_81__TRFC_PB_F1
+
+#define LPDDR4__DENALI_CTL_82_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_82__TREFI_PB_F1_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_82
+#define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_82__TREFI_PB_F1
+
+#define LPDDR4__DENALI_CTL_83_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_MASK                       0x000003FFU
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_83__TRFC_PB_F2_WIDTH                              10U
+#define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_83
+#define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_83__TRFC_PB_F2
+
+#define LPDDR4__DENALI_CTL_84_READ_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_MASK                      0x000FFFFFU
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_84__TREFI_PB_F2_WIDTH                             20U
+#define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_84
+#define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_84__TREFI_PB_F2
+
+#define LPDDR4__DENALI_CTL_84__PBR_EN_MASK                           0x01000000U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WIDTH                                   1U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WOCLR                                   0U
+#define LPDDR4__DENALI_CTL_84__PBR_EN_WOSET                                   0U
+#define LPDDR4__PBR_EN__REG DENALI_CTL_84
+#define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_84__PBR_EN
+
+#define LPDDR4__DENALI_CTL_85_READ_MASK                              0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK                             0x0FFFFF01U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER_WOSET                        0U
+#define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_85
+#define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_85__PBR_NUMERIC_ORDER
+
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_MASK                0x00FFFF00U
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT_WIDTH                       16U
+#define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_85
+#define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_85__PBR_MAX_BANK_WAIT
+
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_MASK            0x0F000000U
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY_WIDTH                    4U
+#define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_85
+#define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_85__PBR_BANK_SELECT_DELAY
+
+#define LPDDR4__DENALI_CTL_86_READ_MASK                              0x001F1F01U
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK                             0x001F1F01U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN_WOSET                          0U
+#define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_86
+#define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_86__PBR_CONT_REQ_EN
+
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_MASK       0x00001F00U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_SHIFT               8U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD_WIDTH               5U
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__REG DENALI_CTL_86
+#define LPDDR4__AREF_PBR_CONT_EN_THRESHOLD__FLD LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_EN_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_MASK      0x001F0000U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_SHIFT             16U
+#define LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD_WIDTH              5U
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_86
+#define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_86__AREF_PBR_CONT_DIS_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_87_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F0_WIDTH                                16U
+#define LPDDR4__TPDEX_F0__REG DENALI_CTL_87
+#define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_87__TPDEX_F0
+
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_87__TPDEX_F1_WIDTH                                16U
+#define LPDDR4__TPDEX_F1__REG DENALI_CTL_87
+#define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_87__TPDEX_F1
+
+#define LPDDR4__DENALI_CTL_88_READ_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_88__TPDEX_F2_WIDTH                                16U
+#define LPDDR4__TPDEX_F2__REG DENALI_CTL_88
+#define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_88__TPDEX_F2
+
+#define LPDDR4__DENALI_CTL_89_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0_WIDTH                        32U
+#define LPDDR4__CTL_UNUSED_REG_0__REG DENALI_CTL_89
+#define LPDDR4__CTL_UNUSED_REG_0__FLD LPDDR4__DENALI_CTL_89__CTL_UNUSED_REG_0
+
+#define LPDDR4__DENALI_CTL_90_READ_MASK                              0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK                             0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F0_WIDTH                                 8U
+#define LPDDR4__TMRRI_F0__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_90__TMRRI_F0
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_MASK                         0x0000FF00U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F1_WIDTH                                 8U
+#define LPDDR4__TMRRI_F1__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_90__TMRRI_F1
+
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_MASK                         0x00FF0000U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_90__TMRRI_F2_WIDTH                                 8U
+#define LPDDR4__TMRRI_F2__REG DENALI_CTL_90
+#define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_90__TMRRI_F2
+
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_90__TCKELCS_F0_WIDTH                               5U
+#define LPDDR4__TCKELCS_F0__REG DENALI_CTL_90
+#define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_90__TCKELCS_F0
+
+#define LPDDR4__DENALI_CTL_91_READ_MASK                              0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK                             0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_91__TCKEHCS_F0_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_91
+#define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_91__TCKEHCS_F0
+
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_91__TMRWCKEL_F0_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_91
+#define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_91__TMRWCKEL_F0
+
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_MASK                        0x000F0000U
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_91__TZQCKE_F0_WIDTH                                4U
+#define LPDDR4__TZQCKE_F0__REG DENALI_CTL_91
+#define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_91__TZQCKE_F0
+
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_91__TCKELCS_F1_WIDTH                               5U
+#define LPDDR4__TCKELCS_F1__REG DENALI_CTL_91
+#define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_91__TCKELCS_F1
+
+#define LPDDR4__DENALI_CTL_92_READ_MASK                              0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK                             0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_92__TCKEHCS_F1_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_92
+#define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_92__TCKEHCS_F1
+
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_92__TMRWCKEL_F1_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_92
+#define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_92__TMRWCKEL_F1
+
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_MASK                        0x000F0000U
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_92__TZQCKE_F1_WIDTH                                4U
+#define LPDDR4__TZQCKE_F1__REG DENALI_CTL_92
+#define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_92__TZQCKE_F1
+
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_92__TCKELCS_F2_WIDTH                               5U
+#define LPDDR4__TCKELCS_F2__REG DENALI_CTL_92
+#define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_92__TCKELCS_F2
+
+#define LPDDR4__DENALI_CTL_93_READ_MASK                              0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK                             0x1F0F1F1FU
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_93__TCKEHCS_F2_WIDTH                               5U
+#define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_93
+#define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_93__TCKEHCS_F2
+
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_93__TMRWCKEL_F2_WIDTH                              5U
+#define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_93
+#define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_93__TMRWCKEL_F2
+
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_MASK                        0x000F0000U
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_93__TZQCKE_F2_WIDTH                                4U
+#define LPDDR4__TZQCKE_F2__REG DENALI_CTL_93
+#define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_93__TZQCKE_F2
+
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_93__TCSCKE_F0_WIDTH                                5U
+#define LPDDR4__TCSCKE_F0__REG DENALI_CTL_93
+#define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_93__TCSCKE_F0
+
+#define LPDDR4__DENALI_CTL_94_READ_MASK                              0x1F011F01U
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK                             0x1F011F01U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_94
+#define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F0
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_MASK                        0x00001F00U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F1_WIDTH                                5U
+#define LPDDR4__TCSCKE_F1__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F1
+
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_94
+#define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_94__CA_DEFAULT_VAL_F1
+
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_94__TCSCKE_F2_WIDTH                                5U
+#define LPDDR4__TCSCKE_F2__REG DENALI_CTL_94
+#define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_94__TCSCKE_F2
+
+#define LPDDR4__DENALI_CTL_95_READ_MASK                              0x00FFFF01U
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK                             0x00FFFF01U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2_WOSET                        0U
+#define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_95
+#define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_95__CA_DEFAULT_VAL_F2
+
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_MASK                          0x00FFFF00U
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_95__TXSR_F0_WIDTH                                 16U
+#define LPDDR4__TXSR_F0__REG DENALI_CTL_95
+#define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_95__TXSR_F0
+
+#define LPDDR4__DENALI_CTL_96_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_96__TXSNR_F0_WIDTH                                16U
+#define LPDDR4__TXSNR_F0__REG DENALI_CTL_96
+#define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_96__TXSNR_F0
+
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_96__TXSR_F1_WIDTH                                 16U
+#define LPDDR4__TXSR_F1__REG DENALI_CTL_96
+#define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_96__TXSR_F1
+
+#define LPDDR4__DENALI_CTL_97_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_97__TXSNR_F1_WIDTH                                16U
+#define LPDDR4__TXSNR_F1__REG DENALI_CTL_97
+#define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_97__TXSNR_F1
+
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_97__TXSR_F2_WIDTH                                 16U
+#define LPDDR4__TXSR_F2__REG DENALI_CTL_97
+#define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_97__TXSR_F2
+
+#define LPDDR4__DENALI_CTL_98_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_98__TXSNR_F2_WIDTH                                16U
+#define LPDDR4__TXSNR_F2__REG DENALI_CTL_98
+#define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_98__TXSNR_F2
+
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_98__TXPR_F0_WIDTH                                 16U
+#define LPDDR4__TXPR_F0__REG DENALI_CTL_98
+#define LPDDR4__TXPR_F0__FLD LPDDR4__DENALI_CTL_98__TXPR_F0
+
+#define LPDDR4__DENALI_CTL_99_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_99__TXPR_F1_WIDTH                                 16U
+#define LPDDR4__TXPR_F1__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F1__FLD LPDDR4__DENALI_CTL_99__TXPR_F1
+
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_MASK                          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_99__TXPR_F2_WIDTH                                 16U
+#define LPDDR4__TXPR_F2__REG DENALI_CTL_99
+#define LPDDR4__TXPR_F2__FLD LPDDR4__DENALI_CTL_99__TXPR_F2
+
+#define LPDDR4__DENALI_CTL_100_READ_MASK                             0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK                            0x1F1F07FFU
+#define LPDDR4__DENALI_CTL_100__TSR_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_100__TSR_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_100__TSR_F0_WIDTH                                  8U
+#define LPDDR4__TSR_F0__REG DENALI_CTL_100
+#define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_100__TSR_F0
+
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_MASK                       0x00000700U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_100__TESCKE_F0_WIDTH                               3U
+#define LPDDR4__TESCKE_F0__REG DENALI_CTL_100
+#define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_100__TESCKE_F0
+
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_100__TCSCKEH_F0_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_100
+#define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_100__TCSCKEH_F0
+
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_MASK                     0x1F000000U
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_100__TCKELCMD_F0_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_100
+#define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_100__TCKELCMD_F0
+
+#define LPDDR4__DENALI_CTL_101_READ_MASK                             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK                            0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_MASK                     0x0000001FU
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_101__TCKEHCMD_F0_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_101__TCKEHCMD_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_101__TCKCKEL_F0_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_101__TCKCKEL_F0
+
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_101__TCKELPD_F0_WIDTH                              5U
+#define LPDDR4__TCKELPD_F0__REG DENALI_CTL_101
+#define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_101__TCKELPD_F0
+
+#define LPDDR4__DENALI_CTL_101__TSR_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_101__TSR_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_101__TSR_F1_WIDTH                                  8U
+#define LPDDR4__TSR_F1__REG DENALI_CTL_101
+#define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_101__TSR_F1
+
+#define LPDDR4__DENALI_CTL_102_READ_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK                            0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_MASK                       0x00000007U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_102__TESCKE_F1_WIDTH                               3U
+#define LPDDR4__TESCKE_F1__REG DENALI_CTL_102
+#define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_102__TESCKE_F1
+
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_102__TCSCKEH_F1_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_102
+#define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_102__TCSCKEH_F1
+
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_MASK                     0x001F0000U
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_102__TCKELCMD_F1_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_102
+#define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_102__TCKELCMD_F1
+
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_MASK                     0x1F000000U
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_102__TCKEHCMD_F1_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_102
+#define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_102__TCKEHCMD_F1
+
+#define LPDDR4__DENALI_CTL_103_READ_MASK                             0x07FF1F1FU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK                            0x07FF1F1FU
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_103__TCKCKEL_F1_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_103__TCKCKEL_F1
+
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_103__TCKELPD_F1_WIDTH                              5U
+#define LPDDR4__TCKELPD_F1__REG DENALI_CTL_103
+#define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_103__TCKELPD_F1
+
+#define LPDDR4__DENALI_CTL_103__TSR_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_103__TSR_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_103__TSR_F2_WIDTH                                  8U
+#define LPDDR4__TSR_F2__REG DENALI_CTL_103
+#define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_103__TSR_F2
+
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_MASK                       0x07000000U
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_103__TESCKE_F2_WIDTH                               3U
+#define LPDDR4__TESCKE_F2__REG DENALI_CTL_103
+#define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_103__TESCKE_F2
+
+#define LPDDR4__DENALI_CTL_104_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_104__TCSCKEH_F2_WIDTH                              5U
+#define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_104
+#define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_104__TCSCKEH_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_MASK                     0x00001F00U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_104__TCKELCMD_F2_WIDTH                             5U
+#define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKELCMD_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_MASK                     0x001F0000U
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_104__TCKEHCMD_F2_WIDTH                             5U
+#define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_104__TCKEHCMD_F2
+
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_104__TCKCKEL_F2_WIDTH                              5U
+#define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_104
+#define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_104__TCKCKEL_F2
+
+#define LPDDR4__DENALI_CTL_105_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_105__TCKELPD_F2_WIDTH                              5U
+#define LPDDR4__TCKELPD_F2__REG DENALI_CTL_105
+#define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_105__TCKELPD_F2
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F0_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F0
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F1_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F1
+
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_105__TCMDCKE_F2_WIDTH                              5U
+#define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_105
+#define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_105__TCMDCKE_F2
+
+#define LPDDR4__DENALI_CTL_106_READ_MASK                             0x07010101U
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK                            0x07010101U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT_WOSET                     0U
+#define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_106
+#define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_106__PWRUP_SREFRESH_EXIT
+
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_MASK        0x00000100U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_SHIFT                8U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WIDTH                1U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOCLR                0U
+#define LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH_WOSET                0U
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__REG DENALI_CTL_106
+#define LPDDR4__SREFRESH_EXIT_NO_REFRESH__FLD LPDDR4__DENALI_CTL_106__SREFRESH_EXIT_NO_REFRESH
+
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_MASK           0x00010000U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH_WOSET                   0U
+#define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_106
+#define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_106__ENABLE_QUICK_SREFRESH
+
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_MASK                       0x07000000U
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_106__CKE_DELAY_WIDTH                               3U
+#define LPDDR4__CKE_DELAY__REG DENALI_CTL_106
+#define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_106__CKE_DELAY
+
+#define LPDDR4__DENALI_CTL_107_READ_MASK                             0x00017F00U
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK                            0x00017F00U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_MASK                         0x0000001FU
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_107__DFS_CMD_WIDTH                                 5U
+#define LPDDR4__DFS_CMD__REG DENALI_CTL_107
+#define LPDDR4__DFS_CMD__FLD LPDDR4__DENALI_CTL_107__DFS_CMD
+
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_MASK                      0x00007F00U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_107__DFS_STATUS_WIDTH                              7U
+#define LPDDR4__DFS_STATUS__REG DENALI_CTL_107
+#define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_107__DFS_STATUS
+
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_107__DFS_ZQ_EN_WOSET                               0U
+#define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_107
+#define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_107__DFS_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_108_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_108
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_108
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_108__DFS_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_109_READ_MASK                             0x0707FFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_109
+#define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_109__DFS_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG_WIDTH                           3U
+#define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_109
+#define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_109__ZQ_STATUS_LOG
+
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_MASK                    0x07000000U
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_109__MC_RESERVED3_WIDTH                            3U
+#define LPDDR4__MC_RESERVED3__REG DENALI_CTL_109
+#define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_109__MC_RESERVED3
+
+#define LPDDR4__DENALI_CTL_110_READ_MASK                             0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK                            0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED4_WIDTH                            3U
+#define LPDDR4__MC_RESERVED4__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED4
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED5_WIDTH                            8U
+#define LPDDR4__MC_RESERVED5__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED5
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED6_WIDTH                            8U
+#define LPDDR4__MC_RESERVED6__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED6
+
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_MASK                    0xFF000000U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_110__MC_RESERVED7_WIDTH                            8U
+#define LPDDR4__MC_RESERVED7__REG DENALI_CTL_110
+#define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_110__MC_RESERVED7
+
+#define LPDDR4__DENALI_CTL_111_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__REG DENALI_CTL_111
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_111
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_111__UPD_CTRLUPD_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_112_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_SHIFT    16U
+#define LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_112
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_112__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_113_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT     0U
+#define LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_113
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_113__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_113
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_113__UPD_CTRLUPD_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_114_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_114
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_114__UPD_CTRLUPD_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_115_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT     0U
+#define LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_SHIFT    16U
+#define LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_115
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_115__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_116_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__REG DENALI_CTL_116
+#define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_116
+#define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_116__UPD_CTRLUPD_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_117_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_MASK 0xFFFF0000U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_SHIFT    16U
+#define LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_117
+#define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_117__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_118_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT     0U
+#define LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_118
+#define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_118__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_119_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_119
+#define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_F0
+
+#define LPDDR4__DENALI_CTL_120_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_120
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_121_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_121
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_121__TDFI_PHYMSTR_MAX_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_122_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_122
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_MAX_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_123_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_123
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_123__TDFI_PHYMSTR_MAX_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_124_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT       0U
+#define LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_124
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_125_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_125
+#define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_125__TDFI_PHYMSTR_RESP_F0
+
+#define LPDDR4__DENALI_CTL_126_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_126
+#define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_126__TDFI_PHYMSTR_MAX_F1
+
+#define LPDDR4__DENALI_CTL_127_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_127
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_127__TDFI_PHYMSTR_MAX_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_128_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_128
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_128__TDFI_PHYMSTR_MAX_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_129_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_129
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_129__TDFI_PHYMSTR_MAX_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_130_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_130
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_130__TDFI_PHYMSTR_MAX_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_131_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT       0U
+#define LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_131
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_131__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_132_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_132
+#define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_132__TDFI_PHYMSTR_RESP_F1
+
+#define LPDDR4__DENALI_CTL_133_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2_WIDTH                    32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_133
+#define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_133__TDFI_PHYMSTR_MAX_F2
+
+#define LPDDR4__DENALI_CTL_134_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_134
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_134__TDFI_PHYMSTR_MAX_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_135_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_135
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_135__TDFI_PHYMSTR_MAX_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_136_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_136
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_136__TDFI_PHYMSTR_MAX_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_137_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH              32U
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_137
+#define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_137__TDFI_PHYMSTR_MAX_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_138_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT       0U
+#define LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH      16U
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_138
+#define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_138__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_139_READ_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_MASK            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2_WIDTH                   20U
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_139
+#define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_139__TDFI_PHYMSTR_RESP_F2
+
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF_WOSET                         0U
+#define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_139
+#define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_139__PHYMSTR_NO_AREF
+
+#define LPDDR4__DENALI_CTL_140_READ_MASK                             0x00010103U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK                            0x00010103U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_MASK            0x00000003U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS_WIDTH                    2U
+#define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_MASK       0x00000100U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_SHIFT               8U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WIDTH               1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOCLR               0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1_WOSET               0U
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_DFI_VERSION_4P0V1__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_DFI_VERSION_4P0V1
+
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_SHIFT      16U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WIDTH       1U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOCLR       0U
+#define LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE_WOSET       0U
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_140
+#define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_140__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
+
+#define LPDDR4__DENALI_CTL_141_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__REG DENALI_CTL_141
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_141__MRR_TEMPCHK_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_142_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_142
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_142__MRR_TEMPCHK_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_143_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_143
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_143__MRR_TEMPCHK_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_144_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_144
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__MRR_TEMPCHK_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_145_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__REG DENALI_CTL_145
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_145__MRR_TEMPCHK_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_146_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_146
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_146__MRR_TEMPCHK_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_147_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__REG DENALI_CTL_147
+#define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_147__MRR_TEMPCHK_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_148_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_MASK   0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2_WIDTH          24U
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_148
+#define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_148__MRR_TEMPCHK_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_149_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2_WIDTH                 24U
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_149
+#define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_149__MRR_TEMPCHK_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_149__PPR_CONTROL_WOSET                             0U
+#define LPDDR4__PPR_CONTROL__REG DENALI_CTL_149
+#define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_149__PPR_CONTROL
+
+#define LPDDR4__DENALI_CTL_150_READ_MASK                             0x0000FF00U
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK                            0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_WIDTH                             3U
+#define LPDDR4__PPR_COMMAND__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND
+
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_MASK          0x0000FF00U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM_WIDTH                  8U
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__REG DENALI_CTL_150
+#define LPDDR4__PPR_COMMAND_MRW_REGNUM__FLD LPDDR4__DENALI_CTL_150__PPR_COMMAND_MRW_REGNUM
+
+#define LPDDR4__DENALI_CTL_151_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_MASK            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA_WIDTH                   17U
+#define LPDDR4__PPR_COMMAND_MRW_DATA__REG DENALI_CTL_151
+#define LPDDR4__PPR_COMMAND_MRW_DATA__FLD LPDDR4__DENALI_CTL_151__PPR_COMMAND_MRW_DATA
+
+#define LPDDR4__DENALI_CTL_152_READ_MASK                             0x0F01FFFFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK                            0x0F01FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS_WIDTH                        17U
+#define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_ROW_ADDRESS
+
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS_WIDTH                        4U
+#define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_152
+#define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_152__PPR_BANK_ADDRESS
+
+#define LPDDR4__DENALI_CTL_153_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS_WOSET                          0U
+#define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_153
+#define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_153__PPR_CS_ADDRESS
+
+#define LPDDR4__DENALI_CTL_154_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_154__PPR_DATA_0_WIDTH                             32U
+#define LPDDR4__PPR_DATA_0__REG DENALI_CTL_154
+#define LPDDR4__PPR_DATA_0__FLD LPDDR4__DENALI_CTL_154__PPR_DATA_0
+
+#define LPDDR4__DENALI_CTL_155_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_155__PPR_DATA_1_WIDTH                             32U
+#define LPDDR4__PPR_DATA_1__REG DENALI_CTL_155
+#define LPDDR4__PPR_DATA_1__FLD LPDDR4__DENALI_CTL_155__PPR_DATA_1
+
+#define LPDDR4__DENALI_CTL_156_READ_MASK                             0xFFFF0103U
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK                            0xFFFF0103U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_MASK                      0x00000003U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_156__PPR_STATUS_WIDTH                              2U
+#define LPDDR4__PPR_STATUS__REG DENALI_CTL_156
+#define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_156__PPR_STATUS
+
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_MASK               0x00000100U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL_WOSET                       0U
+#define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_156
+#define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_156__FM_OVRIDE_CONTROL
+
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_156__CKSRE_F0_WIDTH                                8U
+#define LPDDR4__CKSRE_F0__REG DENALI_CTL_156
+#define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_156__CKSRE_F0
+
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_MASK                        0xFF000000U
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_156__CKSRX_F0_WIDTH                                8U
+#define LPDDR4__CKSRX_F0__REG DENALI_CTL_156
+#define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_156__CKSRX_F0
+
+#define LPDDR4__DENALI_CTL_157_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F1_WIDTH                                8U
+#define LPDDR4__CKSRE_F1__REG DENALI_CTL_157
+#define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_157__CKSRE_F1
+
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F1_WIDTH                                8U
+#define LPDDR4__CKSRX_F1__REG DENALI_CTL_157
+#define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_157__CKSRX_F1
+
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_157__CKSRE_F2_WIDTH                                8U
+#define LPDDR4__CKSRE_F2__REG DENALI_CTL_157
+#define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_157__CKSRE_F2
+
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_MASK                        0xFF000000U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_157__CKSRX_F2_WIDTH                                8U
+#define LPDDR4__CKSRX_F2__REG DENALI_CTL_157
+#define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_157__CKSRX_F2
+
+#define LPDDR4__DENALI_CTL_158_READ_MASK                             0x0F0F0003U
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK                            0x0F0F0003U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_MASK         0x00000003U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE_WIDTH                 2U
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_158
+#define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_158__LOWPOWER_REFRESH_ENABLE
+
+#define LPDDR4__DENALI_CTL_158__LP_CMD_MASK                          0x00007F00U
+#define LPDDR4__DENALI_CTL_158__LP_CMD_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_158__LP_CMD_WIDTH                                  7U
+#define LPDDR4__LP_CMD__REG DENALI_CTL_158
+#define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_158__LP_CMD
+
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__REG DENALI_CTL_158
+#define LPDDR4__LPI_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_158__LPI_IDLE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_MASK          0x0F000000U
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_158
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_158__LPI_SR_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_MASK           0x0000000FU
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SR_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT        8U
+#define LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_PD_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_MASK        0x0F000000U
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT               24U
+#define LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_159
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_159__LPI_SRPD_SHORT_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_MASK         0x0000000FU
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_MASK 0x00000F00U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_SHIFT      8U
+#define LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_MASK             0x000F0000U
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_160
+#define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_160__LPI_TIMER_WAKEUP_F0
+
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_MASK              0x0F000000U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__REG DENALI_CTL_160
+#define LPDDR4__LPI_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_160__LPI_IDLE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT       16U
+#define LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_161
+#define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_161__LPI_PD_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_MASK        0x0000000FU
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_SHORT_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_MASK         0x00000F00U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x000F0000U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT     16U
+#define LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_MASK             0x0F000000U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_162
+#define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_162__LPI_TIMER_WAKEUP_F1
+
+#define LPDDR4__DENALI_CTL_163_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2_WIDTH                      4U
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_IDLE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_MASK          0x00000F00U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2_WIDTH                  4U
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_MASK           0x000F0000U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2_WIDTH                   4U
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT       24U
+#define LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH        4U
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_163
+#define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_163__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_MASK                0x0000000FU
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2_WIDTH                        4U
+#define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_PD_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_MASK        0x00000F00U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT                8U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH                4U
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_SHORT_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_MASK         0x000F0000U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2_WIDTH                 4U
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_MASK 0x0F000000U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_SHIFT     24U
+#define LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2_WIDTH      4U
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_164
+#define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_164__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165_READ_MASK                             0x00013F0FU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK                            0x00013F0FU
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2_WIDTH                     4U
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_165
+#define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_165__LPI_TIMER_WAKEUP_F2
+
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN_WIDTH                           6U
+#define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_165
+#define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_165__LPI_WAKEUP_EN
+
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_MASK                 0x00010000U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN_WOSET                         0U
+#define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_165
+#define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_165__LPI_CTRL_REQ_EN
+
+#define LPDDR4__DENALI_CTL_166_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_MASK                 0x00000FFFU
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT_WIDTH                        12U
+#define LPDDR4__LPI_TIMER_COUNT__REG DENALI_CTL_166
+#define LPDDR4__LPI_TIMER_COUNT__FLD LPDDR4__DENALI_CTL_166__LPI_TIMER_COUNT
+
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_MASK              0x0FFF0000U
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT_WIDTH                     12U
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_166
+#define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_166__LPI_WAKEUP_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_167_READ_MASK                             0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK                            0x0F0F7F07U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_167__TDFI_LP_RESP_WIDTH                            3U
+#define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_167
+#define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_167__TDFI_LP_RESP
+
+#define LPDDR4__DENALI_CTL_167__LP_STATE_MASK                        0x00007F00U
+#define LPDDR4__DENALI_CTL_167__LP_STATE_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_167__LP_STATE_WIDTH                                7U
+#define LPDDR4__LP_STATE__REG DENALI_CTL_167
+#define LPDDR4__LP_STATE__FLD LPDDR4__DENALI_CTL_167__LP_STATE
+
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN_WIDTH                        4U
+#define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_167
+#define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_167__LP_AUTO_ENTRY_EN
+
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN_WIDTH                         4U
+#define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_167
+#define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_167__LP_AUTO_EXIT_EN
+
+#define LPDDR4__DENALI_CTL_168_READ_MASK                             0x000FFF07U
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK                            0x000FFF07U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_MASK             0x00000007U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN_WIDTH                     3U
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_168
+#define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_168__LP_AUTO_MEM_GATE_EN
+
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_MASK                 0x000FFF00U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE_WIDTH                        12U
+#define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_168
+#define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_168__LP_AUTO_PD_IDLE
+
+#define LPDDR4__DENALI_CTL_169_READ_MASK                             0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK                            0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_MASK           0x00000FFFU
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE_WIDTH                  12U
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_SHORT_IDLE
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_MASK            0x00FF0000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE_WIDTH                    8U
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_IDLE
+
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_MASK    0xFF000000U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_SHIFT           24U
+#define LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE_WIDTH            8U
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_169
+#define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_169__LP_AUTO_SR_LONG_MC_GATE_IDLE
+
+#define LPDDR4__DENALI_CTL_170_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_170
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_170
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_170__HW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_171_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_171
+#define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_171__HW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_171
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_171__LPC_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_172_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_172
+#define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_172__LPC_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_173_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_MASK               0x00000001U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN_WOSET                       0U
+#define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_CTRLUPD_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_MASK                0x00000100U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN_WOSET                        0U
+#define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_PHYUPD_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_MASK               0x00010000U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN_WOSET                       0U
+#define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_PHYMSTR_EN
+
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_MASK              0x01000000U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN_WOSET                      0U
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__REG DENALI_CTL_173
+#define LPDDR4__LPC_SR_EXIT_CMD_EN__FLD LPDDR4__DENALI_CTL_173__LPC_SR_EXIT_CMD_EN
+
+#define LPDDR4__DENALI_CTL_174_READ_MASK                             0x0101FF01U
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK                            0x0101FF01U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN_WOSET                            0U
+#define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_174
+#define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_174__LPC_SR_ZQ_EN
+
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_MASK               0x0001FF00U
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY_WIDTH                       9U
+#define LPDDR4__PWRDN_SHIFT_DELAY__REG DENALI_CTL_174
+#define LPDDR4__PWRDN_SHIFT_DELAY__FLD LPDDR4__DENALI_CTL_174__PWRDN_SHIFT_DELAY
+
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_174__DFS_ENABLE_WOSET                              0U
+#define LPDDR4__DFS_ENABLE__REG DENALI_CTL_174
+#define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_174__DFS_ENABLE
+
+#define LPDDR4__DENALI_CTL_175_READ_MASK                             0x00000107U
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK                            0x00000107U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_MASK                     0x00000007U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_175__DFS_DLL_OFF_WIDTH                             3U
+#define LPDDR4__DFS_DLL_OFF__REG DENALI_CTL_175
+#define LPDDR4__DFS_DLL_OFF__FLD LPDDR4__DENALI_CTL_175__DFS_DLL_OFF
+
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN_WOSET                    0U
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_175
+#define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_175__DFS_PHY_REG_WRITE_EN
+
+#define LPDDR4__DENALI_CTL_176_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR_WIDTH                 32U
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_176
+#define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_176__DFS_PHY_REG_WRITE_ADDR
+
+#define LPDDR4__DENALI_CTL_177_READ_MASK                             0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK                            0x03FFFF0FU
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK_WIDTH                  4U
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_177
+#define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_MASK
+
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_MASK          0x00FFFF00U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT_WIDTH                 16U
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_177
+#define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_177__DFS_PHY_REG_WRITE_WAIT
+
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY_WIDTH                        2U
+#define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_177
+#define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_177__CURRENT_REG_COPY
+
+#define LPDDR4__DENALI_CTL_178_READ_MASK                             0x00000303U
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK                            0x00000303U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_MASK                       0x00000003U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_178__INIT_FREQ_WIDTH                               2U
+#define LPDDR4__INIT_FREQ__REG DENALI_CTL_178
+#define LPDDR4__INIT_FREQ__FLD LPDDR4__DENALI_CTL_178__INIT_FREQ
+
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ_WIDTH                        2U
+#define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_178
+#define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_178__DFIBUS_BOOT_FREQ
+
+#define LPDDR4__DENALI_CTL_179_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_SHIFT               0U
+#define LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_179
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_179__DFS_PHY_REG_WRITE_DATA_F0
+
+#define LPDDR4__DENALI_CTL_180_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_SHIFT               0U
+#define LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_180
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_180__DFS_PHY_REG_WRITE_DATA_F1
+
+#define LPDDR4__DENALI_CTL_181_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_SHIFT               0U
+#define LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2_WIDTH              32U
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_181
+#define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_181__DFS_PHY_REG_WRITE_DATA_F2
+
+#define LPDDR4__DENALI_CTL_182_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_182
+#define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_182__TDFI_INIT_START_F0
+
+#define LPDDR4__DENALI_CTL_183_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_183
+#define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_183__TDFI_INIT_COMPLETE_F0
+
+#define LPDDR4__DENALI_CTL_184_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_184
+#define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_184__TDFI_INIT_START_F1
+
+#define LPDDR4__DENALI_CTL_185_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_185
+#define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_185__TDFI_INIT_COMPLETE_F1
+
+#define LPDDR4__DENALI_CTL_186_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_MASK              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2_WIDTH                     24U
+#define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_186
+#define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_186__TDFI_INIT_START_F2
+
+#define LPDDR4__DENALI_CTL_187_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2_WIDTH                  24U
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_187
+#define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_187__TDFI_INIT_COMPLETE_F2
+
+#define LPDDR4__DENALI_CTL_188_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_MASK                   0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_188__WRITE_MODEREG_WIDTH                          27U
+#define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_188
+#define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_188__WRITE_MODEREG
+
+#define LPDDR4__DENALI_CTL_189_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_189__MRW_STATUS_WIDTH                              8U
+#define LPDDR4__MRW_STATUS__REG DENALI_CTL_189
+#define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_189__MRW_STATUS
+
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_MASK                    0x01FFFF00U
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_189__READ_MODEREG_WIDTH                           17U
+#define LPDDR4__READ_MODEREG__REG DENALI_CTL_189
+#define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_189__READ_MODEREG
+
+#define LPDDR4__DENALI_CTL_190_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_MASK             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA_WIDTH                    24U
+#define LPDDR4__PERIPHERAL_MRR_DATA__REG DENALI_CTL_190
+#define LPDDR4__PERIPHERAL_MRR_DATA__FLD LPDDR4__DENALI_CTL_190__PERIPHERAL_MRR_DATA
+
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_MASK              0xFF000000U
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0_WIDTH                      8U
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_190
+#define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_190__AUTO_TEMPCHK_VAL_0
+
+#define LPDDR4__DENALI_CTL_191_READ_MASK                             0x000301FFU
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK                            0x000301FFU
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_MASK              0x000000FFU
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1_WIDTH                      8U
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_191
+#define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_191__AUTO_TEMPCHK_VAL_1
+
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG_WOSET                    0U
+#define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_191
+#define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_191__DISABLE_UPDATE_TVRCG
+
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC_WIDTH                      2U
+#define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_191
+#define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_191__MRW_DFS_UPDATE_FRC
+
+#define LPDDR4__DENALI_CTL_192_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_192
+#define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_192__TVRCG_ENABLE_F0
+
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_192
+#define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_192__TVRCG_DISABLE_F0
+
+#define LPDDR4__DENALI_CTL_193_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_193__TFC_F0_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_193__TFC_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_193__TFC_F0_WIDTH                                 10U
+#define LPDDR4__TFC_F0__REG DENALI_CTL_193
+#define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_193__TFC_F0
+
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_193__TCKFSPE_F0_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_193
+#define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_193__TCKFSPE_F0
+
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_193__TCKFSPX_F0_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_193
+#define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_193__TCKFSPX_F0
+
+#define LPDDR4__DENALI_CTL_194_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_194__TVREF_LONG_F0_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_194
+#define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_194__TVREF_LONG_F0
+
+#define LPDDR4__DENALI_CTL_195_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_195__TVRCG_ENABLE_F1
+
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_195
+#define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_195__TVRCG_DISABLE_F1
+
+#define LPDDR4__DENALI_CTL_196_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_196__TFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_196__TFC_F1_WIDTH                                 10U
+#define LPDDR4__TFC_F1__REG DENALI_CTL_196
+#define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_196__TFC_F1
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_196__TCKFSPE_F1_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_196__TCKFSPE_F1
+
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_196__TCKFSPX_F1_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_196
+#define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_196__TCKFSPX_F1
+
+#define LPDDR4__DENALI_CTL_197_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_197__TVREF_LONG_F1_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_197
+#define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_197__TVREF_LONG_F1
+
+#define LPDDR4__DENALI_CTL_198_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2_WIDTH                        10U
+#define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_198__TVRCG_ENABLE_F2
+
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2_WIDTH                       10U
+#define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_198
+#define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_198__TVRCG_DISABLE_F2
+
+#define LPDDR4__DENALI_CTL_199_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F2_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_199__TFC_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_199__TFC_F2_WIDTH                                 10U
+#define LPDDR4__TFC_F2__REG DENALI_CTL_199
+#define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_199__TFC_F2
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_199__TCKFSPE_F2_WIDTH                              5U
+#define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_199__TCKFSPE_F2
+
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_199__TCKFSPX_F2_WIDTH                              5U
+#define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_199
+#define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_199__TCKFSPX_F2
+
+#define LPDDR4__DENALI_CTL_200_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_MASK                   0x000FFFFFU
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_200__TVREF_LONG_F2_WIDTH                          20U
+#define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_200
+#define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_200__TVREF_LONG_F2
+
+#define LPDDR4__DENALI_CTL_201_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_201
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_SHIFT               16U
+#define LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_201
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_201__MRR_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_202_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_202
+#define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_202__MRR_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_SHIFT               16U
+#define LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_202
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_202__MRW_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_203_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_203
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_MASK        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_SHIFT               16U
+#define LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2_WIDTH               16U
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_203
+#define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_203__MRW_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_204_READ_MASK                             0x01FFFF01U
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK                            0x01FFFF01U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_204__MR4_DLL_RST_WOSET                             0U
+#define LPDDR4__MR4_DLL_RST__REG DENALI_CTL_204
+#define LPDDR4__MR4_DLL_RST__FLD LPDDR4__DENALI_CTL_204__MR4_DLL_RST
+
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_MASK                   0x01FFFF00U
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F0_0__REG DENALI_CTL_204
+#define LPDDR4__MR0_DATA_F0_0__FLD LPDDR4__DENALI_CTL_204__MR0_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_205_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_205
+#define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_205__MR1_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_206_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_206
+#define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_206__MR2_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_207_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F1_0__REG DENALI_CTL_207
+#define LPDDR4__MR0_DATA_F1_0__FLD LPDDR4__DENALI_CTL_207__MR0_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_208_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_208
+#define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_208__MR1_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_209_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_209
+#define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_209__MR2_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_210_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F2_0__REG DENALI_CTL_210
+#define LPDDR4__MR0_DATA_F2_0__FLD LPDDR4__DENALI_CTL_210__MR0_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_211_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_211
+#define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_211__MR1_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_212_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_212
+#define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_212__MR2_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_213_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F0_1__REG DENALI_CTL_213
+#define LPDDR4__MR0_DATA_F0_1__FLD LPDDR4__DENALI_CTL_213__MR0_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_214_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_214
+#define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_214__MR1_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_215_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_215
+#define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_215__MR2_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_216_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F1_1__REG DENALI_CTL_216
+#define LPDDR4__MR0_DATA_F1_1__FLD LPDDR4__DENALI_CTL_216__MR0_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_217_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_217
+#define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_217__MR1_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_218_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_218
+#define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_218__MR2_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_219_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR0_DATA_F2_1__REG DENALI_CTL_219
+#define LPDDR4__MR0_DATA_F2_1__FLD LPDDR4__DENALI_CTL_219__MR0_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_220_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_220
+#define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_220__MR1_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_221_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_221
+#define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_221__MR2_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_222_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0_WIDTH                        17U
+#define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_222
+#define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_222__MRSINGLE_DATA_0
+
+#define LPDDR4__DENALI_CTL_223_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_MASK                 0x0001FFFFU
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1_WIDTH                        17U
+#define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_223
+#define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_223__MRSINGLE_DATA_1
+
+#define LPDDR4__DENALI_CTL_224_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_224
+#define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_224__MR3_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_225_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_225
+#define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_225__MR3_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_226_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_226
+#define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_226__MR3_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_227_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_227
+#define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_227__MR3_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_228_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_228
+#define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_228__MR3_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_229_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_229
+#define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_229__MR3_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_230_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_230
+#define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_230__MR4_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_231_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_231
+#define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_231__MR4_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_232_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_232
+#define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_232__MR4_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_233_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_233
+#define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_233__MR4_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_234_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_234
+#define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_234__MR4_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_235_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_235
+#define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_235__MR4_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_236_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F0_0__REG DENALI_CTL_236
+#define LPDDR4__MR5_DATA_F0_0__FLD LPDDR4__DENALI_CTL_236__MR5_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_237_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F1_0__REG DENALI_CTL_237
+#define LPDDR4__MR5_DATA_F1_0__FLD LPDDR4__DENALI_CTL_237__MR5_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_238_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F2_0__REG DENALI_CTL_238
+#define LPDDR4__MR5_DATA_F2_0__FLD LPDDR4__DENALI_CTL_238__MR5_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_239_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F0_1__REG DENALI_CTL_239
+#define LPDDR4__MR5_DATA_F0_1__FLD LPDDR4__DENALI_CTL_239__MR5_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_240_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F1_1__REG DENALI_CTL_240
+#define LPDDR4__MR5_DATA_F1_1__FLD LPDDR4__DENALI_CTL_240__MR5_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_241_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR5_DATA_F2_1__REG DENALI_CTL_241
+#define LPDDR4__MR5_DATA_F2_1__FLD LPDDR4__DENALI_CTL_241__MR5_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_242_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F0_0__REG DENALI_CTL_242
+#define LPDDR4__MR6_DATA_F0_0__FLD LPDDR4__DENALI_CTL_242__MR6_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_243_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F1_0__REG DENALI_CTL_243
+#define LPDDR4__MR6_DATA_F1_0__FLD LPDDR4__DENALI_CTL_243__MR6_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_244_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F2_0__REG DENALI_CTL_244
+#define LPDDR4__MR6_DATA_F2_0__FLD LPDDR4__DENALI_CTL_244__MR6_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_245_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F0_1__REG DENALI_CTL_245
+#define LPDDR4__MR6_DATA_F0_1__FLD LPDDR4__DENALI_CTL_245__MR6_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_246_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F1_1__REG DENALI_CTL_246
+#define LPDDR4__MR6_DATA_F1_1__FLD LPDDR4__DENALI_CTL_246__MR6_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_247_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_247_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_MASK                   0x0001FFFFU
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1_WIDTH                          17U
+#define LPDDR4__MR6_DATA_F2_1__REG DENALI_CTL_247
+#define LPDDR4__MR6_DATA_F2_1__FLD LPDDR4__DENALI_CTL_247__MR6_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_247__MR8_DATA_0_WIDTH                              8U
+#define LPDDR4__MR8_DATA_0__REG DENALI_CTL_247
+#define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_247__MR8_DATA_0
+
+#define LPDDR4__DENALI_CTL_248_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_248_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_248__MR8_DATA_1_WIDTH                              8U
+#define LPDDR4__MR8_DATA_1__REG DENALI_CTL_248
+#define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_248__MR8_DATA_1
+
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F0_0__REG DENALI_CTL_248
+#define LPDDR4__MR10_DATA_F0_0__FLD LPDDR4__DENALI_CTL_248__MR10_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_249_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F1_0__REG DENALI_CTL_249
+#define LPDDR4__MR10_DATA_F1_0__FLD LPDDR4__DENALI_CTL_249__MR10_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_250_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F2_0__REG DENALI_CTL_250
+#define LPDDR4__MR10_DATA_F2_0__FLD LPDDR4__DENALI_CTL_250__MR10_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_251_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F0_1__REG DENALI_CTL_251
+#define LPDDR4__MR10_DATA_F0_1__FLD LPDDR4__DENALI_CTL_251__MR10_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_252_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F1_1__REG DENALI_CTL_252
+#define LPDDR4__MR10_DATA_F1_1__FLD LPDDR4__DENALI_CTL_252__MR10_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_253_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_253_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR10_DATA_F2_1__REG DENALI_CTL_253
+#define LPDDR4__MR10_DATA_F2_1__FLD LPDDR4__DENALI_CTL_253__MR10_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_253
+#define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_253__MR11_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_254_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_254
+#define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_254__MR11_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_255_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_255_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1_WIDTH                          8U
+#define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_255
+#define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_255__MR11_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_255
+#define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_255__MR12_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_256_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_256
+#define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_256__MR12_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_257_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_257
+#define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_257__MR12_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_258_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_258
+#define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_258__MR12_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_259_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_259
+#define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_259__MR12_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_260_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_260
+#define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_260__MR12_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_261_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_MASK                     0x0001FFFFU
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_261__MR13_DATA_0_WIDTH                            17U
+#define LPDDR4__MR13_DATA_0__REG DENALI_CTL_261
+#define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_261__MR13_DATA_0
+
+#define LPDDR4__DENALI_CTL_262_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_MASK                     0x0001FFFFU
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_262__MR13_DATA_1_WIDTH                            17U
+#define LPDDR4__MR13_DATA_1__REG DENALI_CTL_262
+#define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_262__MR13_DATA_1
+
+#define LPDDR4__DENALI_CTL_263_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_263
+#define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_263__MR14_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_264_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_264
+#define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_264__MR14_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_265_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_265
+#define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_265__MR14_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_266_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_266
+#define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_266__MR14_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_267_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_267
+#define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_267__MR14_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_268_READ_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_268_WRITE_MASK                            0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_268
+#define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_268__MR14_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_268__MR16_DATA_0_WIDTH                             8U
+#define LPDDR4__MR16_DATA_0__REG DENALI_CTL_268
+#define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_268__MR16_DATA_0
+
+#define LPDDR4__DENALI_CTL_269_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_269_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_269__MR16_DATA_1_WIDTH                             8U
+#define LPDDR4__MR16_DATA_1__REG DENALI_CTL_269
+#define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_269__MR16_DATA_1
+
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_0_WIDTH                             8U
+#define LPDDR4__MR17_DATA_0__REG DENALI_CTL_269
+#define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_269__MR17_DATA_0
+
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_269__MR17_DATA_1_WIDTH                             8U
+#define LPDDR4__MR17_DATA_1__REG DENALI_CTL_269
+#define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_269__MR17_DATA_1
+
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_MASK                     0xFF000000U
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_269__MR20_DATA_0_WIDTH                             8U
+#define LPDDR4__MR20_DATA_0__REG DENALI_CTL_269
+#define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_269__MR20_DATA_0
+
+#define LPDDR4__DENALI_CTL_270_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_270_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_270__MR20_DATA_1_WIDTH                             8U
+#define LPDDR4__MR20_DATA_1__REG DENALI_CTL_270
+#define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_270__MR20_DATA_1
+
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_MASK                  0x01FFFF00U
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_270
+#define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_270__MR22_DATA_F0_0
+
+#define LPDDR4__DENALI_CTL_271_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_271
+#define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_271__MR22_DATA_F1_0
+
+#define LPDDR4__DENALI_CTL_272_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_272
+#define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_272__MR22_DATA_F2_0
+
+#define LPDDR4__DENALI_CTL_273_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_273
+#define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_273__MR22_DATA_F0_1
+
+#define LPDDR4__DENALI_CTL_274_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_274
+#define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_274__MR22_DATA_F1_1
+
+#define LPDDR4__DENALI_CTL_275_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275_WRITE_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_MASK                  0x0001FFFFU
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1_WIDTH                         17U
+#define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_275
+#define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_275__MR22_DATA_F2_1
+
+#define LPDDR4__DENALI_CTL_276_READ_MASK                             0x0101FFFFU
+#define LPDDR4__DENALI_CTL_276_WRITE_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_MASK                       0x0001FFFFU
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_276__MR23_DATA_WIDTH                              17U
+#define LPDDR4__MR23_DATA__REG DENALI_CTL_276
+#define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_276__MR23_DATA
+
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_MASK            0x01000000U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_276
+#define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_276__MR_FSP_DATA_VALID_F0
+
+#define LPDDR4__DENALI_CTL_277_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_277_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_277
+#define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F1
+
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2_WOSET                    0U
+#define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_277
+#define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_277__MR_FSP_DATA_VALID_F2
+
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_MASK           0x00010000U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE_WOSET                   0U
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__REG DENALI_CTL_277
+#define LPDDR4__DFS_FSP_INSYNC_ACTIVE__FLD LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_ACTIVE
+
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_SHIFT                24U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE_WOSET                 0U
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__REG DENALI_CTL_277
+#define LPDDR4__DFS_FSP_INSYNC_INACTIVE__FLD LPDDR4__DENALI_CTL_277__DFS_FSP_INSYNC_INACTIVE
+
+#define LPDDR4__DENALI_CTL_278_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_278_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_MASK              0x00000001U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW_WOSET                      0U
+#define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_278
+#define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_278__FSP_PHY_UPDATE_MRW
+
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_MASK            0x00000100U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP_WOSET                    0U
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_278
+#define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_278__DFS_ALWAYS_WRITE_FSP
+
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_278__FSP_STATUS_WOSET                              0U
+#define LPDDR4__FSP_STATUS__REG DENALI_CTL_278
+#define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_278__FSP_STATUS
+
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT_WOSET                          0U
+#define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_278
+#define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_278__FSP_OP_CURRENT
+
+#define LPDDR4__DENALI_CTL_279_READ_MASK                             0x03010101U
+#define LPDDR4__DENALI_CTL_279_WRITE_MASK                            0x03010101U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT_WOSET                          0U
+#define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_279
+#define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_279__FSP_WR_CURRENT
+
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID_WOSET                          0U
+#define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_279
+#define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_279__FSP0_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID_WOSET                          0U
+#define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_279
+#define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_279__FSP1_FRC_VALID
+
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_MASK                        0x03000000U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_279__FSP0_FRC_WIDTH                                2U
+#define LPDDR4__FSP0_FRC__REG DENALI_CTL_279
+#define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_279__FSP0_FRC
+
+#define LPDDR4__DENALI_CTL_280_READ_MASK                             0x3F030003U
+#define LPDDR4__DENALI_CTL_280_WRITE_MASK                            0x3F030003U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_MASK                        0x00000003U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_280__FSP1_FRC_WIDTH                                2U
+#define LPDDR4__FSP1_FRC__REG DENALI_CTL_280
+#define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_280__FSP1_FRC
+
+#define LPDDR4__DENALI_CTL_280__BIST_GO_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_280__BIST_GO_WOSET                                 0U
+#define LPDDR4__BIST_GO__REG DENALI_CTL_280
+#define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_280__BIST_GO
+
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_MASK                     0x00030000U
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_280__BIST_RESULT_WIDTH                             2U
+#define LPDDR4__BIST_RESULT__REG DENALI_CTL_280
+#define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_280__BIST_RESULT
+
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_MASK                      0x3F000000U
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_280__ADDR_SPACE_WIDTH                              6U
+#define LPDDR4__ADDR_SPACE__REG DENALI_CTL_280
+#define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_280__ADDR_SPACE
+
+#define LPDDR4__DENALI_CTL_281_READ_MASK                             0x00000101U
+#define LPDDR4__DENALI_CTL_281_WRITE_MASK                            0x00000101U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK_WOSET                         0U
+#define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_281
+#define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_281__BIST_DATA_CHECK
+
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_MASK                 0x00000100U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK_WOSET                         0U
+#define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_281
+#define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_281__BIST_ADDR_CHECK
+
+#define LPDDR4__DENALI_CTL_282_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0_WIDTH                   32U
+#define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_282
+#define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_282__BIST_START_ADDRESS_0
+
+#define LPDDR4__DENALI_CTL_283_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_283_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_MASK            0x00000001U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1_WOSET                    0U
+#define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_283
+#define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_283__BIST_START_ADDRESS_1
+
+#define LPDDR4__DENALI_CTL_284_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_284__BIST_DATA_MASK_WIDTH                         32U
+#define LPDDR4__BIST_DATA_MASK__REG DENALI_CTL_284
+#define LPDDR4__BIST_DATA_MASK__FLD LPDDR4__DENALI_CTL_284__BIST_DATA_MASK
+
+#define LPDDR4__DENALI_CTL_285_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_285_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_MASK                  0x00000007U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_285__BIST_TEST_MODE_WIDTH                          3U
+#define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_285
+#define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_285__BIST_TEST_MODE
+
+#define LPDDR4__DENALI_CTL_286_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_286
+#define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_286__BIST_DATA_PATTERN_0
+
+#define LPDDR4__DENALI_CTL_287_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1_WIDTH                    32U
+#define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_287
+#define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_287__BIST_DATA_PATTERN_1
+
+#define LPDDR4__DENALI_CTL_288_READ_MASK                             0x000FFF01U
+#define LPDDR4__DENALI_CTL_288_WRITE_MASK                            0x000FFF01U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_288__BIST_RET_STATE_WOSET                          0U
+#define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_288
+#define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_288__BIST_RET_STATE
+
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_MASK                   0x000FFF00U
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_288__BIST_ERR_STOP_WIDTH                          12U
+#define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_288
+#define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_288__BIST_ERR_STOP
+
+#define LPDDR4__DENALI_CTL_289_READ_MASK                             0x1F000FFFU
+#define LPDDR4__DENALI_CTL_289_WRITE_MASK                            0x1F000FFFU
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_MASK                  0x00000FFFU
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT_WIDTH                         12U
+#define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_289
+#define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_289__BIST_ERR_COUNT
+
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_MASK             0x00010000U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT_WOSET                     0U
+#define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_289
+#define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_289__BIST_RET_STATE_EXIT
+
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_MASK                 0x1F000000U
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK_WIDTH                         5U
+#define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_289
+#define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_289__LONG_COUNT_MASK
+
+#define LPDDR4__DENALI_CTL_290_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_290_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_MASK             0x0000001FU
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD_WIDTH                     5U
+#define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_290
+#define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_290__AREF_NORM_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_MASK             0x00001F00U
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD_WIDTH                     5U
+#define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_290
+#define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_290__AREF_HIGH_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_MASK                0x001F0000U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT_WIDTH                        5U
+#define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_290
+#define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_290__AREF_MAX_DEFICIT
+
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_MASK                 0x1F000000U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT_WIDTH                         5U
+#define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_290
+#define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_290__AREF_MAX_CREDIT
+
+#define LPDDR4__DENALI_CTL_291_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_291_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI_WIDTH                  4U
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_291
+#define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_291__AREF_CMD_MAX_PER_TREFI
+
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD_WIDTH                      3U
+#define LPDDR4__ZQCS_OPT_THRESHOLD__REG DENALI_CTL_291
+#define LPDDR4__ZQCS_OPT_THRESHOLD__FLD LPDDR4__DENALI_CTL_291__ZQCS_OPT_THRESHOLD
+
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__REG DENALI_CTL_291
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_291__ZQ_CALSTART_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_292_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_SHIFT           0U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_292
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_292__ZQ_CALSTART_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT          16U
+#define LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__REG DENALI_CTL_292
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_292__ZQ_CALLATCH_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_293_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_293
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_293__ZQ_CS_NORM_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_293
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_293__ZQ_CS_HIGH_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_294_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_294_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_294
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_294__ZQ_CALSTART_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_294
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_294__ZQ_CALLATCH_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_295_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_295
+#define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_295__ZQ_CS_TIMEOUT_F0
+
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_295
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_295__ZQ_PROMOTE_THRESHOLD_F0
+
+#define LPDDR4__DENALI_CTL_296_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_296_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_296
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_296__ZQ_CALSTART_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT          16U
+#define LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__REG DENALI_CTL_296
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_296__ZQ_CALSTART_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_297_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_SHIFT           0U
+#define LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_297
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_297__ZQ_CALLATCH_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_297
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_297__ZQ_CS_NORM_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_298_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_298__ZQ_CS_HIGH_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_298
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_298__ZQ_CALSTART_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_299_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_299__ZQ_CALLATCH_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_299
+#define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_299__ZQ_CS_TIMEOUT_F1
+
+#define LPDDR4__DENALI_CTL_300_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_300
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_300__ZQ_PROMOTE_THRESHOLD_F1
+
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__REG DENALI_CTL_300
+#define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_300__ZQ_CALSTART_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_301_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_MASK   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_SHIFT           0U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_301
+#define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_301__ZQ_CALSTART_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT          16U
+#define LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH          16U
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__REG DENALI_CTL_301
+#define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_301__ZQ_CALLATCH_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_302_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_302__ZQ_CS_NORM_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_302
+#define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_302__ZQ_CS_HIGH_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_303_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_MASK          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_303__ZQ_CALSTART_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2_WIDTH                 16U
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_303
+#define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_303__ZQ_CALLATCH_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_304_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2_WIDTH                       16U
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_304
+#define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_304__ZQ_CS_TIMEOUT_F2
+
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_MASK         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2_WIDTH                16U
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_304
+#define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_304__ZQ_PROMOTE_THRESHOLD_F2
+
+#define LPDDR4__DENALI_CTL_305_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_305_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_MASK               0x000000FFU
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG_WIDTH                       8U
+#define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_305
+#define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_305__TIMEOUT_TIMER_LOG
+
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_MASK                       0x000FFF00U
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_305__ZQINIT_F0_WIDTH                              12U
+#define LPDDR4__ZQINIT_F0__REG DENALI_CTL_305
+#define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_305__ZQINIT_F0
+
+#define LPDDR4__DENALI_CTL_306_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_306_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_306__ZQCL_F0_WIDTH                                12U
+#define LPDDR4__ZQCL_F0__REG DENALI_CTL_306
+#define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_306__ZQCL_F0
+
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_306__ZQCS_F0_WIDTH                                12U
+#define LPDDR4__ZQCS_F0__REG DENALI_CTL_306
+#define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_306__ZQCS_F0
+
+#define LPDDR4__DENALI_CTL_307_READ_MASK                             0x007F0FFFU
+#define LPDDR4__DENALI_CTL_307_WRITE_MASK                            0x007F0FFFU
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_307__TZQCAL_F0_WIDTH                              12U
+#define LPDDR4__TZQCAL_F0__REG DENALI_CTL_307
+#define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_307__TZQCAL_F0
+
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_MASK                       0x007F0000U
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_307__TZQLAT_F0_WIDTH                               7U
+#define LPDDR4__TZQLAT_F0__REG DENALI_CTL_307
+#define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_307__TZQLAT_F0
+
+#define LPDDR4__DENALI_CTL_308_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_308_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_308__ZQINIT_F1_WIDTH                              12U
+#define LPDDR4__ZQINIT_F1__REG DENALI_CTL_308
+#define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_308__ZQINIT_F1
+
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_308__ZQCL_F1_WIDTH                                12U
+#define LPDDR4__ZQCL_F1__REG DENALI_CTL_308
+#define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_308__ZQCL_F1
+
+#define LPDDR4__DENALI_CTL_309_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_309_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_309__ZQCS_F1_WIDTH                                12U
+#define LPDDR4__ZQCS_F1__REG DENALI_CTL_309
+#define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_309__ZQCS_F1
+
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_MASK                       0x0FFF0000U
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_309__TZQCAL_F1_WIDTH                              12U
+#define LPDDR4__TZQCAL_F1__REG DENALI_CTL_309
+#define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_309__TZQCAL_F1
+
+#define LPDDR4__DENALI_CTL_310_READ_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_CTL_310_WRITE_MASK                            0x000FFF7FU
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_MASK                       0x0000007FU
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_310__TZQLAT_F1_WIDTH                               7U
+#define LPDDR4__TZQLAT_F1__REG DENALI_CTL_310
+#define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_310__TZQLAT_F1
+
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_MASK                       0x000FFF00U
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_310__ZQINIT_F2_WIDTH                              12U
+#define LPDDR4__ZQINIT_F2__REG DENALI_CTL_310
+#define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_310__ZQINIT_F2
+
+#define LPDDR4__DENALI_CTL_311_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_311_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_311__ZQCL_F2_WIDTH                                12U
+#define LPDDR4__ZQCL_F2__REG DENALI_CTL_311
+#define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_311__ZQCL_F2
+
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_311__ZQCS_F2_WIDTH                                12U
+#define LPDDR4__ZQCS_F2__REG DENALI_CTL_311
+#define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_311__ZQCS_F2
+
+#define LPDDR4__DENALI_CTL_312_READ_MASK                             0x037F0FFFU
+#define LPDDR4__DENALI_CTL_312_WRITE_MASK                            0x037F0FFFU
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_312__TZQCAL_F2_WIDTH                              12U
+#define LPDDR4__TZQCAL_F2__REG DENALI_CTL_312
+#define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_312__TZQCAL_F2
+
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_MASK                       0x007F0000U
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_312__TZQLAT_F2_WIDTH                               7U
+#define LPDDR4__TZQLAT_F2__REG DENALI_CTL_312
+#define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_312__TZQLAT_F2
+
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_MASK       0x03000000U
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_SHIFT              24U
+#define LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP_WIDTH               2U
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_312
+#define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_312__ZQ_SW_REQ_START_LATCH_MAP
+
+#define LPDDR4__DENALI_CTL_313_READ_MASK                             0x0FFF0100U
+#define LPDDR4__DENALI_CTL_313_WRITE_MASK                            0x0FFF0100U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_MASK                          0x0000000FU
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_WIDTH                                  4U
+#define LPDDR4__ZQ_REQ__REG DENALI_CTL_313
+#define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_313__ZQ_REQ
+
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING_WOSET                          0U
+#define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_313
+#define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_313__ZQ_REQ_PENDING
+
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_MASK                      0x0FFF0000U
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_313__ZQRESET_F0_WIDTH                             12U
+#define LPDDR4__ZQRESET_F0__REG DENALI_CTL_313
+#define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_313__ZQRESET_F0
+
+#define LPDDR4__DENALI_CTL_314_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_MASK                      0x00000FFFU
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F1_WIDTH                             12U
+#define LPDDR4__ZQRESET_F1__REG DENALI_CTL_314
+#define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_314__ZQRESET_F1
+
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_MASK                      0x0FFF0000U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_314__ZQRESET_F2_WIDTH                             12U
+#define LPDDR4__ZQRESET_F2__REG DENALI_CTL_314
+#define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_314__ZQRESET_F2
+
+#define LPDDR4__DENALI_CTL_315_READ_MASK                             0x03030101U
+#define LPDDR4__DENALI_CTL_315_WRITE_MASK                            0x03030101U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_315__NO_ZQ_INIT_WOSET                              0U
+#define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_315
+#define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_315__NO_ZQ_INIT
+
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_315__ZQCS_ROTATE_WOSET                             0U
+#define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_315
+#define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_315__ZQCS_ROTATE
+
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_MASK              0x00030000U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_315
+#define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_315__ZQ_CAL_START_MAP_0
+
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_MASK              0x03000000U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_315
+#define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_315__ZQ_CAL_LATCH_MAP_0
+
+#define LPDDR4__DENALI_CTL_316_READ_MASK                             0x03030303U
+#define LPDDR4__DENALI_CTL_316_WRITE_MASK                            0x03030303U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_MASK              0x00000003U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_316
+#define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_316__ZQ_CAL_START_MAP_1
+
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_MASK              0x00000300U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1_WIDTH                      2U
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_316
+#define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_316__ZQ_CAL_LATCH_MAP_1
+
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_MASK                     0x00030000U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_0_WIDTH                             2U
+#define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_316
+#define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_316__BANK_DIFF_0
+
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_MASK                     0x03000000U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_316__BANK_DIFF_1_WIDTH                             2U
+#define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_316
+#define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_316__BANK_DIFF_1
+
+#define LPDDR4__DENALI_CTL_317_READ_MASK                             0x0F0F0707U
+#define LPDDR4__DENALI_CTL_317_WRITE_MASK                            0x0F0F0707U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_MASK                      0x00000007U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_0_WIDTH                              3U
+#define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_317
+#define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_317__ROW_DIFF_0
+
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_MASK                      0x00000700U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_317__ROW_DIFF_1_WIDTH                              3U
+#define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_317
+#define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_317__ROW_DIFF_1
+
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_MASK                      0x000F0000U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_0_WIDTH                              4U
+#define LPDDR4__COL_DIFF_0__REG DENALI_CTL_317
+#define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_317__COL_DIFF_0
+
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_MASK                      0x0F000000U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_317__COL_DIFF_1_WIDTH                              4U
+#define LPDDR4__COL_DIFF_1__REG DENALI_CTL_317
+#define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_317__COL_DIFF_1
+
+#define LPDDR4__DENALI_CTL_318_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_318_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0_WIDTH                         16U
+#define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_318
+#define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_318__CS_VAL_LOWER_0
+
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0_WIDTH                         16U
+#define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_318
+#define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_318__CS_VAL_UPPER_0
+
+#define LPDDR4__DENALI_CTL_319_READ_MASK                             0x00FFFF03U
+#define LPDDR4__DENALI_CTL_319_WRITE_MASK                            0x00FFFF03U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_MASK                 0x00000003U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_319__ROW_START_VAL_0_WIDTH                         2U
+#define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_319
+#define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_319__ROW_START_VAL_0
+
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_MASK                        0x00FFFF00U
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_319__CS_MSK_0_WIDTH                               16U
+#define LPDDR4__CS_MSK_0__REG DENALI_CTL_319
+#define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_319__CS_MSK_0
+
+#define LPDDR4__DENALI_CTL_320_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_320_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1_WIDTH                         16U
+#define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_320
+#define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_320__CS_VAL_LOWER_1
+
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1_WIDTH                         16U
+#define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_320
+#define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_320__CS_VAL_UPPER_1
+
+#define LPDDR4__DENALI_CTL_321_READ_MASK                             0x03FFFF03U
+#define LPDDR4__DENALI_CTL_321_WRITE_MASK                            0x03FFFF03U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_MASK                 0x00000003U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_321__ROW_START_VAL_1_WIDTH                         2U
+#define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_321
+#define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_321__ROW_START_VAL_1
+
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_MASK                        0x00FFFF00U
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_321__CS_MSK_1_WIDTH                               16U
+#define LPDDR4__CS_MSK_1__REG DENALI_CTL_321
+#define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_321__CS_MSK_1
+
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_MASK                 0x03000000U
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2_WIDTH                         2U
+#define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_321
+#define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_321__CS_MAP_NON_POW2
+
+#define LPDDR4__DENALI_CTL_322_READ_MASK                             0x1F011F01U
+#define LPDDR4__DENALI_CTL_322_WRITE_MASK                            0x1F011F01U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN_WOSET                        0U
+#define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_322
+#define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_322__CS_LOWER_ADDR_EN
+
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_MASK                    0x00001F00U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED8_WIDTH                            5U
+#define LPDDR4__MC_RESERVED8__REG DENALI_CTL_322
+#define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_322__MC_RESERVED8
+
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_322__MC_RESERVED9_WOSET                            0U
+#define LPDDR4__MC_RESERVED9__REG DENALI_CTL_322
+#define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_322__MC_RESERVED9
+
+#define LPDDR4__DENALI_CTL_322__APREBIT_MASK                         0x1F000000U
+#define LPDDR4__DENALI_CTL_322__APREBIT_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_322__APREBIT_WIDTH                                 5U
+#define LPDDR4__APREBIT__REG DENALI_CTL_322
+#define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_322__APREBIT
+
+#define LPDDR4__DENALI_CTL_323_READ_MASK                             0x0101FFFFU
+#define LPDDR4__DENALI_CTL_323_WRITE_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_MASK                       0x000000FFU
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_323__AGE_COUNT_WIDTH                               8U
+#define LPDDR4__AGE_COUNT__REG DENALI_CTL_323
+#define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_323__AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT_WIDTH                       8U
+#define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_323
+#define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_323__COMMAND_AGE_COUNT
+
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_323__ADDR_CMP_EN_WOSET                             0U
+#define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_323
+#define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_323__ADDR_CMP_EN
+
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_MASK          0x01000000U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS_WOSET                  0U
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_323
+#define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_323__ADDR_COLLISION_MPM_DIS
+
+#define LPDDR4__DENALI_CTL_324_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_324_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN_WOSET                           0U
+#define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_324
+#define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_324__BANK_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_324__PLACEMENT_EN_WOSET                            0U
+#define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_324
+#define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_324__PLACEMENT_EN
+
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_324__PRIORITY_EN_WOSET                             0U
+#define LPDDR4__PRIORITY_EN__REG DENALI_CTL_324
+#define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_324__PRIORITY_EN
+
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_324__RW_SAME_EN_WOSET                              0U
+#define LPDDR4__RW_SAME_EN__REG DENALI_CTL_324
+#define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_324__RW_SAME_EN
+
+#define LPDDR4__DENALI_CTL_325_READ_MASK                             0x03010101U
+#define LPDDR4__DENALI_CTL_325_WRITE_MASK                            0x03010101U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN_WOSET                         0U
+#define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_325
+#define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_325__RW_SAME_PAGE_EN
+
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_325__CS_SAME_EN_WOSET                              0U
+#define LPDDR4__CS_SAME_EN__REG DENALI_CTL_325
+#define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_325__CS_SAME_EN
+
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN_WOSET                            0U
+#define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_325
+#define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_325__W2R_SPLIT_EN
+
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_MASK 0x03000000U
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_SHIFT        24U
+#define LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT_WIDTH         2U
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__REG DENALI_CTL_325
+#define LPDDR4__DISABLE_RW_GROUP_W_BNK_CONFLICT__FLD LPDDR4__DENALI_CTL_325__DISABLE_RW_GROUP_W_BNK_CONFLICT
+
+#define LPDDR4__DENALI_CTL_326_READ_MASK                             0x0301011FU
+#define LPDDR4__DENALI_CTL_326_WRITE_MASK                            0x0301011FU
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_MASK       0x0000001FU
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_SHIFT               0U
+#define LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE_WIDTH               5U
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_326
+#define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_326__NUM_Q_ENTRIES_ACT_DISABLE
+
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_MASK                         0x00000100U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_326__SWAP_EN_WOSET                                 0U
+#define LPDDR4__SWAP_EN__REG DENALI_CTL_326
+#define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_326__SWAP_EN
+
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_MASK           0x00010000U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE_WOSET                   0U
+#define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_326
+#define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_326__DISABLE_RD_INTERLEAVE
+
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_MASK                0x03000000U
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD_WIDTH                        2U
+#define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_326
+#define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_326__INHIBIT_DRAM_CMD
+
+#define LPDDR4__DENALI_CTL_327_READ_MASK                             0x07010F03U
+#define LPDDR4__DENALI_CTL_327_WRITE_MASK                            0x07010F03U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_MASK                          0x00000003U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_327__CS_MAP_WIDTH                                  2U
+#define LPDDR4__CS_MAP__REG DENALI_CTL_327
+#define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_327__CS_MAP
+
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_MASK                0x00000F00U
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT_WIDTH                        4U
+#define LPDDR4__BURST_ON_FLY_BIT__REG DENALI_CTL_327
+#define LPDDR4__BURST_ON_FLY_BIT__FLD LPDDR4__DENALI_CTL_327__BURST_ON_FLY_BIT
+
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION_WOSET                        0U
+#define LPDDR4__MEM_DP_REDUCTION__REG DENALI_CTL_327
+#define LPDDR4__MEM_DP_REDUCTION__FLD LPDDR4__DENALI_CTL_327__MEM_DP_REDUCTION
+
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_MASK                 0x07000000U
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0_WIDTH                         3U
+#define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_327
+#define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_327__MEMDATA_RATIO_0
+
+#define LPDDR4__DENALI_CTL_328_READ_MASK                             0x03030307U
+#define LPDDR4__DENALI_CTL_328_WRITE_MASK                            0x03030307U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1_WIDTH                         3U
+#define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_328
+#define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_328__MEMDATA_RATIO_1
+
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_MASK               0x00000300U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0_WIDTH                       2U
+#define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_328
+#define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_MASK               0x00030000U
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0_WIDTH                       2U
+#define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_328
+#define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_328__DEVICE1_BYTE0_CS0
+
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_MASK               0x03000000U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1_WIDTH                       2U
+#define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_328
+#define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_328__DEVICE0_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_329_READ_MASK                             0x03011F03U
+#define LPDDR4__DENALI_CTL_329_WRITE_MASK                            0x03011F03U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_MASK               0x00000003U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1_WIDTH                       2U
+#define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_329
+#define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_329__DEVICE1_BYTE0_CS1
+
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_329__Q_FULLNESS_WIDTH                              5U
+#define LPDDR4__Q_FULLNESS__REG DENALI_CTL_329
+#define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_329__Q_FULLNESS
+
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_MASK                 0x00010000U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT_WOSET                         0U
+#define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_329
+#define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_329__IN_ORDER_ACCEPT
+
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_MASK                    0x03000000U
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_329__WR_ORDER_REQ_WIDTH                            2U
+#define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_329
+#define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_329__WR_ORDER_REQ
+
+#define LPDDR4__DENALI_CTL_330_READ_MASK                             0x01010001U
+#define LPDDR4__DENALI_CTL_330_WRITE_MASK                            0x01010001U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY_WOSET                         0U
+#define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_330
+#define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_330__CONTROLLER_BUSY
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_WOSET                             0U
+#define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_REQ
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_MASK         0x00010000U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_SHIFT                16U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN_WOSET                 0U
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_REQ_PER_AREF_EN
+
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_MASK          0x01000000U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE_WOSET                  0U
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_330
+#define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_330__CTRLUPD_AREF_HP_ENABLE
+
+#define LPDDR4__DENALI_CTL_331_READ_MASK                             0x01030303U
+#define LPDDR4__DENALI_CTL_331_WRITE_MASK                            0x01030303U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_MASK             0x00000003U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F0
+
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_MASK             0x00000300U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F1
+
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_MASK             0x00030000U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2_WIDTH                     2U
+#define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_331
+#define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_331__PREAMBLE_SUPPORT_F2
+
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_SHIFT                24U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN_WOSET                 0U
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_331
+#define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_331__RD_PREAMBLE_TRAINING_EN
+
+#define LPDDR4__DENALI_CTL_332_READ_MASK                             0x00070101U
+#define LPDDR4__DENALI_CTL_332_WRITE_MASK                            0x00070101U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_332__WR_DBI_EN_WOSET                               0U
+#define LPDDR4__WR_DBI_EN__REG DENALI_CTL_332
+#define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_332__WR_DBI_EN
+
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_332__RD_DBI_EN_WOSET                               0U
+#define LPDDR4__RD_DBI_EN__REG DENALI_CTL_332
+#define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_332__RD_DBI_EN
+
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_MASK                       0x00070000U
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_332__DFI_ERROR_WIDTH                               3U
+#define LPDDR4__DFI_ERROR__REG DENALI_CTL_332
+#define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_332__DFI_ERROR
+
+#define LPDDR4__DENALI_CTL_333_READ_MASK                             0x00010FFFU
+#define LPDDR4__DENALI_CTL_333_WRITE_MASK                            0x00010FFFU
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_MASK                  0x00000FFFU
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO_WIDTH                         12U
+#define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_333
+#define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_333__DFI_ERROR_INFO
+
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_333__BG_ROTATE_EN_WOSET                            0U
+#define LPDDR4__BG_ROTATE_EN__REG DENALI_CTL_333
+#define LPDDR4__BG_ROTATE_EN__FLD LPDDR4__DENALI_CTL_333__BG_ROTATE_EN
+
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_333__MC_RESERVED10_WOSET                           0U
+#define LPDDR4__MC_RESERVED10__REG DENALI_CTL_333
+#define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_333__MC_RESERVED10
+
+#define LPDDR4__DENALI_CTL_334_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER_WIDTH                      32U
+#define LPDDR4__INT_STATUS_MASTER__REG DENALI_CTL_334
+#define LPDDR4__INT_STATUS_MASTER__FLD LPDDR4__DENALI_CTL_334__INT_STATUS_MASTER
+
+#define LPDDR4__DENALI_CTL_335_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_335__INT_MASK_MASTER_WIDTH                        32U
+#define LPDDR4__INT_MASK_MASTER__REG DENALI_CTL_335
+#define LPDDR4__INT_MASK_MASTER__FLD LPDDR4__DENALI_CTL_335__INT_MASK_MASTER
+
+#define LPDDR4__DENALI_CTL_336_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT_WIDTH                     32U
+#define LPDDR4__INT_STATUS_TIMEOUT__REG DENALI_CTL_336
+#define LPDDR4__INT_STATUS_TIMEOUT__FLD LPDDR4__DENALI_CTL_336__INT_STATUS_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_337_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_337__MC_RESERVED11_WIDTH                          16U
+#define LPDDR4__MC_RESERVED11__REG DENALI_CTL_337
+#define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_337__MC_RESERVED11
+
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_MASK             0xFFFF0000U
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER_WIDTH                    16U
+#define LPDDR4__INT_STATUS_LOWPOWER__REG DENALI_CTL_337
+#define LPDDR4__INT_STATUS_LOWPOWER__FLD LPDDR4__DENALI_CTL_337__INT_STATUS_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_338_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED12_WIDTH                          16U
+#define LPDDR4__MC_RESERVED12__REG DENALI_CTL_338
+#define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_338__MC_RESERVED12
+
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_338__MC_RESERVED13_WIDTH                          16U
+#define LPDDR4__MC_RESERVED13__REG DENALI_CTL_338
+#define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_338__MC_RESERVED13
+
+#define LPDDR4__DENALI_CTL_339_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING_WIDTH                    32U
+#define LPDDR4__INT_STATUS_TRAINING__REG DENALI_CTL_339
+#define LPDDR4__INT_STATUS_TRAINING__FLD LPDDR4__DENALI_CTL_339__INT_STATUS_TRAINING
+
+#define LPDDR4__DENALI_CTL_340_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF_WIDTH                      32U
+#define LPDDR4__INT_STATUS_USERIF__REG DENALI_CTL_340
+#define LPDDR4__INT_STATUS_USERIF__FLD LPDDR4__DENALI_CTL_340__INT_STATUS_USERIF
+
+#define LPDDR4__DENALI_CTL_341_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_341_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_MASK                 0x0000FFFFU
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_MISC_WIDTH                        16U
+#define LPDDR4__INT_STATUS_MISC__REG DENALI_CTL_341
+#define LPDDR4__INT_STATUS_MISC__FLD LPDDR4__DENALI_CTL_341__INT_STATUS_MISC
+
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_341__INT_STATUS_BIST_WIDTH                         8U
+#define LPDDR4__INT_STATUS_BIST__REG DENALI_CTL_341
+#define LPDDR4__INT_STATUS_BIST__FLD LPDDR4__DENALI_CTL_341__INT_STATUS_BIST
+
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_341__MC_RESERVED14_WIDTH                           8U
+#define LPDDR4__MC_RESERVED14__REG DENALI_CTL_341
+#define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_341__MC_RESERVED14
+
+#define LPDDR4__DENALI_CTL_342_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_DFI_WIDTH                          8U
+#define LPDDR4__INT_STATUS_DFI__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_DFI__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_DFI
+
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED15_WIDTH                           8U
+#define LPDDR4__MC_RESERVED15__REG DENALI_CTL_342
+#define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED15
+
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ_WIDTH                         8U
+#define LPDDR4__INT_STATUS_FREQ__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_FREQ__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_FREQ
+
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_MASK                 0xFF000000U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_342__INT_STATUS_INIT_WIDTH                         8U
+#define LPDDR4__INT_STATUS_INIT__REG DENALI_CTL_342
+#define LPDDR4__INT_STATUS_INIT__FLD LPDDR4__DENALI_CTL_342__INT_STATUS_INIT
+
+#define LPDDR4__DENALI_CTL_343_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_343_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_MODE_WIDTH                         8U
+#define LPDDR4__INT_STATUS_MODE__REG DENALI_CTL_343
+#define LPDDR4__INT_STATUS_MODE__FLD LPDDR4__DENALI_CTL_343__INT_STATUS_MODE
+
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY_WIDTH                       8U
+#define LPDDR4__INT_STATUS_PARITY__REG DENALI_CTL_343
+#define LPDDR4__INT_STATUS_PARITY__FLD LPDDR4__DENALI_CTL_343__INT_STATUS_PARITY
+
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT_WIDTH                        32U
+#define LPDDR4__INT_ACK_TIMEOUT__REG DENALI_CTL_344
+#define LPDDR4__INT_ACK_TIMEOUT__FLD LPDDR4__DENALI_CTL_344__INT_ACK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_345__MC_RESERVED16_WIDTH                          16U
+#define LPDDR4__MC_RESERVED16__REG DENALI_CTL_345
+#define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_345__MC_RESERVED16
+
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER_WIDTH                       16U
+#define LPDDR4__INT_ACK_LOWPOWER__REG DENALI_CTL_345
+#define LPDDR4__INT_ACK_LOWPOWER__FLD LPDDR4__DENALI_CTL_345__INT_ACK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED17_WIDTH                          16U
+#define LPDDR4__MC_RESERVED17__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED17
+
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_346__MC_RESERVED18_WIDTH                          16U
+#define LPDDR4__MC_RESERVED18__REG DENALI_CTL_346
+#define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_346__MC_RESERVED18
+
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING_WIDTH                       32U
+#define LPDDR4__INT_ACK_TRAINING__REG DENALI_CTL_347
+#define LPDDR4__INT_ACK_TRAINING__FLD LPDDR4__DENALI_CTL_347__INT_ACK_TRAINING
+
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_348__INT_ACK_USERIF_WIDTH                         32U
+#define LPDDR4__INT_ACK_USERIF__REG DENALI_CTL_348
+#define LPDDR4__INT_ACK_USERIF__FLD LPDDR4__DENALI_CTL_348__INT_ACK_USERIF
+
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_MASK                    0x0000FFFFU
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_MISC_WIDTH                           16U
+#define LPDDR4__INT_ACK_MISC__REG DENALI_CTL_349
+#define LPDDR4__INT_ACK_MISC__FLD LPDDR4__DENALI_CTL_349__INT_ACK_MISC
+
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_349__INT_ACK_BIST_WIDTH                            8U
+#define LPDDR4__INT_ACK_BIST__REG DENALI_CTL_349
+#define LPDDR4__INT_ACK_BIST__FLD LPDDR4__DENALI_CTL_349__INT_ACK_BIST
+
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_349__MC_RESERVED19_WIDTH                           8U
+#define LPDDR4__MC_RESERVED19__REG DENALI_CTL_349
+#define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_349__MC_RESERVED19
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_DFI_WIDTH                             8U
+#define LPDDR4__INT_ACK_DFI__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_DFI__FLD LPDDR4__DENALI_CTL_350__INT_ACK_DFI
+
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_350__MC_RESERVED20_WIDTH                           8U
+#define LPDDR4__MC_RESERVED20__REG DENALI_CTL_350
+#define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_350__MC_RESERVED20
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_FREQ_WIDTH                            8U
+#define LPDDR4__INT_ACK_FREQ__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_FREQ__FLD LPDDR4__DENALI_CTL_350__INT_ACK_FREQ
+
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_MASK                    0xFF000000U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_350__INT_ACK_INIT_WIDTH                            8U
+#define LPDDR4__INT_ACK_INIT__REG DENALI_CTL_350
+#define LPDDR4__INT_ACK_INIT__FLD LPDDR4__DENALI_CTL_350__INT_ACK_INIT
+
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_MASK                    0x000000FFU
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_MODE_WIDTH                            8U
+#define LPDDR4__INT_ACK_MODE__REG DENALI_CTL_351
+#define LPDDR4__INT_ACK_MODE__FLD LPDDR4__DENALI_CTL_351__INT_ACK_MODE
+
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_351__INT_ACK_PARITY_WIDTH                          8U
+#define LPDDR4__INT_ACK_PARITY__REG DENALI_CTL_351
+#define LPDDR4__INT_ACK_PARITY__FLD LPDDR4__DENALI_CTL_351__INT_ACK_PARITY
+
+#define LPDDR4__DENALI_CTL_352_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT_WIDTH                       32U
+#define LPDDR4__INT_MASK_TIMEOUT__REG DENALI_CTL_352
+#define LPDDR4__INT_MASK_TIMEOUT__FLD LPDDR4__DENALI_CTL_352__INT_MASK_TIMEOUT
+
+#define LPDDR4__DENALI_CTL_353_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_353__MC_RESERVED21_WIDTH                          16U
+#define LPDDR4__MC_RESERVED21__REG DENALI_CTL_353
+#define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_353__MC_RESERVED21
+
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_MASK               0xFFFF0000U
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER_WIDTH                      16U
+#define LPDDR4__INT_MASK_LOWPOWER__REG DENALI_CTL_353
+#define LPDDR4__INT_MASK_LOWPOWER__FLD LPDDR4__DENALI_CTL_353__INT_MASK_LOWPOWER
+
+#define LPDDR4__DENALI_CTL_354_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED22_WIDTH                          16U
+#define LPDDR4__MC_RESERVED22__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED22
+
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_354__MC_RESERVED23_WIDTH                          16U
+#define LPDDR4__MC_RESERVED23__REG DENALI_CTL_354
+#define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_354__MC_RESERVED23
+
+#define LPDDR4__DENALI_CTL_355_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_MASK               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING_WIDTH                      32U
+#define LPDDR4__INT_MASK_TRAINING__REG DENALI_CTL_355
+#define LPDDR4__INT_MASK_TRAINING__FLD LPDDR4__DENALI_CTL_355__INT_MASK_TRAINING
+
+#define LPDDR4__DENALI_CTL_356_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_356__INT_MASK_USERIF_WIDTH                        32U
+#define LPDDR4__INT_MASK_USERIF__REG DENALI_CTL_356
+#define LPDDR4__INT_MASK_USERIF__FLD LPDDR4__DENALI_CTL_356__INT_MASK_USERIF
+
+#define LPDDR4__DENALI_CTL_357_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_MISC_WIDTH                          16U
+#define LPDDR4__INT_MASK_MISC__REG DENALI_CTL_357
+#define LPDDR4__INT_MASK_MISC__FLD LPDDR4__DENALI_CTL_357__INT_MASK_MISC
+
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_357__INT_MASK_BIST_WIDTH                           8U
+#define LPDDR4__INT_MASK_BIST__REG DENALI_CTL_357
+#define LPDDR4__INT_MASK_BIST__FLD LPDDR4__DENALI_CTL_357__INT_MASK_BIST
+
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_357__MC_RESERVED24_WIDTH                           8U
+#define LPDDR4__MC_RESERVED24__REG DENALI_CTL_357
+#define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_357__MC_RESERVED24
+
+#define LPDDR4__DENALI_CTL_358_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_MASK                    0x000000FFU
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_DFI_WIDTH                            8U
+#define LPDDR4__INT_MASK_DFI__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_DFI__FLD LPDDR4__DENALI_CTL_358__INT_MASK_DFI
+
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_358__MC_RESERVED25_WIDTH                           8U
+#define LPDDR4__MC_RESERVED25__REG DENALI_CTL_358
+#define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_358__MC_RESERVED25
+
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_FREQ_WIDTH                           8U
+#define LPDDR4__INT_MASK_FREQ__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_FREQ__FLD LPDDR4__DENALI_CTL_358__INT_MASK_FREQ
+
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_358__INT_MASK_INIT_WIDTH                           8U
+#define LPDDR4__INT_MASK_INIT__REG DENALI_CTL_358
+#define LPDDR4__INT_MASK_INIT__FLD LPDDR4__DENALI_CTL_358__INT_MASK_INIT
+
+#define LPDDR4__DENALI_CTL_359_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_359_WRITE_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_MODE_WIDTH                           8U
+#define LPDDR4__INT_MASK_MODE__REG DENALI_CTL_359
+#define LPDDR4__INT_MASK_MODE__FLD LPDDR4__DENALI_CTL_359__INT_MASK_MODE
+
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_MASK                 0x0000FF00U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_359__INT_MASK_PARITY_WIDTH                         8U
+#define LPDDR4__INT_MASK_PARITY__REG DENALI_CTL_359
+#define LPDDR4__INT_MASK_PARITY__FLD LPDDR4__DENALI_CTL_359__INT_MASK_PARITY
+
+#define LPDDR4__DENALI_CTL_360_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0_WIDTH                    32U
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_360
+#define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_360__OUT_OF_RANGE_ADDR_0
+
+#define LPDDR4__DENALI_CTL_361_READ_MASK                             0x7F07FF01U
+#define LPDDR4__DENALI_CTL_361_WRITE_MASK                            0x7F07FF01U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_MASK             0x00000001U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1_WOSET                     0U
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_ADDR_1
+
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_MASK             0x0007FF00U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH_WIDTH                    11U
+#define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_LENGTH
+
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_MASK               0x7F000000U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE_WIDTH                       7U
+#define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_361
+#define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_361__OUT_OF_RANGE_TYPE
+
+#define LPDDR4__DENALI_CTL_362_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_CTL_362_WRITE_MASK                            0x0000003FU
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_MASK          0x0000003FU
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID_WIDTH                  6U
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_362
+#define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_362__OUT_OF_RANGE_SOURCE_ID
+
+#define LPDDR4__DENALI_CTL_363_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_363
+#define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_363__BIST_EXP_DATA_0
+
+#define LPDDR4__DENALI_CTL_364_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1_WIDTH                        32U
+#define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_364
+#define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_364__BIST_EXP_DATA_1
+
+#define LPDDR4__DENALI_CTL_365_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_365
+#define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_365__BIST_FAIL_DATA_0
+
+#define LPDDR4__DENALI_CTL_366_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_366
+#define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_366__BIST_FAIL_DATA_1
+
+#define LPDDR4__DENALI_CTL_367_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0_WIDTH                       32U
+#define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_367
+#define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_367__BIST_FAIL_ADDR_0
+
+#define LPDDR4__DENALI_CTL_368_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_368_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1_WOSET                        0U
+#define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_368
+#define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_368__BIST_FAIL_ADDR_1
+
+#define LPDDR4__DENALI_CTL_369_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_MASK           0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0_WIDTH                  32U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_369
+#define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_369__PORT_CMD_ERROR_ADDR_0
+
+#define LPDDR4__DENALI_CTL_370_READ_MASK                             0xFF033F01U
+#define LPDDR4__DENALI_CTL_370_WRITE_MASK                            0xFF033F01U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_MASK           0x00000001U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1_WOSET                   0U
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ADDR_1
+
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_MASK               0x00003F00U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID_WIDTH                       6U
+#define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_ID
+
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_MASK             0x00030000U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE_WIDTH                     2U
+#define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_370
+#define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_370__PORT_CMD_ERROR_TYPE
+
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_370
+#define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_370__TODTL_2CMD_F0
+
+#define LPDDR4__DENALI_CTL_371_READ_MASK                             0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_371_WRITE_MASK                            0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F0_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_371
+#define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_371__TODTH_WR_F0
+
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_MASK                     0x00000F00U
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_371__TODTH_RD_F0_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_371
+#define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_371__TODTH_RD_F0
+
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_371
+#define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_371__TODTL_2CMD_F1
+
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_371__TODTH_WR_F1_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_371
+#define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_371__TODTH_WR_F1
+
+#define LPDDR4__DENALI_CTL_372_READ_MASK                             0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_372_WRITE_MASK                            0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F1_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_372
+#define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_372__TODTH_RD_F1
+
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2_WIDTH                           8U
+#define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_372__TODTL_2CMD_F2
+
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_MASK                     0x000F0000U
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_372__TODTH_WR_F2_WIDTH                             4U
+#define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_372__TODTH_WR_F2
+
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_372__TODTH_RD_F2_WIDTH                             4U
+#define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_372
+#define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_372__TODTH_RD_F2
+
+#define LPDDR4__DENALI_CTL_373_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_373_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F0_WOSET                               0U
+#define LPDDR4__ODT_EN_F0__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F0
+
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F1_WOSET                               0U
+#define LPDDR4__ODT_EN_F1__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F1
+
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_373__ODT_EN_F2_WOSET                               0U
+#define LPDDR4__ODT_EN_F2__REG DENALI_CTL_373
+#define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_373__ODT_EN_F2
+
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_MASK         0x01000000U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_SHIFT                24U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD_WOSET                 0U
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_373
+#define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_373__EN_ODT_ASSERT_EXCEPT_RD
+
+#define LPDDR4__DENALI_CTL_374_READ_MASK                             0x033F3F3FU
+#define LPDDR4__DENALI_CTL_374_WRITE_MASK                            0x033F3F3FU
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_MASK                   0x003F0000U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2_WIDTH                           6U
+#define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_374
+#define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_374__WR_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_MASK                  0x03000000U
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0_WIDTH                          2U
+#define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_374
+#define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_374__ODT_RD_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_375_READ_MASK                             0x3F030303U
+#define LPDDR4__DENALI_CTL_375_WRITE_MASK                            0x3F030303U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_MASK                  0x00000003U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0_WIDTH                          2U
+#define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_375
+#define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS0
+
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_MASK                  0x00000300U
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1_WIDTH                          2U
+#define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_375
+#define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_375__ODT_RD_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_MASK                  0x00030000U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1_WIDTH                          2U
+#define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_375
+#define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_375__ODT_WR_MAP_CS1
+
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_MASK                   0x3F000000U
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_375
+#define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_375__RD_TO_ODTH_F0
+
+#define LPDDR4__DENALI_CTL_376_READ_MASK                             0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_376_WRITE_MASK                            0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_376
+#define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F1
+
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2_WIDTH                           6U
+#define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_376
+#define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_376__RD_TO_ODTH_F2
+
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_376
+#define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F0
+
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_376
+#define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_376__RW2MRW_DLY_F1
+
+#define LPDDR4__DENALI_CTL_377_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_377_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_MASK                   0x0000001FU
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2_WIDTH                           5U
+#define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_377
+#define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_377__RW2MRW_DLY_F2
+
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__R2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__R2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_377
+#define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_377__W2R_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_378_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_378_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_378
+#define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_378__W2W_DIFFCS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__R2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__R2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_378
+#define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_378__W2R_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_379_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_379_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_379
+#define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_379__W2W_DIFFCS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__R2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__R2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_379
+#define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_379__W2R_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_380_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_380_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_MASK               0x0000001FU
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2_WIDTH                       5U
+#define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_380
+#define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_380__W2W_DIFFCS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_MASK               0x00001F00U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F0
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_MASK               0x001F0000U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F1
+
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_MASK               0x1F000000U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2_WIDTH                       5U
+#define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_380
+#define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_380__R2W_SAMECS_DLY_F2
+
+#define LPDDR4__DENALI_CTL_381_READ_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_381_WRITE_MASK                            0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_MASK                  0x0000001FU
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__R2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_MASK                  0x00001F00U
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__W2R_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_MASK                  0x001F0000U
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY_WIDTH                          5U
+#define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_381
+#define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_381__W2W_SAMECS_DLY
+
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_381
+#define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_381__TDQSCK_MAX_F0
+
+#define LPDDR4__DENALI_CTL_382_READ_MASK                             0x0F070F07U
+#define LPDDR4__DENALI_CTL_382_WRITE_MASK                            0x0F070F07U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F0
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F1
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MIN_F1
+
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2_WIDTH                           4U
+#define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_382
+#define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_382__TDQSCK_MAX_F2
+
+#define LPDDR4__DENALI_CTL_383_READ_MASK                             0x07010107U
+#define LPDDR4__DENALI_CTL_383_WRITE_MASK                            0x07010107U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2_WIDTH                           3U
+#define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_383
+#define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_383__TDQSCK_MIN_F2
+
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_MASK    0x00000100U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_SHIFT            8U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WIDTH            1U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WOCLR            0U
+#define LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE_WOSET            0U
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__REG DENALI_CTL_383
+#define LPDDR4__AXI0_ALL_STROBES_USED_ENABLE__FLD LPDDR4__DENALI_CTL_383__AXI0_ALL_STROBES_USED_ENABLE
+
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_SHIFT        16U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WIDTH         1U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOCLR         0U
+#define LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE_WOSET         0U
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_383
+#define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_383__AXI0_FIXED_PORT_PRIORITY_ENABLE
+
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_MASK                 0x07000000U
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY_WIDTH                         3U
+#define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_383
+#define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_383__AXI0_R_PRIORITY
+
+#define LPDDR4__DENALI_CTL_384_READ_MASK                             0xFF010307U
+#define LPDDR4__DENALI_CTL_384_WRITE_MASK                            0xFF010307U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY_WIDTH                         3U
+#define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_384
+#define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_384__AXI0_W_PRIORITY
+
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_MASK                      0x00000300U
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_384__CKE_STATUS_WIDTH                              2U
+#define LPDDR4__CKE_STATUS__REG DENALI_CTL_384
+#define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_384__CKE_STATUS
+
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_384__MEM_RST_VALID_WOSET                           0U
+#define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_384
+#define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_384__MEM_RST_VALID
+
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_384
+#define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_384__TDFI_PHY_RDLAT_F0
+
+#define LPDDR4__DENALI_CTL_385_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_385
+#define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_385__TDFI_CTRLUPD_MAX_F0
+
+#define LPDDR4__DENALI_CTL_386_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_386
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_386__TDFI_PHYUPD_TYPE0_F0
+
+#define LPDDR4__DENALI_CTL_387_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_387
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHYUPD_TYPE1_F0
+
+#define LPDDR4__DENALI_CTL_388_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_388
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_388__TDFI_PHYUPD_TYPE2_F0
+
+#define LPDDR4__DENALI_CTL_389_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_389
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_PHYUPD_TYPE3_F0
+
+#define LPDDR4__DENALI_CTL_390_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_390
+#define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_RESP_F0
+
+#define LPDDR4__DENALI_CTL_391_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_SHIFT                0U
+#define LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_391
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_CTRLUPD_INTERVAL_F0
+
+#define LPDDR4__DENALI_CTL_392_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_392_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_CTRL_DELAY_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHY_WRDATA_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_RDCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F0__REG DENALI_CTL_392
+#define LPDDR4__TDFI_RDDATA_EN_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_RDDATA_EN_F0
+
+#define LPDDR4__DENALI_CTL_393_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_393_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_393
+#define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_WRCSLAT_F0
+
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F0__REG DENALI_CTL_393
+#define LPDDR4__TDFI_PHY_WRLAT_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHY_WRLAT_F0
+
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_393
+#define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_393__TDFI_PHY_RDLAT_F1
+
+#define LPDDR4__DENALI_CTL_394_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_394
+#define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_394__TDFI_CTRLUPD_MAX_F1
+
+#define LPDDR4__DENALI_CTL_395_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_395
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_395__TDFI_PHYUPD_TYPE0_F1
+
+#define LPDDR4__DENALI_CTL_396_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_396
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_396__TDFI_PHYUPD_TYPE1_F1
+
+#define LPDDR4__DENALI_CTL_397_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_397
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_PHYUPD_TYPE2_F1
+
+#define LPDDR4__DENALI_CTL_398_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_398
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE3_F1
+
+#define LPDDR4__DENALI_CTL_399_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_399
+#define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_RESP_F1
+
+#define LPDDR4__DENALI_CTL_400_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_SHIFT                0U
+#define LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_400
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_CTRLUPD_INTERVAL_F1
+
+#define LPDDR4__DENALI_CTL_401_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_401_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_CTRL_DELAY_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHY_WRDATA_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_RDCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F1__REG DENALI_CTL_401
+#define LPDDR4__TDFI_RDDATA_EN_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_RDDATA_EN_F1
+
+#define LPDDR4__DENALI_CTL_402_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_402_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_402
+#define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_WRCSLAT_F1
+
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F1__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHY_WRLAT_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHY_WRLAT_F1
+
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_MASK               0x00FF0000U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_402
+#define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_402__TDFI_PHY_RDLAT_F2
+
+#define LPDDR4__DENALI_CTL_403_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403_WRITE_MASK                            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_MASK             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2_WIDTH                    21U
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_403
+#define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_MAX_F2
+
+#define LPDDR4__DENALI_CTL_404_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_404
+#define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_404__TDFI_PHYUPD_TYPE0_F2
+
+#define LPDDR4__DENALI_CTL_405_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_405
+#define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_PHYUPD_TYPE1_F2
+
+#define LPDDR4__DENALI_CTL_406_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_406
+#define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE2_F2
+
+#define LPDDR4__DENALI_CTL_407_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_MASK            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2_WIDTH                   32U
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_407
+#define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE3_F2
+
+#define LPDDR4__DENALI_CTL_408_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408_WRITE_MASK                            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_MASK             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2_WIDTH                    23U
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_408
+#define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_RESP_F2
+
+#define LPDDR4__DENALI_CTL_409_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_SHIFT                0U
+#define LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2_WIDTH               32U
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_409
+#define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_CTRLUPD_INTERVAL_F2
+
+#define LPDDR4__DENALI_CTL_410_READ_MASK                             0xFFFF070FU
+#define LPDDR4__DENALI_CTL_410_WRITE_MASK                            0xFFFF070FU
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2_WIDTH                      4U
+#define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_CTRL_DELAY_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_MASK              0x00000700U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2_WIDTH                      3U
+#define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHY_WRDATA_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2_WIDTH                         8U
+#define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_RDCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_MASK               0xFF000000U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2_WIDTH                       8U
+#define LPDDR4__TDFI_RDDATA_EN_F2__REG DENALI_CTL_410
+#define LPDDR4__TDFI_RDDATA_EN_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_RDDATA_EN_F2
+
+#define LPDDR4__DENALI_CTL_411_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2_WIDTH                         8U
+#define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_411
+#define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_WRCSLAT_F2
+
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2_WIDTH                       8U
+#define LPDDR4__TDFI_PHY_WRLAT_F2__REG DENALI_CTL_411
+#define LPDDR4__TDFI_PHY_WRLAT_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_PHY_WRLAT_F2
+
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_411__DLL_RST_DELAY_WIDTH                          16U
+#define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_411
+#define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_411__DLL_RST_DELAY
+
+#define LPDDR4__DENALI_CTL_412_READ_MASK                             0x00037FFFU
+#define LPDDR4__DENALI_CTL_412_WRITE_MASK                            0x00037FFFU
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY_WIDTH                         8U
+#define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_412
+#define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_412__DLL_RST_ADJ_DLY
+
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_MASK             0x00007F00U
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS_WIDTH                     7U
+#define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_412
+#define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_412__UPDATE_ERROR_STATUS
+
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_MASK                0x00030000U
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE_WIDTH                        2U
+#define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_412
+#define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_412__DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_413_READ_MASK                             0x0F0FFFFFU
+#define LPDDR4__DENALI_CTL_413_WRITE_MASK                            0x0F0FFFFFU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN_WIDTH                       16U
+#define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_413
+#define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRLUPD_MIN
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK           0x000F0000U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH                   4U
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
+
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK            0x0F000000U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH                    4U
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
+#define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
+
+#define LPDDR4__DENALI_CTL_414_READ_MASK                             0x0701FF07U
+#define LPDDR4__DENALI_CTL_414_WRITE_MASK                            0x0701FF07U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_MASK                  0x00000007U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT_WIDTH                          3U
+#define LPDDR4__TDFI_PARIN_LAT__REG DENALI_CTL_414
+#define LPDDR4__TDFI_PARIN_LAT__FLD LPDDR4__DENALI_CTL_414__TDFI_PARIN_LAT
+
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_MASK               0x0000FF00U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY_WIDTH                       8U
+#define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_414
+#define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_414__TDFI_WRDATA_DELAY
+
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_MASK     0x00010000U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_SHIFT            16U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WIDTH             1U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WOCLR             0U
+#define LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE_WOSET             0U
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_414
+#define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_414__DISABLE_MEMORY_MASKED_WRITE
+
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_MASK            0x07000000U
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT_WIDTH                    3U
+#define LPDDR4__STRATEGY_2TICK_COUNT__REG DENALI_CTL_414
+#define LPDDR4__STRATEGY_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_414__STRATEGY_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415_READ_MASK                             0x07070707U
+#define LPDDR4__DENALI_CTL_415_WRITE_MASK                            0x07070707U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_MASK       0x00000007U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_SHIFT               0U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT_WIDTH               3U
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__BANK_ACTIVATE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_MASK                 0x00000700U
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT_WIDTH                         3U
+#define LPDDR4__PRE_2TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__PRE_2TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__PRE_2TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_MASK            0x00070000U
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT_WIDTH                    3U
+#define LPDDR4__STRATEGY_4TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__STRATEGY_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__STRATEGY_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_MASK       0x07000000U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_SHIFT              24U
+#define LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT_WIDTH               3U
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__REG DENALI_CTL_415
+#define LPDDR4__BANK_ACTIVATE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_415__BANK_ACTIVATE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_416_READ_MASK                             0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_416_WRITE_MASK                            0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT_WIDTH                         3U
+#define LPDDR4__PRE_4TICK_COUNT__REG DENALI_CTL_416
+#define LPDDR4__PRE_4TICK_COUNT__FLD LPDDR4__DENALI_CTL_416__PRE_4TICK_COUNT
+
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_2X4_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_MASK          0x000F0000U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_2X4_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_2X4_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_MASK           0x0F000000U
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__REG DENALI_CTL_416
+#define LPDDR4__TMP_NXN_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_416__TMP_NXN_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_417_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_MASK          0x0000000FU
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__TMP_NXN_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_417__TMP_NXN_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__ODT_TICK_PLUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__ODT_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_417__ODT_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__ODT_TICK_MINUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__ODT_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_417__ODT_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_MASK              0x0F000000U
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__REG DENALI_CTL_417
+#define LPDDR4__TRAS_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_417__TRAS_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_418_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ_WIDTH                     4U
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRAS_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRAS_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_MASK               0x00000F00U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__TRP_TICK_PLUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRP_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRP_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_MASK              0x000F0000U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRP_TICK_MINUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TRP_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TRP_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_MASK               0x0F000000U
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ_WIDTH                       4U
+#define LPDDR4__TWR_TICK_PLUS_ADJ__REG DENALI_CTL_418
+#define LPDDR4__TWR_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_418__TWR_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_419_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_MASK              0x0000000FU
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ_WIDTH                      4U
+#define LPDDR4__TWR_TICK_MINUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TWR_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TWR_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_MASK           0x00000F00U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ_WIDTH                   4U
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TMP_4X2_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_MASK          0x000F0000U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ_WIDTH                  4U
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TMP_4X2_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TMP_4X2_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_MASK              0x0F000000U
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ_WIDTH                      4U
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__REG DENALI_CTL_419
+#define LPDDR4__TRFC_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_419__TRFC_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_420_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_MASK             0x0000000FU
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ_WIDTH                     4U
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__TRFC_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_420__TRFC_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_MASK                0x00000F00U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ_WIDTH                        4U
+#define LPDDR4__RL_TICK_PLUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__RL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_420__RL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_MASK               0x000F0000U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ_WIDTH                       4U
+#define LPDDR4__RL_TICK_MINUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__RL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_420__RL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_MASK                0x0F000000U
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ_WIDTH                        4U
+#define LPDDR4__WL_TICK_PLUS_ADJ__REG DENALI_CTL_420
+#define LPDDR4__WL_TICK_PLUS_ADJ__FLD LPDDR4__DENALI_CTL_420__WL_TICK_PLUS_ADJ
+
+#define LPDDR4__DENALI_CTL_421_READ_MASK                             0xFFFFFF0FU
+#define LPDDR4__DENALI_CTL_421_WRITE_MASK                            0xFFFFFF0FU
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_MASK               0x0000000FU
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ_WIDTH                       4U
+#define LPDDR4__WL_TICK_MINUS_ADJ__REG DENALI_CTL_421
+#define LPDDR4__WL_TICK_MINUS_ADJ__FLD LPDDR4__DENALI_CTL_421__WL_TICK_MINUS_ADJ
+
+#define LPDDR4__DENALI_CTL_421__NWR_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_421__NWR_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_421__NWR_F0_WIDTH                                  8U
+#define LPDDR4__NWR_F0__REG DENALI_CTL_421
+#define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_421__NWR_F0
+
+#define LPDDR4__DENALI_CTL_421__NWR_F1_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_421__NWR_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_421__NWR_F1_WIDTH                                  8U
+#define LPDDR4__NWR_F1__REG DENALI_CTL_421
+#define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_421__NWR_F1
+
+#define LPDDR4__DENALI_CTL_421__NWR_F2_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_421__NWR_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_421__NWR_F2_WIDTH                                  8U
+#define LPDDR4__NWR_F2__REG DENALI_CTL_421
+#define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_421__NWR_F2
+
+#define LPDDR4__DENALI_CTL_422_READ_MASK                             0x007F7F7FU
+#define LPDDR4__DENALI_CTL_422_WRITE_MASK                            0x007F7F7FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_MASK            0x0000007FU
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F0
+
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_MASK            0x00007F00U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F1__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F1
+
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_MASK            0x007F0000U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2_WIDTH                    7U
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__REG DENALI_CTL_422
+#define LPDDR4__TDFI_CTRLMSG_RESP_F2__FLD LPDDR4__DENALI_CTL_422__TDFI_CTRLMSG_RESP_F2
+
+#endif /* REG_LPDDR4_DDR_CONTROLLER_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
new file mode 100644
index 000000000000..dcfd7d9e8600
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_phy_core_macros.h
@@ -0,0 +1,1838 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
+#define REG_LPDDR4_PHY_CORE_MACROS_H_
+
+#define LPDDR4__DENALI_PHY_1280_READ_MASK                            0x00000003U
+#define LPDDR4__DENALI_PHY_1280_WRITE_MASK                           0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_MASK                   0x00000003U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL_WIDTH                           2U
+#define LPDDR4__PHY_FREQ_SEL__REG DENALI_PHY_1280
+#define LPDDR4__PHY_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1280__PHY_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1281_READ_MASK                            0x1F030101U
+#define LPDDR4__DENALI_PHY_1281_WRITE_MASK                           0x1F030101U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF_WOSET                0U
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_FROM_REGIF__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_FROM_REGIF
+
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_MASK      0x00000100U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_SHIFT              8U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN_WOSET              0U
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_MULTICAST_EN__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_MULTICAST_EN
+
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_MASK             0x00030000U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX_WIDTH                     2U
+#define LPDDR4__PHY_FREQ_SEL_INDEX__REG DENALI_PHY_1281
+#define LPDDR4__PHY_FREQ_SEL_INDEX__FLD LPDDR4__DENALI_PHY_1281__PHY_FREQ_SEL_INDEX
+
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__REG DENALI_PHY_1281
+#define LPDDR4__PHY_SW_GRP0_SHIFT_0__FLD LPDDR4__DENALI_PHY_1281__PHY_SW_GRP0_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP1_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP1_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP2_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP2_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP3_SHIFT_0__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP3_SHIFT_0
+
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__REG DENALI_PHY_1282
+#define LPDDR4__PHY_SW_GRP0_SHIFT_1__FLD LPDDR4__DENALI_PHY_1282__PHY_SW_GRP0_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1283_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP1_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP1_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP2_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP2_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP3_SHIFT_1__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP3_SHIFT_1
+
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__REG DENALI_PHY_1283
+#define LPDDR4__PHY_SW_GRP0_SHIFT_2__FLD LPDDR4__DENALI_PHY_1283__PHY_SW_GRP0_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284_READ_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1284_WRITE_MASK                           0x1F1F1F1FU
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP1_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP1_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP2_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP2_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP3_SHIFT_2__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP3_SHIFT_2
+
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_MASK            0x1F000000U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__REG DENALI_PHY_1284
+#define LPDDR4__PHY_SW_GRP0_SHIFT_3__FLD LPDDR4__DENALI_PHY_1284__PHY_SW_GRP0_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285_READ_MASK                            0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1285_WRITE_MASK                           0x001F1F1FU
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_MASK            0x0000001FU
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP1_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP1_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_MASK            0x00001F00U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP2_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP2_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_MASK            0x001F0000U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3_WIDTH                    5U
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__REG DENALI_PHY_1285
+#define LPDDR4__PHY_SW_GRP3_SHIFT_3__FLD LPDDR4__DENALI_PHY_1285__PHY_SW_GRP3_SHIFT_3
+
+#define LPDDR4__DENALI_PHY_1286_READ_MASK                            0x011F07FFU
+#define LPDDR4__DENALI_PHY_1286_WRITE_MASK                           0x011F07FFU
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_MASK     0x000007FFU
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY_WIDTH            11U
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__REG DENALI_PHY_1286
+#define LPDDR4__PHY_GRP_BYPASS_SLAVE_DELAY__FLD LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_SLAVE_DELAY
+
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_MASK        0x001F0000U
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT_WIDTH                5U
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__REG DENALI_PHY_1286
+#define LPDDR4__PHY_SW_GRP_BYPASS_SHIFT__FLD LPDDR4__DENALI_PHY_1286__PHY_SW_GRP_BYPASS_SHIFT
+
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE_WOSET                0U
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__REG DENALI_PHY_1286
+#define LPDDR4__PHY_GRP_BYPASS_OVERRIDE__FLD LPDDR4__DENALI_PHY_1286__PHY_GRP_BYPASS_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1287_READ_MASK                            0x07FF0100U
+#define LPDDR4__DENALI_PHY_1287_WRITE_MASK                           0x07FF0100U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_MASK           0x00000001U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE_WOSET                   0U
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__REG DENALI_PHY_1287
+#define LPDDR4__SC_PHY_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1287__SC_PHY_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_MASK 0x00000100U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WIDTH        1U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOCLR        0U
+#define LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE_WOSET        0U
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__REG DENALI_PHY_1287
+#define LPDDR4__PHY_MANUAL_UPDATE_PHYUPD_ENABLE__FLD LPDDR4__DENALI_PHY_1287__PHY_MANUAL_UPDATE_PHYUPD_ENABLE
+
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_MASK                0x07FF0000U
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START_WIDTH                       11U
+#define LPDDR4__PHY_CSLVL_START__REG DENALI_PHY_1287
+#define LPDDR4__PHY_CSLVL_START__FLD LPDDR4__DENALI_PHY_1287__PHY_CSLVL_START
+
+#define LPDDR4__DENALI_PHY_1288_READ_MASK                            0x000107FFU
+#define LPDDR4__DENALI_PHY_1288_WRITE_MASK                           0x000107FFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY_WIDTH                  11U
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__REG DENALI_PHY_1288
+#define LPDDR4__PHY_CSLVL_COARSE_DLY__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_COARSE_DLY
+
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_MASK           0x00010000U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_SHIFT                  16U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE_WOSET                   0U
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__REG DENALI_PHY_1288
+#define LPDDR4__PHY_CSLVL_DEBUG_MODE__FLD LPDDR4__DENALI_PHY_1288__PHY_CSLVL_DEBUG_MODE
+
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT_WOSET                0U
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__REG DENALI_PHY_1288
+#define LPDDR4__SC_PHY_CSLVL_DEBUG_CONT__FLD LPDDR4__DENALI_PHY_1288__SC_PHY_CSLVL_DEBUG_CONT
+
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_MASK         0x00000001U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR_WOSET                 0U
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__REG DENALI_PHY_1289
+#define LPDDR4__SC_PHY_CSLVL_ERROR_CLR__FLD LPDDR4__DENALI_PHY_1289__SC_PHY_CSLVL_ERROR_CLR
+
+#define LPDDR4__DENALI_PHY_1290_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS0__REG DENALI_PHY_1290
+#define LPDDR4__PHY_CSLVL_OBS0__FLD LPDDR4__DENALI_PHY_1290__PHY_CSLVL_OBS0
+
+#define LPDDR4__DENALI_PHY_1291_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS1__REG DENALI_PHY_1291
+#define LPDDR4__PHY_CSLVL_OBS1__FLD LPDDR4__DENALI_PHY_1291__PHY_CSLVL_OBS1
+
+#define LPDDR4__DENALI_PHY_1292_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2_WIDTH                        32U
+#define LPDDR4__PHY_CSLVL_OBS2__REG DENALI_PHY_1292
+#define LPDDR4__PHY_CSLVL_OBS2__FLD LPDDR4__DENALI_PHY_1292__PHY_CSLVL_OBS2
+
+#define LPDDR4__DENALI_PHY_1293_READ_MASK                            0x0101FF01U
+#define LPDDR4__DENALI_PHY_1293_WRITE_MASK                           0x0101FF01U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_MASK               0x00000001U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE_WOSET                       0U
+#define LPDDR4__PHY_CSLVL_ENABLE__REG DENALI_PHY_1293
+#define LPDDR4__PHY_CSLVL_ENABLE__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_ENABLE
+
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_MASK 0x0001FF00U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_SHIFT        8U
+#define LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET_WIDTH        9U
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__REG DENALI_PHY_1293
+#define LPDDR4__PHY_CSLVL_PERIODIC_START_OFFSET__FLD LPDDR4__DENALI_PHY_1293__PHY_CSLVL_PERIODIC_START_OFFSET
+
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE_WOSET                   0U
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__REG DENALI_PHY_1293
+#define LPDDR4__PHY_LP4_BOOT_DISABLE__FLD LPDDR4__DENALI_PHY_1293__PHY_LP4_BOOT_DISABLE
+
+#define LPDDR4__DENALI_PHY_1294_READ_MASK                            0x0007FF03U
+#define LPDDR4__DENALI_PHY_1294_WRITE_MASK                           0x0007FF03U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_MASK               0x00000003U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP_WIDTH                       2U
+#define LPDDR4__PHY_CSLVL_CS_MAP__REG DENALI_PHY_1294
+#define LPDDR4__PHY_CSLVL_CS_MAP__FLD LPDDR4__DENALI_PHY_1294__PHY_CSLVL_CS_MAP
+
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_MASK                  0x0007FF00U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_SHIFT                          8U
+#define LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR_WIDTH                         11U
+#define LPDDR4__PHY_CSLVL_QTR__REG DENALI_PHY_1294
+#define LPDDR4__PHY_CSLVL_QTR__FLD LPDDR4__DENALI_PHY_1294__PHY_CSLVL_QTR
+
+#define LPDDR4__DENALI_PHY_1295_READ_MASK                            0x070F07FFU
+#define LPDDR4__DENALI_PHY_1295_WRITE_MASK                           0x070F07FFU
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_MASK           0x000007FFU
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK_WIDTH                  11U
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__REG DENALI_PHY_1295
+#define LPDDR4__PHY_CSLVL_COARSE_CHK__FLD LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CHK
+
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_MASK   0x000F0000U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT_WIDTH           4U
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__REG DENALI_PHY_1295
+#define LPDDR4__PHY_CSLVL_COARSE_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1295__PHY_CSLVL_COARSE_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_MASK 0x07000000U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_SHIFT      24U
+#define LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE_WIDTH       3U
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__REG DENALI_PHY_1295
+#define LPDDR4__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE__FLD LPDDR4__DENALI_PHY_1295__PHY_ADRCTL_SLAVE_LOOP_CNT_UPDATE
+
+#define LPDDR4__DENALI_PHY_1296_READ_MASK                            0x01010300U
+#define LPDDR4__DENALI_PHY_1296_WRITE_MASK                           0x01010300U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS_WOSET               0U
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADRCTL_SNAP_OBS_REGS__FLD LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_SNAP_OBS_REGS
+
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_MASK            0x00000300U
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE_WIDTH                    2U
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__REG DENALI_PHY_1296
+#define LPDDR4__PHY_DFI_PHYUPD_TYPE__FLD LPDDR4__DENALI_PHY_1296__PHY_DFI_PHYUPD_TYPE
+
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR_WOSET                       0U
+#define LPDDR4__PHY_ADRCTL_LPDDR__REG DENALI_PHY_1296
+#define LPDDR4__PHY_ADRCTL_LPDDR__FLD LPDDR4__DENALI_PHY_1296__PHY_ADRCTL_LPDDR
+
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_MASK                 0x01000000U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_SHIFT                        24U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE_WOSET                         0U
+#define LPDDR4__PHY_LP4_ACTIVE__REG DENALI_PHY_1296
+#define LPDDR4__PHY_LP4_ACTIVE__FLD LPDDR4__DENALI_PHY_1296__PHY_LP4_ACTIVE
+
+#define LPDDR4__DENALI_PHY_1297_READ_MASK                            0x0F010001U
+#define LPDDR4__DENALI_PHY_1297_WRITE_MASK                           0x0F010001U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_MASK                  0x00000001U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WIDTH                          1U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WOCLR                          0U
+#define LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS_WOSET                          0U
+#define LPDDR4__PHY_LPDDR3_CS__REG DENALI_PHY_1297
+#define LPDDR4__PHY_LPDDR3_CS__FLD LPDDR4__DENALI_PHY_1297__PHY_LPDDR3_CS
+
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_MASK   0x00000100U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES_WOSET           0U
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__REG DENALI_PHY_1297
+#define LPDDR4__SC_PHY_UPDATE_CLK_CAL_VALUES__FLD LPDDR4__DENALI_PHY_1297__SC_PHY_UPDATE_CLK_CAL_VALUES
+
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_MASK  0x00010000U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE_WOSET          0U
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__REG DENALI_PHY_1297
+#define LPDDR4__PHY_CONTINUOUS_CLK_CAL_UPDATE__FLD LPDDR4__DENALI_PHY_1297__PHY_CONTINUOUS_CLK_CAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_MASK             0x0F000000U
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__REG DENALI_PHY_1297
+#define LPDDR4__PHY_SW_TXIO_CTRL_0__FLD LPDDR4__DENALI_PHY_1297__PHY_SW_TXIO_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1298_READ_MASK                            0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1298_WRITE_MASK                           0x010F0F0FU
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_MASK             0x0000000FU
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_1__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_2__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_MASK             0x000F0000U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_SHIFT                    16U
+#define LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3_WIDTH                     4U
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__REG DENALI_PHY_1298
+#define LPDDR4__PHY_SW_TXIO_CTRL_3__FLD LPDDR4__DENALI_PHY_1298__PHY_SW_TXIO_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL_WOSET                0U
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__REG DENALI_PHY_1298
+#define LPDDR4__PHY_MEMCLK_SW_TXIO_CTRL__FLD LPDDR4__DENALI_PHY_1298__PHY_MEMCLK_SW_TXIO_CTRL
+
+#define LPDDR4__DENALI_PHY_1299_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1299_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_MASK     0x0000000FU
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_0__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_0
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_MASK     0x00000F00U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_1__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_1
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_MASK     0x000F0000U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_SHIFT            16U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_2__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_2
+
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_MASK     0x0F000000U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_SHIFT            24U
+#define LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3_WIDTH             4U
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__REG DENALI_PHY_1299
+#define LPDDR4__PHY_ADRCTL_SW_TXPWR_CTRL_3__FLD LPDDR4__DENALI_PHY_1299__PHY_ADRCTL_SW_TXPWR_CTRL_3
+
+#define LPDDR4__DENALI_PHY_1300_READ_MASK                            0x00010101U
+#define LPDDR4__DENALI_PHY_1300_WRITE_MASK                           0x00010101U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL_WOSET               0U
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__REG DENALI_PHY_1300
+#define LPDDR4__PHY_MEMCLK_SW_TXPWR_CTRL__FLD LPDDR4__DENALI_PHY_1300__PHY_MEMCLK_SW_TXPWR_CTRL
+
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_MASK     0x00000100U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_SHIFT             8U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE_WOSET             0U
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__REG DENALI_PHY_1300
+#define LPDDR4__PHY_TOP_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_TOP_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_MASK 0x00010000U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_SHIFT   16U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WIDTH    1U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOCLR    0U
+#define LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE_WOSET    0U
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__REG DENALI_PHY_1300
+#define LPDDR4__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1300__PHY_BYTE_DISABLE_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1301_READ_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_PHY_1301_WRITE_MASK                           0x010FFFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_MASK         0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL_WIDTH                16U
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__REG DENALI_PHY_1301
+#define LPDDR4__PHY_STATIC_TOG_CONTROL__FLD LPDDR4__DENALI_PHY_1301__PHY_STATIC_TOG_CONTROL
+
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_MASK  0x000F0000U
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE_WIDTH          4U
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__REG DENALI_PHY_1301
+#define LPDDR4__PHY_ADRCTL_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_ADRCTL_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_MASK  0x01000000U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WIDTH          1U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOCLR          0U
+#define LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE_WOSET          0U
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__REG DENALI_PHY_1301
+#define LPDDR4__PHY_MEMCLK_STATIC_TOG_DISABLE__FLD LPDDR4__DENALI_PHY_1301__PHY_MEMCLK_STATIC_TOG_DISABLE
+
+#define LPDDR4__DENALI_PHY_1302_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1302_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_MASK        0x00000001U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS_WOSET                0U
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__REG DENALI_PHY_1302
+#define LPDDR4__PHY_LP4_BOOT_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1302__PHY_LP4_BOOT_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1303_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_MASK             0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS_WIDTH                    32U
+#define LPDDR4__PHY_CLK_SWITCH_OBS__REG DENALI_PHY_1303
+#define LPDDR4__PHY_CLK_SWITCH_OBS__FLD LPDDR4__DENALI_PHY_1303__PHY_CLK_SWITCH_OBS
+
+#define LPDDR4__DENALI_PHY_1304_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT_WIDTH                          16U
+#define LPDDR4__PHY_PLL_WAIT__REG DENALI_PHY_1304
+#define LPDDR4__PHY_PLL_WAIT__FLD LPDDR4__DENALI_PHY_1304__PHY_PLL_WAIT
+
+#define LPDDR4__DENALI_PHY_1305_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1305_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_MASK              0x00000001U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS_WOSET                      0U
+#define LPDDR4__PHY_SW_PLL_BYPASS__REG DENALI_PHY_1305
+#define LPDDR4__PHY_SW_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1305__PHY_SW_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1306_READ_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306_WRITE_MASK                           0x0F0F0F0FU
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_MASK            0x0000000FU
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_0__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_0__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_0
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_MASK            0x00000F00U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_1__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_1__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_1
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_MASK            0x000F0000U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_2__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_2__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_2
+
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_MASK            0x0F000000U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_SHIFT                   24U
+#define LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3_WIDTH                    4U
+#define LPDDR4__PHY_SET_DFI_INPUT_3__REG DENALI_PHY_1306
+#define LPDDR4__PHY_SET_DFI_INPUT_3__FLD LPDDR4__DENALI_PHY_1306__PHY_SET_DFI_INPUT_3
+
+#define LPDDR4__DENALI_PHY_1307_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1307_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT0_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT1_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT2_0
+
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_MASK   0x03000000U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__REG DENALI_PHY_1307
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_0__FLD LPDDR4__DENALI_PHY_1307__PHY_CS_ACS_ALLOCATION_BIT3_0
+
+#define LPDDR4__DENALI_PHY_1308_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1308_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT0_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT1_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT2_1
+
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_MASK   0x03000000U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__REG DENALI_PHY_1308
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_1__FLD LPDDR4__DENALI_PHY_1308__PHY_CS_ACS_ALLOCATION_BIT3_1
+
+#define LPDDR4__DENALI_PHY_1309_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1309_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT0_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT1_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT2_2
+
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_MASK   0x03000000U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__REG DENALI_PHY_1309
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_2__FLD LPDDR4__DENALI_PHY_1309__PHY_CS_ACS_ALLOCATION_BIT3_2
+
+#define LPDDR4__DENALI_PHY_1310_READ_MASK                            0x03030303U
+#define LPDDR4__DENALI_PHY_1310_WRITE_MASK                           0x03030303U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_MASK   0x00000003U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT0_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT0_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_MASK   0x00000300U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_SHIFT           8U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT1_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT1_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_MASK   0x00030000U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_SHIFT          16U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT2_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT2_3
+
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_MASK   0x03000000U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3_WIDTH           2U
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__REG DENALI_PHY_1310
+#define LPDDR4__PHY_CS_ACS_ALLOCATION_BIT3_3__FLD LPDDR4__DENALI_PHY_1310__PHY_CS_ACS_ALLOCATION_BIT3_3
+
+#define LPDDR4__DENALI_PHY_1311_READ_MASK                            0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1311_WRITE_MASK                           0xFFFF1FFFU
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_MASK          0x00001FFFU
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL_WIDTH                 13U
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__REG DENALI_PHY_1311
+#define LPDDR4__PHY_LP4_BOOT_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1311__PHY_LP4_BOOT_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_MASK          0xFFFF0000U
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE_WIDTH                 16U
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__REG DENALI_PHY_1311
+#define LPDDR4__PHY_PLL_CTRL_OVERRIDE__FLD LPDDR4__DENALI_PHY_1311__PHY_PLL_CTRL_OVERRIDE
+
+#define LPDDR4__DENALI_PHY_1312_READ_MASK                            0x0000FF01U
+#define LPDDR4__DENALI_PHY_1312_WRITE_MASK                           0x0000FF01U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_MASK       0x00000001U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK_WOSET               0U
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__REG DENALI_PHY_1312
+#define LPDDR4__PHY_USE_PLL_DSKEWCALLOCK__FLD LPDDR4__DENALI_PHY_1312__PHY_USE_PLL_DSKEWCALLOCK
+
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_MASK           0x0000FF00U
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL_WIDTH                   8U
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__REG DENALI_PHY_1312
+#define LPDDR4__PHY_PLL_SPO_CAL_CTRL__FLD LPDDR4__DENALI_PHY_1312__PHY_PLL_SPO_CAL_CTRL
+
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_MASK    0x00030000U
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS_WIDTH            2U
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__REG DENALI_PHY_1312
+#define LPDDR4__SC_PHY_PLL_SPO_CAL_SNAP_OBS__FLD LPDDR4__DENALI_PHY_1312__SC_PHY_PLL_SPO_CAL_SNAP_OBS
+
+#define LPDDR4__DENALI_PHY_1313_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0_WIDTH                         16U
+#define LPDDR4__PHY_PLL_OBS_0__REG DENALI_PHY_1313
+#define LPDDR4__PHY_PLL_OBS_0__FLD LPDDR4__DENALI_PHY_1313__PHY_PLL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1314_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0_WIDTH                 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__REG DENALI_PHY_1314
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_0__FLD LPDDR4__DENALI_PHY_1314__PHY_PLL_SPO_CAL_OBS_0
+
+#define LPDDR4__DENALI_PHY_1315_READ_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1315_WRITE_MASK                           0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_MASK          0x00000FFFU
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0_WIDTH                 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__REG DENALI_PHY_1315
+#define LPDDR4__PHY_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1315__PHY_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0_WIDTH        12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__REG DENALI_PHY_1315
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_0__FLD LPDDR4__DENALI_PHY_1315__PHY_LP4_BOOT_PLL_DESKEWCALIN_0
+
+#define LPDDR4__DENALI_PHY_1316_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_SHIFT                          0U
+#define LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1_WIDTH                         16U
+#define LPDDR4__PHY_PLL_OBS_1__REG DENALI_PHY_1316
+#define LPDDR4__PHY_PLL_OBS_1__FLD LPDDR4__DENALI_PHY_1316__PHY_PLL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1317_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_MASK          0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1_WIDTH                 17U
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__REG DENALI_PHY_1317
+#define LPDDR4__PHY_PLL_SPO_CAL_OBS_1__FLD LPDDR4__DENALI_PHY_1317__PHY_PLL_SPO_CAL_OBS_1
+
+#define LPDDR4__DENALI_PHY_1318_READ_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1318_WRITE_MASK                           0x0FFF0FFFU
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_MASK          0x00000FFFU
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1_WIDTH                 12U
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1318__PHY_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_MASK 0x0FFF0000U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1_WIDTH        12U
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__REG DENALI_PHY_1318
+#define LPDDR4__PHY_LP4_BOOT_PLL_DESKEWCALIN_1__FLD LPDDR4__DENALI_PHY_1318__PHY_LP4_BOOT_PLL_DESKEWCALIN_1
+
+#define LPDDR4__DENALI_PHY_1319_READ_MASK                            0xFF0F0101U
+#define LPDDR4__DENALI_PHY_1319_WRITE_MASK                           0xFF0F0101U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_MASK             0x00000001U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WIDTH                     1U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WOCLR                     0U
+#define LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL_WOSET                     0U
+#define LPDDR4__PHY_PLL_REFOUT_SEL__REG DENALI_PHY_1319
+#define LPDDR4__PHY_PLL_REFOUT_SEL__FLD LPDDR4__DENALI_PHY_1319__PHY_PLL_REFOUT_SEL
+
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_MASK      0x00000100U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_SHIFT              8U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WIDTH              1U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WOCLR              0U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL_WOSET              0U
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__REG DENALI_PHY_1319
+#define LPDDR4__PHY_LP4_BOOT_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1319__PHY_LP4_BOOT_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_MASK                0x000F0000U
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT_WIDTH                        4U
+#define LPDDR4__PHY_TCKSRE_WAIT__REG DENALI_PHY_1319
+#define LPDDR4__PHY_TCKSRE_WAIT__FLD LPDDR4__DENALI_PHY_1319__PHY_TCKSRE_WAIT
+
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_MASK                  0xFF000000U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_SHIFT                         24U
+#define LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP_WIDTH                          8U
+#define LPDDR4__PHY_LP_WAKEUP__REG DENALI_PHY_1319
+#define LPDDR4__PHY_LP_WAKEUP__FLD LPDDR4__DENALI_PHY_1319__PHY_LP_WAKEUP
+
+#define LPDDR4__DENALI_PHY_1320_READ_MASK                            0x0003FF01U
+#define LPDDR4__DENALI_PHY_1320_WRITE_MASK                           0x0003FF01U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN_WOSET                         0U
+#define LPDDR4__PHY_LS_IDLE_EN__REG DENALI_PHY_1320
+#define LPDDR4__PHY_LS_IDLE_EN__FLD LPDDR4__DENALI_PHY_1320__PHY_LS_IDLE_EN
+
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_MASK        0x0003FF00U
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_SHIFT                8U
+#define LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG_WIDTH               10U
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__REG DENALI_PHY_1320
+#define LPDDR4__PHY_LP_CTRLUPD_CNTR_CFG__FLD LPDDR4__DENALI_PHY_1320__PHY_LP_CTRLUPD_CNTR_CFG
+
+#define LPDDR4__DENALI_PHY_1321_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1321_WRITE_MASK                           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL_WIDTH                      17U
+#define LPDDR4__PHY_DS_EXIT_CTRL__REG DENALI_PHY_1321
+#define LPDDR4__PHY_DS_EXIT_CTRL__FLD LPDDR4__DENALI_PHY_1321__PHY_DS_EXIT_CTRL
+
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_MASK           0x01000000U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_SHIFT                  24U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WIDTH                   1U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WOCLR                   0U
+#define LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY_WOSET                   0U
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__REG DENALI_PHY_1321
+#define LPDDR4__PHY_TDFI_PHY_WRDELAY__FLD LPDDR4__DENALI_PHY_1321__PHY_TDFI_PHY_WRDELAY
+
+#define LPDDR4__DENALI_PHY_1322_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_MASK              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM_WIDTH                     18U
+#define LPDDR4__PHY_PAD_FDBK_TERM__REG DENALI_PHY_1322
+#define LPDDR4__PHY_PAD_FDBK_TERM__FLD LPDDR4__DENALI_PHY_1322__PHY_PAD_FDBK_TERM
+
+#define LPDDR4__DENALI_PHY_1323_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_MASK              0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM_WIDTH                     17U
+#define LPDDR4__PHY_PAD_DATA_TERM__REG DENALI_PHY_1323
+#define LPDDR4__PHY_PAD_DATA_TERM__FLD LPDDR4__DENALI_PHY_1323__PHY_PAD_DATA_TERM
+
+#define LPDDR4__DENALI_PHY_1324_READ_MASK                            0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324_WRITE_MASK                           0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_MASK               0x0001FFFFU
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM_WIDTH                      17U
+#define LPDDR4__PHY_PAD_DQS_TERM__REG DENALI_PHY_1324
+#define LPDDR4__PHY_PAD_DQS_TERM__FLD LPDDR4__DENALI_PHY_1324__PHY_PAD_DQS_TERM
+
+#define LPDDR4__DENALI_PHY_1325_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_MASK              0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM_WIDTH                     18U
+#define LPDDR4__PHY_PAD_ADDR_TERM__REG DENALI_PHY_1325
+#define LPDDR4__PHY_PAD_ADDR_TERM__FLD LPDDR4__DENALI_PHY_1325__PHY_PAD_ADDR_TERM
+
+#define LPDDR4__DENALI_PHY_1326_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_CLK_TERM__REG DENALI_PHY_1326
+#define LPDDR4__PHY_PAD_CLK_TERM__FLD LPDDR4__DENALI_PHY_1326__PHY_PAD_CLK_TERM
+
+#define LPDDR4__DENALI_PHY_1327_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_ERR_TERM__REG DENALI_PHY_1327
+#define LPDDR4__PHY_PAD_ERR_TERM__FLD LPDDR4__DENALI_PHY_1327__PHY_PAD_ERR_TERM
+
+#define LPDDR4__DENALI_PHY_1328_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_CKE_TERM__REG DENALI_PHY_1328
+#define LPDDR4__PHY_PAD_CKE_TERM__FLD LPDDR4__DENALI_PHY_1328__PHY_PAD_CKE_TERM
+
+#define LPDDR4__DENALI_PHY_1329_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_RST_TERM__REG DENALI_PHY_1329
+#define LPDDR4__PHY_PAD_RST_TERM__FLD LPDDR4__DENALI_PHY_1329__PHY_PAD_RST_TERM
+
+#define LPDDR4__DENALI_PHY_1330_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_MASK                0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM_WIDTH                       18U
+#define LPDDR4__PHY_PAD_CS_TERM__REG DENALI_PHY_1330
+#define LPDDR4__PHY_PAD_CS_TERM__FLD LPDDR4__DENALI_PHY_1330__PHY_PAD_CS_TERM
+
+#define LPDDR4__DENALI_PHY_1331_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_MASK               0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM_WIDTH                      18U
+#define LPDDR4__PHY_PAD_ODT_TERM__REG DENALI_PHY_1331
+#define LPDDR4__PHY_PAD_ODT_TERM__FLD LPDDR4__DENALI_PHY_1331__PHY_PAD_ODT_TERM
+
+#define LPDDR4__DENALI_PHY_1332_READ_MASK                            0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1332_WRITE_MASK                           0x1FFF03FFU
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_MASK              0x000003FFU
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL_WIDTH                     10U
+#define LPDDR4__PHY_ADRCTL_RX_CAL__REG DENALI_PHY_1332
+#define LPDDR4__PHY_ADRCTL_RX_CAL__FLD LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_MASK          0x1FFF0000U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL_WIDTH                 13U
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__REG DENALI_PHY_1332
+#define LPDDR4__PHY_ADRCTL_LP3_RX_CAL__FLD LPDDR4__DENALI_PHY_1332__PHY_ADRCTL_LP3_RX_CAL
+
+#define LPDDR4__DENALI_PHY_1333_READ_MASK                            0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333_WRITE_MASK                           0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_MASK                 0x00001FFFU
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0_WIDTH                        13U
+#define LPDDR4__PHY_CAL_MODE_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_MODE_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_MODE_0
+
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_MASK                0x00010000U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0_WOSET                        0U
+#define LPDDR4__PHY_CAL_CLEAR_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_CLEAR_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_CLEAR_0
+
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_MASK                0x01000000U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_SHIFT                       24U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0_WOSET                        0U
+#define LPDDR4__PHY_CAL_START_0__REG DENALI_PHY_1333
+#define LPDDR4__PHY_CAL_START_0__FLD LPDDR4__DENALI_PHY_1333__PHY_CAL_START_0
+
+#define LPDDR4__DENALI_PHY_1334_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_MASK       0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_SHIFT               0U
+#define LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0_WIDTH              32U
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__REG DENALI_PHY_1334
+#define LPDDR4__PHY_CAL_INTERVAL_COUNT_0__FLD LPDDR4__DENALI_PHY_1334__PHY_CAL_INTERVAL_COUNT_0
+
+#define LPDDR4__DENALI_PHY_1335_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1335_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__REG DENALI_PHY_1335
+#define LPDDR4__PHY_CAL_SAMPLE_WAIT_0__FLD LPDDR4__DENALI_PHY_1335__PHY_CAL_SAMPLE_WAIT_0
+
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_MASK  0x00000700U
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0_WIDTH          3U
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__REG DENALI_PHY_1335
+#define LPDDR4__PHY_LP4_BOOT_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1335__PHY_LP4_BOOT_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1336_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_MASK           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0_WIDTH                  24U
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__REG DENALI_PHY_1336
+#define LPDDR4__PHY_CAL_RESULT_OBS_0__FLD LPDDR4__DENALI_PHY_1336__PHY_CAL_RESULT_OBS_0
+
+#define LPDDR4__DENALI_PHY_1337_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__REG DENALI_PHY_1337
+#define LPDDR4__PHY_CAL_RESULT2_OBS_0__FLD LPDDR4__DENALI_PHY_1337__PHY_CAL_RESULT2_OBS_0
+
+#define LPDDR4__DENALI_PHY_1338_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__REG DENALI_PHY_1338
+#define LPDDR4__PHY_CAL_RESULT4_OBS_0__FLD LPDDR4__DENALI_PHY_1338__PHY_CAL_RESULT4_OBS_0
+
+#define LPDDR4__DENALI_PHY_1339_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__REG DENALI_PHY_1339
+#define LPDDR4__PHY_CAL_RESULT5_OBS_0__FLD LPDDR4__DENALI_PHY_1339__PHY_CAL_RESULT5_OBS_0
+
+#define LPDDR4__DENALI_PHY_1340_READ_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340_WRITE_MASK                           0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__REG DENALI_PHY_1340
+#define LPDDR4__PHY_CAL_RESULT6_OBS_0__FLD LPDDR4__DENALI_PHY_1340__PHY_CAL_RESULT6_OBS_0
+
+#define LPDDR4__DENALI_PHY_1341_READ_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1341_WRITE_MASK                           0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_MASK          0x00FFFFFFU
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0_WIDTH                 24U
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__REG DENALI_PHY_1341
+#define LPDDR4__PHY_CAL_RESULT7_OBS_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_RESULT7_OBS_0
+
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_MASK             0x7F000000U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0_WIDTH                     7U
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__REG DENALI_PHY_1341
+#define LPDDR4__PHY_CAL_CPTR_CNT_0__FLD LPDDR4__DENALI_PHY_1341__PHY_CAL_CPTR_CNT_0
+
+#define LPDDR4__DENALI_PHY_1342_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1342_WRITE_MASK                           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_MASK          0x000000FFU
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_PU_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_PU_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_MASK          0x0000FF00U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_SHIFT                  8U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0_WIDTH                  8U
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_PD_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_PD_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_MASK         0x00FF0000U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0_WIDTH                 8U
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_RCV_FINE_ADJ_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_RCV_FINE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_MASK              0x01000000U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_SHIFT                     24U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WIDTH                      1U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WOCLR                      0U
+#define LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0_WOSET                      0U
+#define LPDDR4__PHY_CAL_DBG_CFG_0__REG DENALI_PHY_1342
+#define LPDDR4__PHY_CAL_DBG_CFG_0__FLD LPDDR4__DENALI_PHY_1342__PHY_CAL_DBG_CFG_0
+
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_MASK          0x00000001U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0_WOSET                  0U
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__REG DENALI_PHY_1343
+#define LPDDR4__SC_PHY_PAD_DBG_CONT_0__FLD LPDDR4__DENALI_PHY_1343__SC_PHY_PAD_DBG_CONT_0
+
+#define LPDDR4__DENALI_PHY_1344_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_MASK          0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_SHIFT                  0U
+#define LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0_WIDTH                 32U
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__REG DENALI_PHY_1344
+#define LPDDR4__PHY_CAL_RESULT3_OBS_0__FLD LPDDR4__DENALI_PHY_1344__PHY_CAL_RESULT3_OBS_0
+
+#define LPDDR4__DENALI_PHY_1345_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1345_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_MASK           0x000000FFU
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0_WIDTH                   8U
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__REG DENALI_PHY_1345
+#define LPDDR4__PHY_ADRCTL_PVT_MAP_0__FLD LPDDR4__DENALI_PHY_1345__PHY_ADRCTL_PVT_MAP_0
+
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_MASK            0x0FFFFF00U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_SHIFT                    8U
+#define LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0_WIDTH                   20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__REG DENALI_PHY_1345
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_0__FLD LPDDR4__DENALI_PHY_1345__PHY_CAL_SLOPE_ADJ_0
+
+#define LPDDR4__DENALI_PHY_1346_READ_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346_WRITE_MASK                           0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_MASK      0x000FFFFFU
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0_WIDTH             20U
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__REG DENALI_PHY_1346
+#define LPDDR4__PHY_CAL_SLOPE_ADJ_PASS2_0__FLD LPDDR4__DENALI_PHY_1346__PHY_CAL_SLOPE_ADJ_PASS2_0
+
+#define LPDDR4__DENALI_PHY_1347_READ_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347_WRITE_MASK                           0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_MASK         0x01FFFFFFU
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0_WIDTH                25U
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__REG DENALI_PHY_1347
+#define LPDDR4__PHY_CAL_TWO_PASS_CFG_0__FLD LPDDR4__DENALI_PHY_1347__PHY_CAL_TWO_PASS_CFG_0
+
+#define LPDDR4__DENALI_PHY_1348_READ_MASK                            0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1348_WRITE_MASK                           0x3F7FFFFFU
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_MASK           0x007FFFFFU
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0_WIDTH                  23U
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__REG DENALI_PHY_1348
+#define LPDDR4__PHY_CAL_SW_CAL_CFG_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_SW_CAL_CFG_0
+
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__REG DENALI_PHY_1348
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1348__PHY_CAL_RANGE_PASS1_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349_READ_MASK                            0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1349_WRITE_MASK                           0x3F3F1F3FU
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_MASK 0x00001F00U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS1_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PU_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_MASK 0x3F000000U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__REG DENALI_PHY_1349
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1349__PHY_CAL_RANGE_PASS2_PD_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350_READ_MASK                            0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1350_WRITE_MASK                           0x1F3F3F1FU
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_MASK 0x0000001FU
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS2_RX_MAX_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_MASK 0x003F0000U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_MASK 0x1F000000U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_SHIFT    24U
+#define LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__REG DENALI_PHY_1350
+#define LPDDR4__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1350__PHY_CAL_RANGE_PASS1_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351_READ_MASK                            0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1351_WRITE_MASK                           0x001F3F3FU
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_MASK 0x0000003FU
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_SHIFT     0U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PU_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_MASK 0x00003F00U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_SHIFT     8U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0_WIDTH     6U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_PD_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_SHIFT    16U
+#define LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0_WIDTH     5U
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__REG DENALI_PHY_1351
+#define LPDDR4__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0__FLD LPDDR4__DENALI_PHY_1351__PHY_CAL_RANGE_PASS2_RX_MIN_DELTA_0
+
+#define LPDDR4__DENALI_PHY_1352_READ_MASK                            0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352_WRITE_MASK                           0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_MASK               0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL_WIDTH                      16U
+#define LPDDR4__PHY_PAD_ATB_CTRL__REG DENALI_PHY_1352
+#define LPDDR4__PHY_PAD_ATB_CTRL__FLD LPDDR4__DENALI_PHY_1352__PHY_PAD_ATB_CTRL
+
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_MASK       0x00010000U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_SHIFT              16U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WIDTH               1U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WOCLR               0U
+#define LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE_WOSET               0U
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__REG DENALI_PHY_1352
+#define LPDDR4__PHY_ADRCTL_MANUAL_UPDATE__FLD LPDDR4__DENALI_PHY_1352__PHY_ADRCTL_MANUAL_UPDATE
+
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_MASK          0x01000000U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_SHIFT                 24U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WIDTH                  1U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WOCLR                  0U
+#define LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR_WOSET                  0U
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__REG DENALI_PHY_1352
+#define LPDDR4__PHY_AC_LPBK_ERR_CLEAR__FLD LPDDR4__DENALI_PHY_1352__PHY_AC_LPBK_ERR_CLEAR
+
+#define LPDDR4__DENALI_PHY_1353_READ_MASK                            0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1353_WRITE_MASK                           0x01FF0F03U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_MASK         0x00000003U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT_WIDTH                 2U
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_MASK             0x00000F00U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_SHIFT                     8U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE_WIDTH                     4U
+#define LPDDR4__PHY_AC_LPBK_ENABLE__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_MASK            0x01FF0000U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_SHIFT                   16U
+#define LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL_WIDTH                    9U
+#define LPDDR4__PHY_AC_LPBK_CONTROL__REG DENALI_PHY_1353
+#define LPDDR4__PHY_AC_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1353__PHY_AC_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1354_READ_MASK                            0x00000F7FU
+#define LPDDR4__DENALI_PHY_1354_WRITE_MASK                           0x00000F7FU
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_MASK      0x0000007FU
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_SHIFT              0U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START_WIDTH              7U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__REG DENALI_PHY_1354
+#define LPDDR4__PHY_AC_PRBS_PATTERN_START__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_START
+
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_MASK       0x00000F00U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK_WIDTH               4U
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__REG DENALI_PHY_1354
+#define LPDDR4__PHY_AC_PRBS_PATTERN_MASK__FLD LPDDR4__DENALI_PHY_1354__PHY_AC_PRBS_PATTERN_MASK
+
+#define LPDDR4__DENALI_PHY_1355_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_MASK         0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS_WIDTH                32U
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__REG DENALI_PHY_1355
+#define LPDDR4__PHY_AC_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1355__PHY_AC_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1356_READ_MASK                            0x003F0101U
+#define LPDDR4__DENALI_PHY_1356_WRITE_MASK                           0x003F0101U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_MASK     0x00000001U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WIDTH             1U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WOCLR             0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT_WOSET             0U
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_MASK         0x00000100U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE_WOSET                 0U
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_ENABLE__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_ENABLE
+
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_MASK        0x003F0000U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL_WIDTH                6U
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__REG DENALI_PHY_1356
+#define LPDDR4__PHY_AC_CLK_LPBK_CONTROL__FLD LPDDR4__DENALI_PHY_1356__PHY_AC_CLK_LPBK_CONTROL
+
+#define LPDDR4__DENALI_PHY_1357_READ_MASK                            0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1357_WRITE_MASK                           0x0101FFFFU
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_MASK     0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_SHIFT             0U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS_WIDTH            16U
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__REG DENALI_PHY_1357
+#define LPDDR4__PHY_AC_CLK_LPBK_RESULT_OBS__FLD LPDDR4__DENALI_PHY_1357__PHY_AC_CLK_LPBK_RESULT_OBS
+
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_MASK         0x00010000U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WIDTH                 1U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WOCLR                 0U
+#define LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE_WOSET                 0U
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__REG DENALI_PHY_1357
+#define LPDDR4__PHY_AC_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1357__PHY_AC_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_MASK        0x01000000U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_SHIFT               24U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE_WOSET                0U
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__REG DENALI_PHY_1357
+#define LPDDR4__PHY_TOP_PWR_RDC_DISABLE__FLD LPDDR4__DENALI_PHY_1357__PHY_TOP_PWR_RDC_DISABLE
+
+#define LPDDR4__DENALI_PHY_1358_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1358_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_MASK 0x00000001U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_SHIFT       0U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WIDTH       1U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOCLR       0U
+#define LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE_WOSET       0U
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__REG DENALI_PHY_1358
+#define LPDDR4__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE__FLD LPDDR4__DENALI_PHY_1358__PHY_AC_SLV_DLY_CTRL_GATE_DISABLE
+
+#define LPDDR4__DENALI_PHY_1359_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL_WIDTH               32U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__REG DENALI_PHY_1359
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL__FLD LPDDR4__DENALI_PHY_1359__PHY_DATA_BYTE_ORDER_SEL
+
+#define LPDDR4__DENALI_PHY_1360_READ_MASK                            0x03071FFFU
+#define LPDDR4__DENALI_PHY_1360_WRITE_MASK                           0x03071FFFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_MASK   0x000000FFU
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_SHIFT           0U
+#define LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH_WIDTH           8U
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__REG DENALI_PHY_1360
+#define LPDDR4__PHY_DATA_BYTE_ORDER_SEL_HIGH__FLD LPDDR4__DENALI_PHY_1360__PHY_DATA_BYTE_ORDER_SEL_HIGH
+
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_MASK           0x00001F00U
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_SHIFT                   8U
+#define LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP_WIDTH                   5U
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__REG DENALI_PHY_1360
+#define LPDDR4__PHY_CALVL_DEVICE_MAP__FLD LPDDR4__DENALI_PHY_1360__PHY_CALVL_DEVICE_MAP
+
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_MASK                0x00070000U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE_WIDTH                        3U
+#define LPDDR4__PHY_ADR_DISABLE__REG DENALI_PHY_1360
+#define LPDDR4__PHY_ADR_DISABLE__FLD LPDDR4__DENALI_PHY_1360__PHY_ADR_DISABLE
+
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_MASK  0x03000000U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_SHIFT         24U
+#define LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__REG DENALI_PHY_1360
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0__FLD LPDDR4__DENALI_PHY_1360__PHY_ADRCTL_MSTR_DLY_ENC_SEL_0
+
+#define LPDDR4__DENALI_PHY_1361_READ_MASK                            0x00030303U
+#define LPDDR4__DENALI_PHY_1361_WRITE_MASK                           0x00030303U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_MASK  0x00000003U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_SHIFT          0U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_1
+
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_MASK  0x00000300U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_SHIFT          8U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_2
+
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_MASK  0x00030000U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_SHIFT         16U
+#define LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3_WIDTH          2U
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__REG DENALI_PHY_1361
+#define LPDDR4__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3__FLD LPDDR4__DENALI_PHY_1361__PHY_ADRCTL_MSTR_DLY_ENC_SEL_3
+
+#define LPDDR4__DENALI_PHY_1362_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE_WIDTH                     32U
+#define LPDDR4__PHY_DDL_AC_ENABLE__REG DENALI_PHY_1362
+#define LPDDR4__PHY_DDL_AC_ENABLE__FLD LPDDR4__DENALI_PHY_1362__PHY_DDL_AC_ENABLE
+
+#define LPDDR4__DENALI_PHY_1363_READ_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363_WRITE_MASK                           0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_MASK                0x03FFFFFFU
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE_WIDTH                       26U
+#define LPDDR4__PHY_DDL_AC_MODE__REG DENALI_PHY_1363
+#define LPDDR4__PHY_DDL_AC_MODE__FLD LPDDR4__DENALI_PHY_1363__PHY_DDL_AC_MODE
+
+#define LPDDR4__DENALI_PHY_1364_READ_MASK                            0x00FF073FU
+#define LPDDR4__DENALI_PHY_1364_WRITE_MASK                           0x00FF073FU
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_MASK                0x0000003FU
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK_WIDTH                        6U
+#define LPDDR4__PHY_DDL_AC_MASK__REG DENALI_PHY_1364
+#define LPDDR4__PHY_DDL_AC_MASK__FLD LPDDR4__DENALI_PHY_1364__PHY_DDL_AC_MASK
+
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_MASK         0x00000700U
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_SHIFT                 8U
+#define LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG_WIDTH                 3U
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__REG DENALI_PHY_1364
+#define LPDDR4__PHY_INIT_UPDATE_CONFIG__FLD LPDDR4__DENALI_PHY_1364__PHY_INIT_UPDATE_CONFIG
+
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_MASK 0x00FF0000U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC_WIDTH         8U
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__REG DENALI_PHY_1364
+#define LPDDR4__PHY_DDL_TRACK_UPD_THRESHOLD_AC__FLD LPDDR4__DENALI_PHY_1364__PHY_DDL_TRACK_UPD_THRESHOLD_AC
+
+#define LPDDR4__DENALI_PHY_1365_READ_MASK                            0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1365_WRITE_MASK                           0x0707FFFFU
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_MASK    0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_SHIFT            0U
+#define LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN_WIDTH           16U
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__REG DENALI_PHY_1365
+#define LPDDR4__PHY_CA_PARITY_ERR_PULSE_MIN__FLD LPDDR4__DENALI_PHY_1365__PHY_CA_PARITY_ERR_PULSE_MIN
+
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_MASK                0x00070000U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_SHIFT                       16U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN_WIDTH                        3U
+#define LPDDR4__PHY_ERR_MASK_EN__REG DENALI_PHY_1365
+#define LPDDR4__PHY_ERR_MASK_EN__FLD LPDDR4__DENALI_PHY_1365__PHY_ERR_MASK_EN
+
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_MASK                 0x07000000U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_SHIFT                        24U
+#define LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS_WIDTH                         3U
+#define LPDDR4__PHY_ERR_STATUS__REG DENALI_PHY_1365
+#define LPDDR4__PHY_ERR_STATUS__FLD LPDDR4__DENALI_PHY_1365__PHY_ERR_STATUS
+
+#define LPDDR4__DENALI_PHY_1366_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER_WIDTH               32U
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__REG DENALI_PHY_1366
+#define LPDDR4__PHY_DS0_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1366__PHY_DS0_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1367_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_MASK        0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER_WIDTH               32U
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__REG DENALI_PHY_1367
+#define LPDDR4__PHY_DS1_DQS_ERR_COUNTER__FLD LPDDR4__DENALI_PHY_1367__PHY_DS1_DQS_ERR_COUNTER
+
+#define LPDDR4__DENALI_PHY_1368_READ_MASK                            0x030FFF03U
+#define LPDDR4__DENALI_PHY_1368_WRITE_MASK                           0x030FFF03U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_MASK                 0x00000003U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN_WIDTH                         2U
+#define LPDDR4__PHY_DLL_RST_EN__REG DENALI_PHY_1368
+#define LPDDR4__PHY_DLL_RST_EN__FLD LPDDR4__DENALI_PHY_1368__PHY_DLL_RST_EN
+
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_MASK       0x000FFF00U
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_SHIFT               8U
+#define LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS_WIDTH              12U
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__REG DENALI_PHY_1368
+#define LPDDR4__PHY_AC_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1368__PHY_AC_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_MASK       0x03000000U
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_SHIFT              24U
+#define LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS_WIDTH               2U
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__REG DENALI_PHY_1368
+#define LPDDR4__PHY_DS_INIT_COMPLETE_OBS__FLD LPDDR4__DENALI_PHY_1368__PHY_DS_INIT_COMPLETE_OBS
+
+#define LPDDR4__DENALI_PHY_1369_READ_MASK                            0x0F1F0101U
+#define LPDDR4__DENALI_PHY_1369_WRITE_MASK                           0x0F1F0101U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_MASK                0x00000001U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_SHIFT                        0U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WIDTH                        1U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WOCLR                        0U
+#define LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK_WOSET                        0U
+#define LPDDR4__PHY_UPDATE_MASK__REG DENALI_PHY_1369
+#define LPDDR4__PHY_UPDATE_MASK__FLD LPDDR4__DENALI_PHY_1369__PHY_UPDATE_MASK
+
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_MASK                     0x00000100U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_SHIFT                             8U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WIDTH                             1U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WOCLR                             0U
+#define LPDDR4__DENALI_PHY_1369__PHY_ERR_IE_WOSET                             0U
+#define LPDDR4__PHY_ERR_IE__REG DENALI_PHY_1369
+#define LPDDR4__PHY_ERR_IE__FLD LPDDR4__DENALI_PHY_1369__PHY_ERR_IE
+
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_MASK 0x001F0000U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_SHIFT        16U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT_WIDTH         5U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__REG DENALI_PHY_1369
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SLV_DLY_ENC_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_MASK       0x0F000000U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_SHIFT              24U
+#define LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT_WIDTH               4U
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__REG DENALI_PHY_1369
+#define LPDDR4__PHY_GRP_SHIFT_OBS_SELECT__FLD LPDDR4__DENALI_PHY_1369__PHY_GRP_SHIFT_OBS_SELECT
+
+#define LPDDR4__DENALI_PHY_1370_READ_MASK                            0x000707FFU
+#define LPDDR4__DENALI_PHY_1370_WRITE_MASK                           0x000707FFU
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_MASK        0x000007FFU
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_SHIFT                0U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS_WIDTH               11U
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__REG DENALI_PHY_1370
+#define LPDDR4__PHY_GRP_SLV_DLY_ENC_OBS__FLD LPDDR4__DENALI_PHY_1370__PHY_GRP_SLV_DLY_ENC_OBS
+
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_MASK              0x00070000U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_SHIFT                     16U
+#define LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS_WIDTH                      3U
+#define LPDDR4__PHY_GRP_SHIFT_OBS__REG DENALI_PHY_1370
+#define LPDDR4__PHY_GRP_SHIFT_OBS__FLD LPDDR4__DENALI_PHY_1370__PHY_GRP_SHIFT_OBS
+
+#define LPDDR4__DENALI_PHY_1371_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_MASK           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0_WIDTH                  18U
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__REG DENALI_PHY_1371
+#define LPDDR4__PHY_PAD_CAL_IO_CFG_0__FLD LPDDR4__DENALI_PHY_1371__PHY_PAD_CAL_IO_CFG_0
+
+#define LPDDR4__DENALI_PHY_1372_READ_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1372_WRITE_MASK                           0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_MASK             0x0000FFFFU
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG_WIDTH                    16U
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__REG DENALI_PHY_1372
+#define LPDDR4__PHY_PAD_ACS_IO_CFG__FLD LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_IO_CFG
+
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_MASK    0x00070000U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_SHIFT           16U
+#define LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL_WIDTH            3U
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__REG DENALI_PHY_1372
+#define LPDDR4__PHY_PAD_ACS_RX_PCLK_CLK_SEL__FLD LPDDR4__DENALI_PHY_1372__PHY_PAD_ACS_RX_PCLK_CLK_SEL
+
+#define LPDDR4__DENALI_PHY_1373_READ_MASK                            0x00000001U
+#define LPDDR4__DENALI_PHY_1373_WRITE_MASK                           0x00000001U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_MASK                 0x00000001U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_SHIFT                         0U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WIDTH                         1U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WOCLR                         0U
+#define LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS_WOSET                         0U
+#define LPDDR4__PHY_PLL_BYPASS__REG DENALI_PHY_1373
+#define LPDDR4__PHY_PLL_BYPASS__FLD LPDDR4__DENALI_PHY_1373__PHY_PLL_BYPASS
+
+#define LPDDR4__DENALI_PHY_1374_READ_MASK                            0x00011FFFU
+#define LPDDR4__DENALI_PHY_1374_WRITE_MASK                           0x00011FFFU
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_MASK                   0x00001FFFU
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_SHIFT                           0U
+#define LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL_WIDTH                          13U
+#define LPDDR4__PHY_PLL_CTRL__REG DENALI_PHY_1374
+#define LPDDR4__PHY_PLL_CTRL__FLD LPDDR4__DENALI_PHY_1374__PHY_PLL_CTRL
+
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_MASK               0x00010000U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_SHIFT                      16U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WIDTH                       1U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WOCLR                       0U
+#define LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL_WOSET                       0U
+#define LPDDR4__PHY_LOW_FREQ_SEL__REG DENALI_PHY_1374
+#define LPDDR4__PHY_LOW_FREQ_SEL__FLD LPDDR4__DENALI_PHY_1374__PHY_LOW_FREQ_SEL
+
+#define LPDDR4__DENALI_PHY_1375_READ_MASK                            0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1375_WRITE_MASK                           0x0F0F0FFFU
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_MASK           0x00000FFFU
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC_WIDTH                  12U
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__REG DENALI_PHY_1375
+#define LPDDR4__PHY_PAD_VREF_CTRL_AC__FLD LPDDR4__DENALI_PHY_1375__PHY_PAD_VREF_CTRL_AC
+
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_MASK          0x000F0000U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_SHIFT                 16U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT_WIDTH                  4U
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__REG DENALI_PHY_1375
+#define LPDDR4__PHY_CSLVL_CAPTURE_CNT__FLD LPDDR4__DENALI_PHY_1375__PHY_CSLVL_CAPTURE_CNT
+
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_MASK             0x0F000000U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_SHIFT                    24U
+#define LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP_WIDTH                     4U
+#define LPDDR4__PHY_CSLVL_DLY_STEP__REG DENALI_PHY_1375
+#define LPDDR4__PHY_CSLVL_DLY_STEP__FLD LPDDR4__DENALI_PHY_1375__PHY_CSLVL_DLY_STEP
+
+#define LPDDR4__DENALI_PHY_1376_READ_MASK                            0x010103FFU
+#define LPDDR4__DENALI_PHY_1376_WRITE_MASK                           0x010103FFU
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_MASK           0x000003FFU
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_WIDTH                  10U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__REG DENALI_PHY_1376
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN__FLD LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN
+
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_MASK        0x00010000U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_SHIFT               16U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WIDTH                1U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WOCLR                0U
+#define LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN_WOSET                0U
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__REG DENALI_PHY_1376
+#define LPDDR4__PHY_SW_CSLVL_DVW_MIN_EN__FLD LPDDR4__DENALI_PHY_1376__PHY_SW_CSLVL_DVW_MIN_EN
+
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_MASK   0x01000000U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_SHIFT          24U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WIDTH           1U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOCLR           0U
+#define LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE_WOSET           0U
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__REG DENALI_PHY_1376
+#define LPDDR4__PHY_LVL_MEAS_DLY_STEP_ENABLE__FLD LPDDR4__DENALI_PHY_1376__PHY_LVL_MEAS_DLY_STEP_ENABLE
+
+#define LPDDR4__DENALI_PHY_1377_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1377_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__REG DENALI_PHY_1377
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1377__PHY_GRP0_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__REG DENALI_PHY_1377
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1377__PHY_GRP1_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1378_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1378_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__REG DENALI_PHY_1378
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1378__PHY_GRP2_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__REG DENALI_PHY_1378
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_0__FLD LPDDR4__DENALI_PHY_1378__PHY_GRP3_SLAVE_DELAY_0
+
+#define LPDDR4__DENALI_PHY_1379_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1379_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__REG DENALI_PHY_1379
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1379__PHY_GRP0_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__REG DENALI_PHY_1379
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1379__PHY_GRP1_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1380_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1380_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__REG DENALI_PHY_1380
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1380__PHY_GRP2_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__REG DENALI_PHY_1380
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_1__FLD LPDDR4__DENALI_PHY_1380__PHY_GRP3_SLAVE_DELAY_1
+
+#define LPDDR4__DENALI_PHY_1381_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1381_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__REG DENALI_PHY_1381
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1381__PHY_GRP0_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__REG DENALI_PHY_1381
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1381__PHY_GRP1_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1382_READ_MASK                            0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1382_WRITE_MASK                           0x07FF07FFU
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__REG DENALI_PHY_1382
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1382__PHY_GRP2_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_MASK         0x07FF0000U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_SHIFT                16U
+#define LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__REG DENALI_PHY_1382
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_2__FLD LPDDR4__DENALI_PHY_1382__PHY_GRP3_SLAVE_DELAY_2
+
+#define LPDDR4__DENALI_PHY_1383_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1383_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__REG DENALI_PHY_1383
+#define LPDDR4__PHY_GRP0_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1383__PHY_GRP0_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1384_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1384_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__REG DENALI_PHY_1384
+#define LPDDR4__PHY_GRP1_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1384__PHY_GRP1_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1385_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1385_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__REG DENALI_PHY_1385
+#define LPDDR4__PHY_GRP2_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1385__PHY_GRP2_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1386_READ_MASK                            0x000007FFU
+#define LPDDR4__DENALI_PHY_1386_WRITE_MASK                           0x000007FFU
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_MASK         0x000007FFU
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_SHIFT                 0U
+#define LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3_WIDTH                11U
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__REG DENALI_PHY_1386
+#define LPDDR4__PHY_GRP3_SLAVE_DELAY_3__FLD LPDDR4__DENALI_PHY_1386__PHY_GRP3_SLAVE_DELAY_3
+
+#define LPDDR4__DENALI_PHY_1387_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE_WIDTH                    30U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__REG DENALI_PHY_1387
+#define LPDDR4__PHY_PAD_FDBK_DRIVE__FLD LPDDR4__DENALI_PHY_1387__PHY_PAD_FDBK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1388_READ_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388_WRITE_MASK                           0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_MASK            0x0003FFFFU
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2_WIDTH                   18U
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__REG DENALI_PHY_1388
+#define LPDDR4__PHY_PAD_FDBK_DRIVE2__FLD LPDDR4__DENALI_PHY_1388__PHY_PAD_FDBK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1389_READ_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389_WRITE_MASK                           0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_MASK             0x7FFFFFFFU
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE_WIDTH                    31U
+#define LPDDR4__PHY_PAD_DATA_DRIVE__REG DENALI_PHY_1389
+#define LPDDR4__PHY_PAD_DATA_DRIVE__FLD LPDDR4__DENALI_PHY_1389__PHY_PAD_DATA_DRIVE
+
+#define LPDDR4__DENALI_PHY_1390_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE_WIDTH                     32U
+#define LPDDR4__PHY_PAD_DQS_DRIVE__REG DENALI_PHY_1390
+#define LPDDR4__PHY_PAD_DQS_DRIVE__FLD LPDDR4__DENALI_PHY_1390__PHY_PAD_DQS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1391_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_MASK             0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE_WIDTH                    30U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__REG DENALI_PHY_1391
+#define LPDDR4__PHY_PAD_ADDR_DRIVE__FLD LPDDR4__DENALI_PHY_1391__PHY_PAD_ADDR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1392_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_MASK            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_SHIFT                    0U
+#define LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2_WIDTH                   28U
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__REG DENALI_PHY_1392
+#define LPDDR4__PHY_PAD_ADDR_DRIVE2__FLD LPDDR4__DENALI_PHY_1392__PHY_PAD_ADDR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1393_READ_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393_WRITE_MASK                           0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_MASK              0xFFFFFFFFU
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE_WIDTH                     32U
+#define LPDDR4__PHY_PAD_CLK_DRIVE__REG DENALI_PHY_1393
+#define LPDDR4__PHY_PAD_CLK_DRIVE__FLD LPDDR4__DENALI_PHY_1393__PHY_PAD_CLK_DRIVE
+
+#define LPDDR4__DENALI_PHY_1394_READ_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394_WRITE_MASK                           0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_MASK             0x0007FFFFU
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2_WIDTH                    19U
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__REG DENALI_PHY_1394
+#define LPDDR4__PHY_PAD_CLK_DRIVE2__FLD LPDDR4__DENALI_PHY_1394__PHY_PAD_CLK_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1395_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_ERR_DRIVE__REG DENALI_PHY_1395
+#define LPDDR4__PHY_PAD_ERR_DRIVE__FLD LPDDR4__DENALI_PHY_1395__PHY_PAD_ERR_DRIVE
+
+#define LPDDR4__DENALI_PHY_1396_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__REG DENALI_PHY_1396
+#define LPDDR4__PHY_PAD_ERR_DRIVE2__FLD LPDDR4__DENALI_PHY_1396__PHY_PAD_ERR_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1397_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_CKE_DRIVE__REG DENALI_PHY_1397
+#define LPDDR4__PHY_PAD_CKE_DRIVE__FLD LPDDR4__DENALI_PHY_1397__PHY_PAD_CKE_DRIVE
+
+#define LPDDR4__DENALI_PHY_1398_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__REG DENALI_PHY_1398
+#define LPDDR4__PHY_PAD_CKE_DRIVE2__FLD LPDDR4__DENALI_PHY_1398__PHY_PAD_CKE_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1399_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_RST_DRIVE__REG DENALI_PHY_1399
+#define LPDDR4__PHY_PAD_RST_DRIVE__FLD LPDDR4__DENALI_PHY_1399__PHY_PAD_RST_DRIVE
+
+#define LPDDR4__DENALI_PHY_1400_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_RST_DRIVE2__REG DENALI_PHY_1400
+#define LPDDR4__PHY_PAD_RST_DRIVE2__FLD LPDDR4__DENALI_PHY_1400__PHY_PAD_RST_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1401_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_MASK               0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_SHIFT                       0U
+#define LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE_WIDTH                      30U
+#define LPDDR4__PHY_PAD_CS_DRIVE__REG DENALI_PHY_1401
+#define LPDDR4__PHY_PAD_CS_DRIVE__FLD LPDDR4__DENALI_PHY_1401__PHY_PAD_CS_DRIVE
+
+#define LPDDR4__DENALI_PHY_1402_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_MASK              0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2_WIDTH                     28U
+#define LPDDR4__PHY_PAD_CS_DRIVE2__REG DENALI_PHY_1402
+#define LPDDR4__PHY_PAD_CS_DRIVE2__FLD LPDDR4__DENALI_PHY_1402__PHY_PAD_CS_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1403_READ_MASK                            0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403_WRITE_MASK                           0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_MASK              0x3FFFFFFFU
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_SHIFT                      0U
+#define LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE_WIDTH                     30U
+#define LPDDR4__PHY_PAD_ODT_DRIVE__REG DENALI_PHY_1403
+#define LPDDR4__PHY_PAD_ODT_DRIVE__FLD LPDDR4__DENALI_PHY_1403__PHY_PAD_ODT_DRIVE
+
+#define LPDDR4__DENALI_PHY_1404_READ_MASK                            0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404_WRITE_MASK                           0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_MASK             0x0FFFFFFFU
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_SHIFT                     0U
+#define LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2_WIDTH                    28U
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__REG DENALI_PHY_1404
+#define LPDDR4__PHY_PAD_ODT_DRIVE2__FLD LPDDR4__DENALI_PHY_1404__PHY_PAD_ODT_DRIVE2
+
+#define LPDDR4__DENALI_PHY_1405_READ_MASK                            0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1405_WRITE_MASK                           0x7FFFFF07U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_MASK           0x00000007U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_SHIFT                   0U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0_WIDTH                   3U
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_CLK_SELECT_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_CLK_SELECT_0
+
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_MASK    0x00FFFF00U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_SHIFT            8U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0_WIDTH           16U
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_VREF_SWITCH_TIMER_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_VREF_SWITCH_TIMER_0
+
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_MASK         0x7F000000U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_SHIFT                24U
+#define LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0_WIDTH                 7U
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__REG DENALI_PHY_1405
+#define LPDDR4__PHY_CAL_SETTLING_PRD_0__FLD LPDDR4__DENALI_PHY_1405__PHY_CAL_SETTLING_PRD_0
+
+#endif /* REG_LPDDR4_PHY_CORE_MACROS_H_ */
diff --git a/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
new file mode 100644
index 000000000000..9aa281af2193
--- /dev/null
+++ b/drivers/ram/k3-ddrss/16bit/lpddr4_pi_macros.h
@@ -0,0 +1,5784 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Cadence DDR Driver
+ *
+ * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
+ * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#ifndef REG_LPDDR4_PI_MACROS_H_
+#define REG_LPDDR4_PI_MACROS_H_
+
+#define LPDDR4__DENALI_PI_0_READ_MASK                                0x00000F01U
+#define LPDDR4__DENALI_PI_0_WRITE_MASK                               0x00000F01U
+#define LPDDR4__DENALI_PI_0__PI_START_MASK                           0x00000001U
+#define LPDDR4__DENALI_PI_0__PI_START_SHIFT                                   0U
+#define LPDDR4__DENALI_PI_0__PI_START_WIDTH                                   1U
+#define LPDDR4__DENALI_PI_0__PI_START_WOCLR                                   0U
+#define LPDDR4__DENALI_PI_0__PI_START_WOSET                                   0U
+#define LPDDR4__PI_START__REG DENALI_PI_0
+#define LPDDR4__PI_START__FLD LPDDR4__DENALI_PI_0__PI_START
+
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_MASK                      0x00000F00U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_SHIFT                              8U
+#define LPDDR4__DENALI_PI_0__PI_DRAM_CLASS_WIDTH                              4U
+#define LPDDR4__PI_DRAM_CLASS__REG DENALI_PI_0
+#define LPDDR4__PI_DRAM_CLASS__FLD LPDDR4__DENALI_PI_0__PI_DRAM_CLASS
+
+#define LPDDR4__DENALI_PI_1_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_1__PI_VERSION_0_WIDTH                              32U
+#define LPDDR4__PI_VERSION_0__REG DENALI_PI_1
+#define LPDDR4__PI_VERSION_0__FLD LPDDR4__DENALI_PI_1__PI_VERSION_0
+
+#define LPDDR4__DENALI_PI_2_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_SHIFT                               0U
+#define LPDDR4__DENALI_PI_2__PI_VERSION_1_WIDTH                              32U
+#define LPDDR4__PI_VERSION_1__REG DENALI_PI_2
+#define LPDDR4__PI_VERSION_1__FLD LPDDR4__DENALI_PI_2__PI_VERSION_1
+
+#define LPDDR4__DENALI_PI_3_READ_MASK                                0x0101FFFFU
+#define LPDDR4__DENALI_PI_3_WRITE_MASK                               0x0101FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_MASK                              0x0000FFFFU
+#define LPDDR4__DENALI_PI_3__PI_ID_SHIFT                                      0U
+#define LPDDR4__DENALI_PI_3__PI_ID_WIDTH                                     16U
+#define LPDDR4__PI_ID__REG DENALI_PI_3
+#define LPDDR4__PI_ID__FLD LPDDR4__DENALI_PI_3__PI_ID
+
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_SHIFT                            16U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WIDTH                             1U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOCLR                             0U
+#define LPDDR4__DENALI_PI_3__PI_RELEASE_DFI_WOSET                             0U
+#define LPDDR4__PI_RELEASE_DFI__REG DENALI_PI_3
+#define LPDDR4__PI_RELEASE_DFI__FLD LPDDR4__DENALI_PI_3__PI_RELEASE_DFI
+
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_MASK                  0x01000000U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_SHIFT                         24U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WIDTH                          1U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOCLR                          0U
+#define LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ_WOSET                          0U
+#define LPDDR4__PI_NORMAL_LVL_SEQ__REG DENALI_PI_3
+#define LPDDR4__PI_NORMAL_LVL_SEQ__FLD LPDDR4__DENALI_PI_3__PI_NORMAL_LVL_SEQ
+
+#define LPDDR4__DENALI_PI_4_READ_MASK                                0xFFFF0301U
+#define LPDDR4__DENALI_PI_4_WRITE_MASK                               0xFFFF0301U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_SHIFT                             0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN_WOSET                             0U
+#define LPDDR4__PI_INIT_LVL_EN__REG DENALI_PI_4
+#define LPDDR4__PI_INIT_LVL_EN__FLD LPDDR4__DENALI_PI_4__PI_INIT_LVL_EN
+
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_MASK                  0x00000300U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_SHIFT                          8U
+#define LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD_WIDTH                          2U
+#define LPDDR4__PI_NOTCARE_PHYUPD__REG DENALI_PI_4
+#define LPDDR4__PI_NOTCARE_PHYUPD__FLD LPDDR4__DENALI_PI_4__PI_NOTCARE_PHYUPD
+
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_MASK                        0xFFFF0000U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_SHIFT                               16U
+#define LPDDR4__DENALI_PI_4__PI_TCMD_GAP_WIDTH                               16U
+#define LPDDR4__PI_TCMD_GAP__REG DENALI_PI_4
+#define LPDDR4__PI_TCMD_GAP__FLD LPDDR4__DENALI_PI_4__PI_TCMD_GAP
+
+#define LPDDR4__DENALI_PI_5_READ_MASK                                0x030100FFU
+#define LPDDR4__DENALI_PI_5_WRITE_MASK                               0x030100FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_MASK                       0x000000FFU
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_SHIFT                               0U
+#define LPDDR4__DENALI_PI_5__PI_RESERVED0_WIDTH                               8U
+#define LPDDR4__PI_RESERVED0__REG DENALI_PI_5
+#define LPDDR4__PI_RESERVED0__FLD LPDDR4__DENALI_PI_5__PI_RESERVED0
+
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_MASK              0x00000100U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_SHIFT                      8U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WIDTH                      1U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOCLR                      0U
+#define LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ_WOSET                      0U
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__REG DENALI_PI_5
+#define LPDDR4__PI_TRAIN_ALL_FREQ_REQ__FLD LPDDR4__DENALI_PI_5__PI_TRAIN_ALL_FREQ_REQ
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_MASK                     0x00010000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_SHIFT                            16U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WIDTH                             1U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOCLR                             0U
+#define LPDDR4__DENALI_PI_5__PI_DFI_VERSION_WOSET                             0U
+#define LPDDR4__PI_DFI_VERSION__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_VERSION__FLD LPDDR4__DENALI_PI_5__PI_DFI_VERSION
+
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_SHIFT                       24U
+#define LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE_WIDTH                        2U
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__REG DENALI_PI_5
+#define LPDDR4__PI_DFI_PHYMSTR_TYPE__FLD LPDDR4__DENALI_PI_5__PI_DFI_PHYMSTR_TYPE
+
+#define LPDDR4__DENALI_PI_6_READ_MASK                                0x00000101U
+#define LPDDR4__DENALI_PI_6_WRITE_MASK                               0x00000101U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_MASK          0x00000001U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_SHIFT                  0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WIDTH                  1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOCLR                  0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R_WOSET                  0U
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_CS_STATE_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_CS_STATE_R
+
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_MASK         0x00000100U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_SHIFT                 8U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WIDTH                 1U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOCLR                 0U
+#define LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R_WOSET                 0U
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__REG DENALI_PI_6
+#define LPDDR4__PI_DFI_PHYMSTR_STATE_SEL_R__FLD LPDDR4__DENALI_PI_6__PI_DFI_PHYMSTR_STATE_SEL_R
+
+#define LPDDR4__DENALI_PI_7_READ_MASK                                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7_WRITE_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__REG DENALI_PI_7
+#define LPDDR4__PI_TDFI_PHYMSTR_MAX__FLD LPDDR4__DENALI_PI_7__PI_TDFI_PHYMSTR_MAX
+
+#define LPDDR4__DENALI_PI_8_READ_MASK                                0x000FFFFFU
+#define LPDDR4__DENALI_PI_8_WRITE_MASK                               0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_MASK               0x000FFFFFU
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_SHIFT                       0U
+#define LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP_WIDTH                      20U
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__REG DENALI_PI_8
+#define LPDDR4__PI_TDFI_PHYMSTR_RESP__FLD LPDDR4__DENALI_PI_8__PI_TDFI_PHYMSTR_RESP
+
+#define LPDDR4__DENALI_PI_9_READ_MASK                                0x000FFFFFU
+#define LPDDR4__DENALI_PI_9_WRITE_MASK                               0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_MASK                0x000FFFFFU
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_SHIFT                        0U
+#define LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP_WIDTH                       20U
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__REG DENALI_PI_9
+#define LPDDR4__PI_TDFI_PHYUPD_RESP__FLD LPDDR4__DENALI_PI_9__PI_TDFI_PHYUPD_RESP
+
+#define LPDDR4__DENALI_PI_10_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_SHIFT                        0U
+#define LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX_WIDTH                       32U
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__REG DENALI_PI_10
+#define LPDDR4__PI_TDFI_PHYUPD_MAX__FLD LPDDR4__DENALI_PI_10__PI_TDFI_PHYUPD_MAX
+
+#define LPDDR4__DENALI_PI_11_READ_MASK                               0x0000011FU
+#define LPDDR4__DENALI_PI_11_WRITE_MASK                              0x0000011FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_MASK                 0x0000001FU
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_SHIFT                         0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ_WIDTH                         5U
+#define LPDDR4__PI_INIT_WORK_FREQ__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_WORK_FREQ__FLD LPDDR4__DENALI_PI_11__PI_INIT_WORK_FREQ
+
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_MASK            0x00000100U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_SHIFT                    8U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WIDTH                    1U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOCLR                    0U
+#define LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY_WOSET                    0U
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__REG DENALI_PI_11
+#define LPDDR4__PI_INIT_DFS_CALVL_ONLY__FLD LPDDR4__DENALI_PI_11__PI_INIT_DFS_CALVL_ONLY
+
+#define LPDDR4__DENALI_PI_12_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12_WRITE_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_SHIFT                               0U
+#define LPDDR4__DENALI_PI_12__PI_FREQ_MAP_WIDTH                              32U
+#define LPDDR4__PI_FREQ_MAP__REG DENALI_PI_12
+#define LPDDR4__PI_FREQ_MAP__FLD LPDDR4__DENALI_PI_12__PI_FREQ_MAP
+
+#define LPDDR4__DENALI_PI_13_READ_MASK                               0x01030101U
+#define LPDDR4__DENALI_PI_13_WRITE_MASK                              0x01030101U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_MASK                       0x00000001U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_SHIFT                               0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WIDTH                               1U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOCLR                               0U
+#define LPDDR4__DENALI_PI_13__PI_SW_RST_N_WOSET                               0U
+#define LPDDR4__PI_SW_RST_N__REG DENALI_PI_13
+#define LPDDR4__PI_SW_RST_N__FLD LPDDR4__DENALI_PI_13__PI_SW_RST_N
+
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_MASK                      0x00000100U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_SHIFT                              8U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WIDTH                              1U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOCLR                              0U
+#define LPDDR4__DENALI_PI_13__PI_RESERVED1_WOSET                              0U
+#define LPDDR4__PI_RESERVED1__REG DENALI_PI_13
+#define LPDDR4__PI_RESERVED1__FLD LPDDR4__DENALI_PI_13__PI_RESERVED1
+
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_MASK                         0x00030000U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_SHIFT                                16U
+#define LPDDR4__DENALI_PI_13__PI_CS_MAP_WIDTH                                 2U
+#define LPDDR4__PI_CS_MAP__REG DENALI_PI_13
+#define LPDDR4__PI_CS_MAP__FLD LPDDR4__DENALI_PI_13__PI_CS_MAP
+
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_MASK                   0x01000000U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_SHIFT                          24U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WIDTH                           1U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOCLR                           0U
+#define LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL_WOSET                           0U
+#define LPDDR4__PI_SWLVL_CS_SEL__REG DENALI_PI_13
+#define LPDDR4__PI_SWLVL_CS_SEL__FLD LPDDR4__DENALI_PI_13__PI_SWLVL_CS_SEL
+
+#define LPDDR4__DENALI_PI_14_READ_MASK                               0x0F011F03U
+#define LPDDR4__DENALI_PI_14_WRITE_MASK                              0x0F011F03U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_MASK                        0x00000003U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_SHIFT                                0U
+#define LPDDR4__DENALI_PI_14__PI_CS_MASK_WIDTH                                2U
+#define LPDDR4__PI_CS_MASK__REG DENALI_PI_14
+#define LPDDR4__PI_CS_MASK__FLD LPDDR4__DENALI_PI_14__PI_CS_MASK
+
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_MASK               0x00001F00U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_SHIFT                       8U
+#define LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE_WIDTH                       5U
+#define LPDDR4__PI_RANK_NUM_PER_CKE__REG DENALI_PI_14
+#define LPDDR4__PI_RANK_NUM_PER_CKE__FLD LPDDR4__DENALI_PI_14__PI_RANK_NUM_PER_CKE
+
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_MASK           0x00010000U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_SHIFT                  16U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WIDTH                   1U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOCLR                   0U
+#define LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN_WOSET                   0U
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__REG DENALI_PI_14
+#define LPDDR4__PI_SRX_LVL_TARGET_CS_EN__FLD LPDDR4__DENALI_PI_14__PI_SRX_LVL_TARGET_CS_EN
+
+#define LPDDR4__DENALI_PI_14__PI_TMRR_MASK                           0x0F000000U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_SHIFT                                  24U
+#define LPDDR4__DENALI_PI_14__PI_TMRR_WIDTH                                   4U
+#define LPDDR4__PI_TMRR__REG DENALI_PI_14
+#define LPDDR4__PI_TMRR__FLD LPDDR4__DENALI_PI_14__PI_TMRR
+
+#define LPDDR4__DENALI_PI_15_READ_MASK                               0x0101070FU
+#define LPDDR4__DENALI_PI_15_WRITE_MASK                              0x0101070FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_MASK                          0x0000000FU
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_SHIFT                                  0U
+#define LPDDR4__DENALI_PI_15__PI_TMPRR_WIDTH                                  4U
+#define LPDDR4__PI_TMPRR__REG DENALI_PI_15
+#define LPDDR4__PI_TMPRR__FLD LPDDR4__DENALI_PI_15__PI_TMPRR
+
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_MASK                        0x00000700U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_SHIFT                                8U
+#define LPDDR4__DENALI_PI_15__PI_VRCG_EN_WIDTH                                3U
+#define LPDDR4__PI_VRCG_EN__REG DENALI_PI_15
+#define LPDDR4__PI_VRCG_EN__FLD LPDDR4__DENALI_PI_15__PI_VRCG_EN
+
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_MASK            0x00010000U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_SHIFT                   16U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WIDTH                    1U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOCLR                    0U
+#define LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY_WOSET                    0U
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__REG DENALI_PI_15
+#define LPDDR4__PI_MCAREF_FORWARD_ONLY__FLD LPDDR4__DENALI_PI_15__PI_MCAREF_FORWARD_ONLY
+
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_SHIFT                             24U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WIDTH                              1U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOCLR                              0U
+#define LPDDR4__DENALI_PI_15__PI_RESERVED2_WOSET                              0U
+#define LPDDR4__PI_RESERVED2__REG DENALI_PI_15
+#define LPDDR4__PI_RESERVED2__FLD LPDDR4__DENALI_PI_15__PI_RESERVED2
+
+#define LPDDR4__DENALI_PI_16_READ_MASK                               0x010FFFFFU
+#define LPDDR4__DENALI_PI_16_WRITE_MASK                              0x010FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_SHIFT                          0U
+#define LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL_WIDTH                         20U
+#define LPDDR4__PI_TREF_INTERVAL__REG DENALI_PI_16
+#define LPDDR4__PI_TREF_INTERVAL__FLD LPDDR4__DENALI_PI_16__PI_TREF_INTERVAL
+
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_MASK                      0x01000000U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_SHIFT                             24U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WIDTH                              1U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOCLR                              0U
+#define LPDDR4__DENALI_PI_16__PI_ON_DFIBUS_WOSET                              0U
+#define LPDDR4__PI_ON_DFIBUS__REG DENALI_PI_16
+#define LPDDR4__PI_ON_DFIBUS__FLD LPDDR4__DENALI_PI_16__PI_ON_DFIBUS
+
+#define LPDDR4__DENALI_PI_17_READ_MASK                               0x01010001U
+#define LPDDR4__DENALI_PI_17_WRITE_MASK                              0x01010001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_MASK                 0x00000001U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_SHIFT                         0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WIDTH                         1U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOCLR                         0U
+#define LPDDR4__DENALI_PI_17__PI_DATA_RETENTION_WOSET                         0U
+#define LPDDR4__PI_DATA_RETENTION__REG DENALI_PI_17
+#define LPDDR4__PI_DATA_RETENTION__FLD LPDDR4__DENALI_PI_17__PI_DATA_RETENTION
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_MASK                     0x00000100U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_SHIFT                             8U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WIDTH                             1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOCLR                             0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD_WOSET                             0U
+#define LPDDR4__PI_SWLVL_LOAD__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_LOAD__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_LOAD
+
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_MASK                  0x00010000U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_SHIFT                         16U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WIDTH                          1U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOCLR                          0U
+#define LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE_WOSET                          0U
+#define LPDDR4__PI_SWLVL_OP_DONE__REG DENALI_PI_17
+#define LPDDR4__PI_SWLVL_OP_DONE__FLD LPDDR4__DENALI_PI_17__PI_SWLVL_OP_DONE
+
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_MASK                0x01000000U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WIDTH                        1U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOCLR                        0U
+#define LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_0__REG DENALI_PI_17
+#define LPDDR4__PI_SW_WRLVL_RESP_0__FLD LPDDR4__DENALI_PI_17__PI_SW_WRLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18_READ_MASK                               0x03030301U
+#define LPDDR4__DENALI_PI_18_WRITE_MASK                              0x03030301U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_MASK                0x00000001U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_SHIFT                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WIDTH                        1U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOCLR                        0U
+#define LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1_WOSET                        0U
+#define LPDDR4__PI_SW_WRLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_WRLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_WRLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_MASK                0x00000300U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_SHIFT                        8U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_0
+
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_MASK                0x00030000U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_SHIFT                       16U
+#define LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1_WIDTH                        2U
+#define LPDDR4__PI_SW_RDLVL_RESP_1__REG DENALI_PI_18
+#define LPDDR4__PI_SW_RDLVL_RESP_1__FLD LPDDR4__DENALI_PI_18__PI_SW_RDLVL_RESP_1
+
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_MASK                0x03000000U
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_SHIFT                       24U
+#define LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0_WIDTH                        2U
+#define LPDDR4__PI_SW_CALVL_RESP_0__REG DENALI_PI_18
+#define LPDDR4__PI_SW_CALVL_RESP_0__FLD LPDDR4__DENALI_PI_18__PI_SW_CALVL_RESP_0
+
+#define LPDDR4__DENALI_PI_19_READ_MASK                               0x00000007U
+#define LPDDR4__DENALI_PI_19_WRITE_MASK                              0x00000007U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_MASK               0x00000007U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_SHIFT                       0U
+#define LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE_WIDTH                       3U
+#define LPDDR4__PI_SW_LEVELING_MODE__REG DENALI_PI_19
+#define LPDDR4__PI_SW_LEVELING_MODE__FLD LPDDR4__DENALI_PI_19__PI_SW_LEVELING_MODE
+
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_MASK                    0x00000100U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_SHIFT                            8U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WIDTH                            1U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOCLR                            0U
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_START_WOSET                            0U
+#define LPDDR4__PI_SWLVL_START__REG DENALI_PI_19
+#define LPDDR4__PI_SWLVL_START__FLD LPDDR4__DENALI_PI_19__PI_SWLVL_START
+
+#define LPDDR4__DENALI_PI_19__PI_SWLVL_EXIT_MASK                     0x00010000U
+#defin