[PATCH 07/15] ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issues

Dave Gerlach d-gerlach at ti.com
Tue May 4 04:51:56 CEST 2021


Fix the indentation for certain macros to be consistent with the other
macros in the file, as the existing indentation does not make sense in
many places.

Signed-off-by: Dave Gerlach <d-gerlach at ti.com>
---
 .../k3-j721e/lpddr4_ddr_controller_macros.h   | 7362 ++++++++---------
 1 file changed, 3681 insertions(+), 3681 deletions(-)

diff --git a/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
index 274a976ef986..846b1a97c076 100644
--- a/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
+++ b/drivers/ram/k3-j721e/lpddr4_ddr_controller_macros.h
@@ -10,127 +10,127 @@
 #ifndef REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
 #define REG_LPDDR4_DDR_CONTROLLER_MACROS_H_
 
-#define LPDDR4__DENALI_CTL_0_READ_MASK				               0xFFFF0F01U
-#define LPDDR4__DENALI_CTL_0_WRITE_MASK				              0xFFFF0F01U
-#define LPDDR4__DENALI_CTL_0__START_MASK				             0x00000001U
-#define LPDDR4__DENALI_CTL_0__START_SHIFT								     0U
-#define LPDDR4__DENALI_CTL_0__START_WIDTH								     1U
-#define LPDDR4__DENALI_CTL_0__START_WOCLR								     0U
-#define LPDDR4__DENALI_CTL_0__START_WOSET								     0U
+#define LPDDR4__DENALI_CTL_0_READ_MASK                               0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0_WRITE_MASK                              0xFFFF0F01U
+#define LPDDR4__DENALI_CTL_0__START_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_0__START_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WIDTH                                     1U
+#define LPDDR4__DENALI_CTL_0__START_WOCLR                                     0U
+#define LPDDR4__DENALI_CTL_0__START_WOSET                                     0U
 #define LPDDR4__START__REG DENALI_CTL_0
 #define LPDDR4__START__FLD LPDDR4__DENALI_CTL_0__START
 
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK				        0x00000F00U
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT								8U
-#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH								4U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_0__DRAM_CLASS_WIDTH                                4U
 #define LPDDR4__DRAM_CLASS__REG DENALI_CTL_0
 #define LPDDR4__DRAM_CLASS__FLD LPDDR4__DENALI_CTL_0__DRAM_CLASS
 
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK				     0xFFFF0000U
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH				            16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_MASK                     0xFFFF0000U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_0__CONTROLLER_ID_WIDTH                            16U
 #define LPDDR4__CONTROLLER_ID__REG DENALI_CTL_0
 #define LPDDR4__CONTROLLER_ID__FLD LPDDR4__DENALI_CTL_0__CONTROLLER_ID
 
-#define LPDDR4__DENALI_CTL_1_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_1_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_1_WRITE_MASK                              0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH				     32U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0_WIDTH                     32U
 #define LPDDR4__CONTROLLER_VERSION_0__REG DENALI_CTL_1
 #define LPDDR4__CONTROLLER_VERSION_0__FLD LPDDR4__DENALI_CTL_1__CONTROLLER_VERSION_0
 
-#define LPDDR4__DENALI_CTL_2_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_2_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_2_WRITE_MASK                              0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_MASK              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH				     32U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1_WIDTH                     32U
 #define LPDDR4__CONTROLLER_VERSION_1__REG DENALI_CTL_2
 #define LPDDR4__CONTROLLER_VERSION_1__FLD LPDDR4__DENALI_CTL_2__CONTROLLER_VERSION_1
 
-#define LPDDR4__DENALI_CTL_3_READ_MASK				               0xFF030F1FU
-#define LPDDR4__DENALI_CTL_3_WRITE_MASK				              0xFF030F1FU
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK				       0x0000001FU
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_3_READ_MASK                               0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3_WRITE_MASK                              0xFF030F1FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_3__MAX_ROW_REG_WIDTH                               5U
 #define LPDDR4__MAX_ROW_REG__REG DENALI_CTL_3
 #define LPDDR4__MAX_ROW_REG__FLD LPDDR4__DENALI_CTL_3__MAX_ROW_REG
 
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK				       0x00000F00U
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH				               4U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_MASK                       0x00000F00U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_3__MAX_COL_REG_WIDTH                               4U
 #define LPDDR4__MAX_COL_REG__REG DENALI_CTL_3
 #define LPDDR4__MAX_COL_REG__FLD LPDDR4__DENALI_CTL_3__MAX_COL_REG
 
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK				        0x00030000U
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH								2U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_3__MAX_CS_REG_WIDTH                                2U
 #define LPDDR4__MAX_CS_REG__REG DENALI_CTL_3
 #define LPDDR4__MAX_CS_REG__FLD LPDDR4__DENALI_CTL_3__MAX_CS_REG
 
 #define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_MASK              0xFF000000U
-#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH				      8U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH_WIDTH                      8U
 #define LPDDR4__READ_DATA_FIFO_DEPTH__REG DENALI_CTL_3
 #define LPDDR4__READ_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_3__READ_DATA_FIFO_DEPTH
 
-#define LPDDR4__DENALI_CTL_4_READ_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_4_WRITE_MASK				              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_4_WRITE_MASK                              0x00FFFFFFU
 #define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_MASK          0x000000FFU
-#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH				  8U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH_WIDTH                  8U
 #define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
 #define LPDDR4__READ_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__READ_DATA_FIFO_PTR_WIDTH
 
 #define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_MASK             0x0000FF00U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH				     8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH_WIDTH                     8U
 #define LPDDR4__WRITE_DATA_FIFO_DEPTH__REG DENALI_CTL_4
 #define LPDDR4__WRITE_DATA_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_DEPTH
 
 #define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_MASK         0x00FF0000U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT				16U
-#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH				 8U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_SHIFT                16U
+#define LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH_WIDTH                 8U
 #define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__REG DENALI_CTL_4
 #define LPDDR4__WRITE_DATA_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_4__WRITE_DATA_FIFO_PTR_WIDTH
 
-#define LPDDR4__DENALI_CTL_5_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_5_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_5_WRITE_MASK                              0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_MASK            0x0000FFFFU
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH				   16U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH_WIDTH                   16U
 #define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__REG DENALI_CTL_5
 #define LPDDR4__MEMCD_RMODW_FIFO_DEPTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_DEPTH
 
 #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_MASK        0x00FF0000U
 #define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_SHIFT               16U
-#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH				8U
+#define LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH_WIDTH                8U
 #define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__REG DENALI_CTL_5
 #define LPDDR4__MEMCD_RMODW_FIFO_PTR_WIDTH__FLD LPDDR4__DENALI_CTL_5__MEMCD_RMODW_FIFO_PTR_WIDTH
 
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES_WIDTH                          8U
 #define LPDDR4__ASYNC_CDC_STAGES__REG DENALI_CTL_5
 #define LPDDR4__ASYNC_CDC_STAGES__FLD LPDDR4__DENALI_CTL_5__ASYNC_CDC_STAGES
 
-#define LPDDR4__DENALI_CTL_6_READ_MASK				               0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_6_WRITE_MASK				              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_READ_MASK                               0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_6_WRITE_MASK                              0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_MASK           0x000000FFU
-#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH				   8U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH_WIDTH                   8U
 #define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
 #define LPDDR4__AXI0_CMDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_CMDFIFO_LOG2_DEPTH
 
 #define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_MASK            0x0000FF00U
-#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT				    8U
-#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH				    8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH_WIDTH                    8U
 #define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__REG DENALI_CTL_6
 #define LPDDR4__AXI0_RDFIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_RDFIFO_LOG2_DEPTH
 
 #define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_MASK          0x00FF0000U
-#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH				  8U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH_WIDTH                  8U
 #define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__REG DENALI_CTL_6
 #define LPDDR4__AXI0_WR_ARRAY_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WR_ARRAY_LOG2_DEPTH
 
@@ -140,1141 +140,1141 @@
 #define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__REG DENALI_CTL_6
 #define LPDDR4__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH__FLD LPDDR4__DENALI_CTL_6__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH
 
-#define LPDDR4__DENALI_CTL_7_READ_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7_WRITE_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK				          0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH								 24U
+#define LPDDR4__DENALI_CTL_7_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_MASK                          0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_7__TINIT_F0_WIDTH                                 24U
 #define LPDDR4__TINIT_F0__REG DENALI_CTL_7
 #define LPDDR4__TINIT_F0__FLD LPDDR4__DENALI_CTL_7__TINIT_F0
 
-#define LPDDR4__DENALI_CTL_8_READ_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8_WRITE_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK				         0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH								24U
+#define LPDDR4__DENALI_CTL_8_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_8__TINIT3_F0_WIDTH                                24U
 #define LPDDR4__TINIT3_F0__REG DENALI_CTL_8
 #define LPDDR4__TINIT3_F0__FLD LPDDR4__DENALI_CTL_8__TINIT3_F0
 
-#define LPDDR4__DENALI_CTL_9_READ_MASK				               0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9_WRITE_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK				         0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH								24U
+#define LPDDR4__DENALI_CTL_9_READ_MASK                               0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9_WRITE_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_9__TINIT4_F0_WIDTH                                24U
 #define LPDDR4__TINIT4_F0__REG DENALI_CTL_9
 #define LPDDR4__TINIT4_F0__FLD LPDDR4__DENALI_CTL_9__TINIT4_F0
 
-#define LPDDR4__DENALI_CTL_10_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT								0U
-#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH				               24U
+#define LPDDR4__DENALI_CTL_10_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_10__TINIT5_F0_WIDTH                               24U
 #define LPDDR4__TINIT5_F0__REG DENALI_CTL_10
 #define LPDDR4__TINIT5_F0__FLD LPDDR4__DENALI_CTL_10__TINIT5_F0
 
-#define LPDDR4__DENALI_CTL_11_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK				         0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH								24U
+#define LPDDR4__DENALI_CTL_11_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_11__TINIT_F1_WIDTH                                24U
 #define LPDDR4__TINIT_F1__REG DENALI_CTL_11
 #define LPDDR4__TINIT_F1__FLD LPDDR4__DENALI_CTL_11__TINIT_F1
 
-#define LPDDR4__DENALI_CTL_12_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH				               24U
+#define LPDDR4__DENALI_CTL_12_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_12__TINIT3_F1_WIDTH                               24U
 #define LPDDR4__TINIT3_F1__REG DENALI_CTL_12
 #define LPDDR4__TINIT3_F1__FLD LPDDR4__DENALI_CTL_12__TINIT3_F1
 
-#define LPDDR4__DENALI_CTL_13_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH				               24U
+#define LPDDR4__DENALI_CTL_13_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_13__TINIT4_F1_WIDTH                               24U
 #define LPDDR4__TINIT4_F1__REG DENALI_CTL_13
 #define LPDDR4__TINIT4_F1__FLD LPDDR4__DENALI_CTL_13__TINIT4_F1
 
-#define LPDDR4__DENALI_CTL_14_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH				               24U
+#define LPDDR4__DENALI_CTL_14_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_14__TINIT5_F1_WIDTH                               24U
 #define LPDDR4__TINIT5_F1__REG DENALI_CTL_14
 #define LPDDR4__TINIT5_F1__FLD LPDDR4__DENALI_CTL_14__TINIT5_F1
 
-#define LPDDR4__DENALI_CTL_15_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK				         0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH								24U
+#define LPDDR4__DENALI_CTL_15_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_MASK                         0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_15__TINIT_F2_WIDTH                                24U
 #define LPDDR4__TINIT_F2__REG DENALI_CTL_15
 #define LPDDR4__TINIT_F2__FLD LPDDR4__DENALI_CTL_15__TINIT_F2
 
-#define LPDDR4__DENALI_CTL_16_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH				               24U
+#define LPDDR4__DENALI_CTL_16_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_16__TINIT3_F2_WIDTH                               24U
 #define LPDDR4__TINIT3_F2__REG DENALI_CTL_16
 #define LPDDR4__TINIT3_F2__FLD LPDDR4__DENALI_CTL_16__TINIT3_F2
 
-#define LPDDR4__DENALI_CTL_17_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH				               24U
+#define LPDDR4__DENALI_CTL_17_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_17__TINIT4_F2_WIDTH                               24U
 #define LPDDR4__TINIT4_F2__REG DENALI_CTL_17
 #define LPDDR4__TINIT4_F2__FLD LPDDR4__DENALI_CTL_17__TINIT4_F2
 
-#define LPDDR4__DENALI_CTL_18_READ_MASK				              0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_18_WRITE_MASK				             0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK				        0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH				               24U
+#define LPDDR4__DENALI_CTL_18_READ_MASK                              0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18_WRITE_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_MASK                        0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_18__TINIT5_F2_WIDTH                               24U
 #define LPDDR4__TINIT5_F2__REG DENALI_CTL_18
 #define LPDDR4__TINIT5_F2__FLD LPDDR4__DENALI_CTL_18__TINIT5_F2
 
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET				         0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT_WOSET                         0U
 #define LPDDR4__NO_AUTO_MRR_INIT__REG DENALI_CTL_18
 #define LPDDR4__NO_AUTO_MRR_INIT__FLD LPDDR4__DENALI_CTL_18__NO_AUTO_MRR_INIT
 
-#define LPDDR4__DENALI_CTL_19_READ_MASK				              0x01010101U
-#define LPDDR4__DENALI_CTL_19_WRITE_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK				 0x00000001U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET				         0U
+#define LPDDR4__DENALI_CTL_19_READ_MASK                              0x01010101U
+#define LPDDR4__DENALI_CTL_19_WRITE_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS_WOSET                         0U
 #define LPDDR4__MRR_ERROR_STATUS__REG DENALI_CTL_19
 #define LPDDR4__MRR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_19__MRR_ERROR_STATUS
 
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET				          0U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS_WOSET                          0U
 #define LPDDR4__DFI_INV_DATA_CS__REG DENALI_CTL_19
 #define LPDDR4__DFI_INV_DATA_CS__FLD LPDDR4__DENALI_CTL_19__DFI_INV_DATA_CS
 
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK				      0x00010000U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET				              0U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_19__NO_MRW_INIT_WOSET                              0U
 #define LPDDR4__NO_MRW_INIT__REG DENALI_CTL_19
 #define LPDDR4__NO_MRW_INIT__FLD LPDDR4__DENALI_CTL_19__NO_MRW_INIT
 
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK				        0x01000000U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH								1U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR								0U
-#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET								0U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_MASK                        0x01000000U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_19__ODT_VALUE_WOSET                                0U
 #define LPDDR4__ODT_VALUE__REG DENALI_CTL_19
 #define LPDDR4__ODT_VALUE__FLD LPDDR4__DENALI_CTL_19__ODT_VALUE
 
-#define LPDDR4__DENALI_CTL_20_READ_MASK				              0x03013F01U
-#define LPDDR4__DENALI_CTL_20_WRITE_MASK				             0x03013F01U
+#define LPDDR4__DENALI_CTL_20_READ_MASK                              0x03013F01U
+#define LPDDR4__DENALI_CTL_20_WRITE_MASK                             0x03013F01U
 #define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_MASK             0x00000001U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH				     1U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR				     0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET				     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE_WOSET                     0U
 #define LPDDR4__PHY_INDEP_TRAIN_MODE__REG DENALI_CTL_20
 #define LPDDR4__PHY_INDEP_TRAIN_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_TRAIN_MODE
 
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK				    0x00003F00U
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH				            6U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_MASK                    0x00003F00U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR_WIDTH                            6U
 #define LPDDR4__TSREF2PHYMSTR__REG DENALI_CTL_20
 #define LPDDR4__TSREF2PHYMSTR__FLD LPDDR4__DENALI_CTL_20__TSREF2PHYMSTR
 
 #define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET				      0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE_WOSET                      0U
 #define LPDDR4__PHY_INDEP_INIT_MODE__REG DENALI_CTL_20
 #define LPDDR4__PHY_INDEP_INIT_MODE__FLD LPDDR4__DENALI_CTL_20__PHY_INDEP_INIT_MODE
 
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK				 0x03000000U
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH				         2U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_MASK                 0x03000000U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT_WIDTH                         2U
 #define LPDDR4__DFIBUS_FREQ_INIT__REG DENALI_CTL_20
 #define LPDDR4__DFIBUS_FREQ_INIT__FLD LPDDR4__DENALI_CTL_20__DFIBUS_FREQ_INIT
 
-#define LPDDR4__DENALI_CTL_21_READ_MASK				              0x1F1F1F03U
-#define LPDDR4__DENALI_CTL_21_WRITE_MASK				             0x1F1F1F03U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK				 0x00000003U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH				         2U
+#define LPDDR4__DENALI_CTL_21_READ_MASK                              0x1F1F1F03U
+#define LPDDR4__DENALI_CTL_21_WRITE_MASK                             0x1F1F1F03U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_MASK                 0x00000003U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ_WIDTH                         2U
 #define LPDDR4__DFIBUS_BOOT_FREQ__REG DENALI_CTL_21
 #define LPDDR4__DFIBUS_BOOT_FREQ__FLD LPDDR4__DENALI_CTL_21__DFIBUS_BOOT_FREQ
 
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK				   0x00001F00U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH				           5U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_MASK                   0x00001F00U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0_WIDTH                           5U
 #define LPDDR4__DFIBUS_FREQ_F0__REG DENALI_CTL_21
 #define LPDDR4__DFIBUS_FREQ_F0__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F0
 
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK				   0x001F0000U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH				           5U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1_WIDTH                           5U
 #define LPDDR4__DFIBUS_FREQ_F1__REG DENALI_CTL_21
 #define LPDDR4__DFIBUS_FREQ_F1__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F1
 
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK				   0x1F000000U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH				           5U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2_WIDTH                           5U
 #define LPDDR4__DFIBUS_FREQ_F2__REG DENALI_CTL_21
 #define LPDDR4__DFIBUS_FREQ_F2__FLD LPDDR4__DENALI_CTL_21__DFIBUS_FREQ_F2
 
-#define LPDDR4__DENALI_CTL_22_READ_MASK				              0x00030303U
-#define LPDDR4__DENALI_CTL_22_WRITE_MASK				             0x00030303U
+#define LPDDR4__DENALI_CTL_22_READ_MASK                              0x00030303U
+#define LPDDR4__DENALI_CTL_22_WRITE_MASK                             0x00030303U
 #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_MASK              0x00000003U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH				      2U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0_WIDTH                      2U
 #define LPDDR4__FREQ_CHANGE_TYPE_F0__REG DENALI_CTL_22
 #define LPDDR4__FREQ_CHANGE_TYPE_F0__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F0
 
 #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_MASK              0x00000300U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH				      2U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1_WIDTH                      2U
 #define LPDDR4__FREQ_CHANGE_TYPE_F1__REG DENALI_CTL_22
 #define LPDDR4__FREQ_CHANGE_TYPE_F1__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F1
 
 #define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_MASK              0x00030000U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH				      2U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2_WIDTH                      2U
 #define LPDDR4__FREQ_CHANGE_TYPE_F2__REG DENALI_CTL_22
 #define LPDDR4__FREQ_CHANGE_TYPE_F2__FLD LPDDR4__DENALI_CTL_22__FREQ_CHANGE_TYPE_F2
 
-#define LPDDR4__DENALI_CTL_23_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK				       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH				              32U
+#define LPDDR4__DENALI_CTL_23_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_23__TRST_PWRON_WIDTH                              32U
 #define LPDDR4__TRST_PWRON__REG DENALI_CTL_23
 #define LPDDR4__TRST_PWRON__FLD LPDDR4__DENALI_CTL_23__TRST_PWRON
 
-#define LPDDR4__DENALI_CTL_24_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK				     0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH				            32U
+#define LPDDR4__DENALI_CTL_24_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_MASK                     0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_24__CKE_INACTIVE_WIDTH                            32U
 #define LPDDR4__CKE_INACTIVE__REG DENALI_CTL_24
 #define LPDDR4__CKE_INACTIVE__FLD LPDDR4__DENALI_CTL_24__CKE_INACTIVE
 
-#define LPDDR4__DENALI_CTL_25_READ_MASK				              0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_25_WRITE_MASK				             0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK				     0x00000001U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET				             0U
+#define LPDDR4__DENALI_CTL_25_READ_MASK                              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_25_WRITE_MASK                             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED0_WOSET                             0U
 #define LPDDR4__MC_RESERVED0__REG DENALI_CTL_25
 #define LPDDR4__MC_RESERVED0__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED0
 
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK				     0xFFFFFF00U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH				            24U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_MASK                     0xFFFFFF00U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_25__MC_RESERVED1_WIDTH                            24U
 #define LPDDR4__MC_RESERVED1__REG DENALI_CTL_25
 #define LPDDR4__MC_RESERVED1__FLD LPDDR4__DENALI_CTL_25__MC_RESERVED1
 
-#define LPDDR4__DENALI_CTL_26_READ_MASK				              0x0001FFFFU
-#define LPDDR4__DENALI_CTL_26_WRITE_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK				     0x000000FFU
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_26_READ_MASK                              0x0001FFFFU
+#define LPDDR4__DENALI_CTL_26_WRITE_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED2_WIDTH                             8U
 #define LPDDR4__MC_RESERVED2__REG DENALI_CTL_26
 #define LPDDR4__MC_RESERVED2__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED2
 
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK				     0x0000FF00U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_26__MC_RESERVED3_WIDTH                             8U
 #define LPDDR4__MC_RESERVED3__REG DENALI_CTL_26
 #define LPDDR4__MC_RESERVED3__FLD LPDDR4__DENALI_CTL_26__MC_RESERVED3
 
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK				   0x00010000U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET				           0U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE_WOSET                           0U
 #define LPDDR4__DQS_OSC_ENABLE__REG DENALI_CTL_26
 #define LPDDR4__DQS_OSC_ENABLE__FLD LPDDR4__DENALI_CTL_26__DQS_OSC_ENABLE
 
-#define LPDDR4__DENALI_CTL_27_READ_MASK				              0xFF0F7FFFU
-#define LPDDR4__DENALI_CTL_27_WRITE_MASK				             0xFF0F7FFFU
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK				   0x00007FFFU
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH				          15U
+#define LPDDR4__DENALI_CTL_27_READ_MASK                              0xFF0F7FFFU
+#define LPDDR4__DENALI_CTL_27_WRITE_MASK                             0xFF0F7FFFU
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_MASK                   0x00007FFFU
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD_WIDTH                          15U
 #define LPDDR4__DQS_OSC_PERIOD__REG DENALI_CTL_27
 #define LPDDR4__DQS_OSC_PERIOD__FLD LPDDR4__DENALI_CTL_27__DQS_OSC_PERIOD
 
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK				0x000F0000U
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH				        4U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES_WIDTH                        4U
 #define LPDDR4__FUNC_VALID_CYCLES__REG DENALI_CTL_27
 #define LPDDR4__FUNC_VALID_CYCLES__FLD LPDDR4__DENALI_CTL_27__FUNC_VALID_CYCLES
 
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK				         0xFF000000U
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT								24U
-#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH								 8U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_MASK                         0xFF000000U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_27__TOSCO_F0_WIDTH                                 8U
 #define LPDDR4__TOSCO_F0__REG DENALI_CTL_27
 #define LPDDR4__TOSCO_F0__FLD LPDDR4__DENALI_CTL_27__TOSCO_F0
 
-#define LPDDR4__DENALI_CTL_28_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_28_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK				         0x000000FFU
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH								 8U
+#define LPDDR4__DENALI_CTL_28_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_28_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F1_WIDTH                                 8U
 #define LPDDR4__TOSCO_F1__REG DENALI_CTL_28
 #define LPDDR4__TOSCO_F1__FLD LPDDR4__DENALI_CTL_28__TOSCO_F1
 
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK				         0x0000FF00U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT								 8U
-#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH								 8U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_MASK                         0x0000FF00U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_28__TOSCO_F2_WIDTH                                 8U
 #define LPDDR4__TOSCO_F2__REG DENALI_CTL_28
 #define LPDDR4__TOSCO_F2__FLD LPDDR4__DENALI_CTL_28__TOSCO_F2
 
 #define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_MASK           0x00FF0000U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH				   8U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD_WIDTH                   8U
 #define LPDDR4__DQS_OSC_NORM_THRESHOLD__REG DENALI_CTL_28
 #define LPDDR4__DQS_OSC_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_NORM_THRESHOLD
 
 #define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_MASK           0xFF000000U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT				  24U
-#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH				   8U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD_WIDTH                   8U
 #define LPDDR4__DQS_OSC_HIGH_THRESHOLD__REG DENALI_CTL_28
 #define LPDDR4__DQS_OSC_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_28__DQS_OSC_HIGH_THRESHOLD
 
-#define LPDDR4__DENALI_CTL_29_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_29_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_29_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_29_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT_WIDTH                          8U
 #define LPDDR4__DQS_OSC_TIMEOUT__REG DENALI_CTL_29
 #define LPDDR4__DQS_OSC_TIMEOUT__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_TIMEOUT
 
 #define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_MASK        0x0000FF00U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT				8U
-#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH				8U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_SHIFT                8U
+#define LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD_WIDTH                8U
 #define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__REG DENALI_CTL_29
 #define LPDDR4__DQS_OSC_PROMOTE_THRESHOLD__FLD LPDDR4__DENALI_CTL_29__DQS_OSC_PROMOTE_THRESHOLD
 
 #define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_MASK               0xFFFF0000U
-#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH				      16U
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT_WIDTH                      16U
 #define LPDDR4__OSC_VARIANCE_LIMIT__REG DENALI_CTL_29
 #define LPDDR4__OSC_VARIANCE_LIMIT__FLD LPDDR4__DENALI_CTL_29__OSC_VARIANCE_LIMIT
 
-#define LPDDR4__DENALI_CTL_30_READ_MASK				              0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30_WRITE_MASK				             0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK				  0x00000001U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET				          0U
+#define LPDDR4__DENALI_CTL_30_READ_MASK                              0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30_WRITE_MASK                             0x00FFFF00U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST_WOSET                          0U
 #define LPDDR4__DQS_OSC_REQUEST__REG DENALI_CTL_30
 #define LPDDR4__DQS_OSC_REQUEST__FLD LPDDR4__DENALI_CTL_30__DQS_OSC_REQUEST
 
 #define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_MASK             0x00FFFF00U
-#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH				    16U
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0_WIDTH                    16U
 #define LPDDR4__OSC_BASE_VALUE_0_CS0__REG DENALI_CTL_30
 #define LPDDR4__OSC_BASE_VALUE_0_CS0__FLD LPDDR4__DENALI_CTL_30__OSC_BASE_VALUE_0_CS0
 
-#define LPDDR4__DENALI_CTL_31_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_31_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_31_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_MASK             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH				    16U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0_WIDTH                    16U
 #define LPDDR4__OSC_BASE_VALUE_1_CS0__REG DENALI_CTL_31
 #define LPDDR4__OSC_BASE_VALUE_1_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_1_CS0
 
 #define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_MASK             0xFFFF0000U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH				    16U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0_WIDTH                    16U
 #define LPDDR4__OSC_BASE_VALUE_2_CS0__REG DENALI_CTL_31
 #define LPDDR4__OSC_BASE_VALUE_2_CS0__FLD LPDDR4__DENALI_CTL_31__OSC_BASE_VALUE_2_CS0
 
-#define LPDDR4__DENALI_CTL_32_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_32_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_32_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_MASK             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH				    16U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0_WIDTH                    16U
 #define LPDDR4__OSC_BASE_VALUE_3_CS0__REG DENALI_CTL_32
 #define LPDDR4__OSC_BASE_VALUE_3_CS0__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_3_CS0
 
 #define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_MASK             0xFFFF0000U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH				    16U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1_WIDTH                    16U
 #define LPDDR4__OSC_BASE_VALUE_0_CS1__REG DENALI_CTL_32
 #define LPDDR4__OSC_BASE_VALUE_0_CS1__FLD LPDDR4__DENALI_CTL_32__OSC_BASE_VALUE_0_CS1
 
-#define LPDDR4__DENALI_CTL_33_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_33_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_33_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_MASK             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH				    16U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1_WIDTH                    16U
 #define LPDDR4__OSC_BASE_VALUE_1_CS1__REG DENALI_CTL_33
 #define LPDDR4__OSC_BASE_VALUE_1_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_1_CS1
 
 #define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_MASK             0xFFFF0000U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH				    16U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1_WIDTH                    16U
 #define LPDDR4__OSC_BASE_VALUE_2_CS1__REG DENALI_CTL_33
 #define LPDDR4__OSC_BASE_VALUE_2_CS1__FLD LPDDR4__DENALI_CTL_33__OSC_BASE_VALUE_2_CS1
 
-#define LPDDR4__DENALI_CTL_34_READ_MASK				              0x7F7FFFFFU
-#define LPDDR4__DENALI_CTL_34_WRITE_MASK				             0x7F7FFFFFU
+#define LPDDR4__DENALI_CTL_34_READ_MASK                              0x7F7FFFFFU
+#define LPDDR4__DENALI_CTL_34_WRITE_MASK                             0x7F7FFFFFU
 #define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_MASK             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH				    16U
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1_WIDTH                    16U
 #define LPDDR4__OSC_BASE_VALUE_3_CS1__REG DENALI_CTL_34
 #define LPDDR4__OSC_BASE_VALUE_3_CS1__FLD LPDDR4__DENALI_CTL_34__OSC_BASE_VALUE_3_CS1
 
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK				    0x007F0000U
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_MASK                    0x007F0000U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0_WIDTH                            7U
 #define LPDDR4__CASLAT_LIN_F0__REG DENALI_CTL_34
 #define LPDDR4__CASLAT_LIN_F0__FLD LPDDR4__DENALI_CTL_34__CASLAT_LIN_F0
 
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK				         0x7F000000U
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT								24U
-#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH								 7U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_MASK                         0x7F000000U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_34__WRLAT_F0_WIDTH                                 7U
 #define LPDDR4__WRLAT_F0__REG DENALI_CTL_34
 #define LPDDR4__WRLAT_F0__FLD LPDDR4__DENALI_CTL_34__WRLAT_F0
 
-#define LPDDR4__DENALI_CTL_35_READ_MASK				              0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_35_WRITE_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_35_READ_MASK                              0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_35_WRITE_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1_WIDTH                            7U
 #define LPDDR4__CASLAT_LIN_F1__REG DENALI_CTL_35
 #define LPDDR4__CASLAT_LIN_F1__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F1
 
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK				         0x00007F00U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT								 8U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH								 7U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_MASK                         0x00007F00U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F1_WIDTH                                 7U
 #define LPDDR4__WRLAT_F1__REG DENALI_CTL_35
 #define LPDDR4__WRLAT_F1__FLD LPDDR4__DENALI_CTL_35__WRLAT_F1
 
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK				    0x007F0000U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_MASK                    0x007F0000U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2_WIDTH                            7U
 #define LPDDR4__CASLAT_LIN_F2__REG DENALI_CTL_35
 #define LPDDR4__CASLAT_LIN_F2__FLD LPDDR4__DENALI_CTL_35__CASLAT_LIN_F2
 
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK				         0x7F000000U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT								24U
-#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH								 7U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_MASK                         0x7F000000U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_35__WRLAT_F2_WIDTH                                 7U
 #define LPDDR4__WRLAT_F2__REG DENALI_CTL_35
 #define LPDDR4__WRLAT_F2__FLD LPDDR4__DENALI_CTL_35__WRLAT_F2
 
-#define LPDDR4__DENALI_CTL_36_READ_MASK				              0x00FF1F07U
-#define LPDDR4__DENALI_CTL_36_WRITE_MASK				             0x00FF1F07U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK				0x00000007U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH				        3U
+#define LPDDR4__DENALI_CTL_36_READ_MASK                              0x00FF1F07U
+#define LPDDR4__DENALI_CTL_36_WRITE_MASK                             0x00FF1F07U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL_WIDTH                        3U
 #define LPDDR4__TBST_INT_INTERVAL__REG DENALI_CTL_36
 #define LPDDR4__TBST_INT_INTERVAL__FLD LPDDR4__DENALI_CTL_36__TBST_INT_INTERVAL
 
-#define LPDDR4__DENALI_CTL_36__TCCD_MASK				             0x00001F00U
-#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT								     8U
-#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH								     5U
+#define LPDDR4__DENALI_CTL_36__TCCD_MASK                             0x00001F00U
+#define LPDDR4__DENALI_CTL_36__TCCD_SHIFT                                     8U
+#define LPDDR4__DENALI_CTL_36__TCCD_WIDTH                                     5U
 #define LPDDR4__TCCD__REG DENALI_CTL_36
 #define LPDDR4__TCCD__FLD LPDDR4__DENALI_CTL_36__TCCD
 
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_36__TRRD_F0_WIDTH                                  8U
 #define LPDDR4__TRRD_F0__REG DENALI_CTL_36
 #define LPDDR4__TRRD_F0__FLD LPDDR4__DENALI_CTL_36__TRRD_F0
 
-#define LPDDR4__DENALI_CTL_37_READ_MASK				              0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_37_WRITE_MASK				             0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK				           0x000001FFU
-#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH								   9U
+#define LPDDR4__DENALI_CTL_37_READ_MASK                              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_37_WRITE_MASK                             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_37__TRC_F0_MASK                           0x000001FFU
+#define LPDDR4__DENALI_CTL_37__TRC_F0_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_37__TRC_F0_WIDTH                                   9U
 #define LPDDR4__TRC_F0__REG DENALI_CTL_37
 #define LPDDR4__TRC_F0__FLD LPDDR4__DENALI_CTL_37__TRC_F0
 
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK				      0x00FF0000U
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_37__TRAS_MIN_F0_WIDTH                              8U
 #define LPDDR4__TRAS_MIN_F0__REG DENALI_CTL_37
 #define LPDDR4__TRAS_MIN_F0__FLD LPDDR4__DENALI_CTL_37__TRAS_MIN_F0
 
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK				          0x3F000000U
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH								  6U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_MASK                          0x3F000000U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_37__TWTR_F0_WIDTH                                  6U
 #define LPDDR4__TWTR_F0__REG DENALI_CTL_37
 #define LPDDR4__TWTR_F0__FLD LPDDR4__DENALI_CTL_37__TWTR_F0
 
-#define LPDDR4__DENALI_CTL_38_READ_MASK				              0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_38_WRITE_MASK				             0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK				           0x000000FFU
-#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_38_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_38_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_38__TRP_F0_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_38__TRP_F0_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_38__TRP_F0_WIDTH                                   8U
 #define LPDDR4__TRP_F0__REG DENALI_CTL_38
 #define LPDDR4__TRP_F0__FLD LPDDR4__DENALI_CTL_38__TRP_F0
 
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK				          0x0001FF00U
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH								  9U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_38__TFAW_F0_WIDTH                                  9U
 #define LPDDR4__TFAW_F0__REG DENALI_CTL_38
 #define LPDDR4__TFAW_F0__FLD LPDDR4__DENALI_CTL_38__TFAW_F0
 
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_38__TRRD_F1_WIDTH                                  8U
 #define LPDDR4__TRRD_F1__REG DENALI_CTL_38
 #define LPDDR4__TRRD_F1__FLD LPDDR4__DENALI_CTL_38__TRRD_F1
 
-#define LPDDR4__DENALI_CTL_39_READ_MASK				              0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_39_WRITE_MASK				             0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK				           0x000001FFU
-#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH								   9U
+#define LPDDR4__DENALI_CTL_39_READ_MASK                              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_39_WRITE_MASK                             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_39__TRC_F1_MASK                           0x000001FFU
+#define LPDDR4__DENALI_CTL_39__TRC_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_39__TRC_F1_WIDTH                                   9U
 #define LPDDR4__TRC_F1__REG DENALI_CTL_39
 #define LPDDR4__TRC_F1__FLD LPDDR4__DENALI_CTL_39__TRC_F1
 
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK				      0x00FF0000U
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_39__TRAS_MIN_F1_WIDTH                              8U
 #define LPDDR4__TRAS_MIN_F1__REG DENALI_CTL_39
 #define LPDDR4__TRAS_MIN_F1__FLD LPDDR4__DENALI_CTL_39__TRAS_MIN_F1
 
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK				          0x3F000000U
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH								  6U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_MASK                          0x3F000000U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_39__TWTR_F1_WIDTH                                  6U
 #define LPDDR4__TWTR_F1__REG DENALI_CTL_39
 #define LPDDR4__TWTR_F1__FLD LPDDR4__DENALI_CTL_39__TWTR_F1
 
-#define LPDDR4__DENALI_CTL_40_READ_MASK				              0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_40_WRITE_MASK				             0xFF01FFFFU
-#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK				           0x000000FFU
-#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_40_READ_MASK                              0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_40_WRITE_MASK                             0xFF01FFFFU
+#define LPDDR4__DENALI_CTL_40__TRP_F1_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_40__TRP_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_40__TRP_F1_WIDTH                                   8U
 #define LPDDR4__TRP_F1__REG DENALI_CTL_40
 #define LPDDR4__TRP_F1__FLD LPDDR4__DENALI_CTL_40__TRP_F1
 
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK				          0x0001FF00U
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH								  9U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_40__TFAW_F1_WIDTH                                  9U
 #define LPDDR4__TFAW_F1__REG DENALI_CTL_40
 #define LPDDR4__TFAW_F1__FLD LPDDR4__DENALI_CTL_40__TFAW_F1
 
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_40__TRRD_F2_WIDTH                                  8U
 #define LPDDR4__TRRD_F2__REG DENALI_CTL_40
 #define LPDDR4__TRRD_F2__FLD LPDDR4__DENALI_CTL_40__TRRD_F2
 
-#define LPDDR4__DENALI_CTL_41_READ_MASK				              0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_41_WRITE_MASK				             0x3FFF01FFU
-#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK				           0x000001FFU
-#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH								   9U
+#define LPDDR4__DENALI_CTL_41_READ_MASK                              0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_41_WRITE_MASK                             0x3FFF01FFU
+#define LPDDR4__DENALI_CTL_41__TRC_F2_MASK                           0x000001FFU
+#define LPDDR4__DENALI_CTL_41__TRC_F2_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_41__TRC_F2_WIDTH                                   9U
 #define LPDDR4__TRC_F2__REG DENALI_CTL_41
 #define LPDDR4__TRC_F2__FLD LPDDR4__DENALI_CTL_41__TRC_F2
 
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK				      0x00FF0000U
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_41__TRAS_MIN_F2_WIDTH                              8U
 #define LPDDR4__TRAS_MIN_F2__REG DENALI_CTL_41
 #define LPDDR4__TRAS_MIN_F2__FLD LPDDR4__DENALI_CTL_41__TRAS_MIN_F2
 
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK				          0x3F000000U
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH								  6U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_MASK                          0x3F000000U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_41__TWTR_F2_WIDTH                                  6U
 #define LPDDR4__TWTR_F2__REG DENALI_CTL_41
 #define LPDDR4__TWTR_F2__FLD LPDDR4__DENALI_CTL_41__TWTR_F2
 
-#define LPDDR4__DENALI_CTL_42_READ_MASK				              0x3F01FFFFU
-#define LPDDR4__DENALI_CTL_42_WRITE_MASK				             0x3F01FFFFU
-#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK				           0x000000FFU
-#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_42_READ_MASK                              0x3F01FFFFU
+#define LPDDR4__DENALI_CTL_42_WRITE_MASK                             0x3F01FFFFU
+#define LPDDR4__DENALI_CTL_42__TRP_F2_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_42__TRP_F2_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_42__TRP_F2_WIDTH                                   8U
 #define LPDDR4__TRP_F2__REG DENALI_CTL_42
 #define LPDDR4__TRP_F2__FLD LPDDR4__DENALI_CTL_42__TRP_F2
 
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK				          0x0001FF00U
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH								  9U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_MASK                          0x0001FF00U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_42__TFAW_F2_WIDTH                                  9U
 #define LPDDR4__TFAW_F2__REG DENALI_CTL_42
 #define LPDDR4__TFAW_F2__FLD LPDDR4__DENALI_CTL_42__TFAW_F2
 
-#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK				           0x3F000000U
-#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH								   6U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_MASK                           0x3F000000U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_42__TCCDMW_WIDTH                                   6U
 #define LPDDR4__TCCDMW__REG DENALI_CTL_42
 #define LPDDR4__TCCDMW__FLD LPDDR4__DENALI_CTL_42__TCCDMW
 
-#define LPDDR4__DENALI_CTL_43_READ_MASK				              0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_43_WRITE_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK				          0x000000FFU
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_43_READ_MASK                              0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_43_WRITE_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_43__TRTP_F0_WIDTH                                  8U
 #define LPDDR4__TRTP_F0__REG DENALI_CTL_43
 #define LPDDR4__TRTP_F0__FLD LPDDR4__DENALI_CTL_43__TRTP_F0
 
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_43__TMRD_F0_WIDTH                                  8U
 #define LPDDR4__TMRD_F0__REG DENALI_CTL_43
 #define LPDDR4__TMRD_F0__FLD LPDDR4__DENALI_CTL_43__TMRD_F0
 
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_43__TMOD_F0_WIDTH                                  8U
 #define LPDDR4__TMOD_F0__REG DENALI_CTL_43
 #define LPDDR4__TMOD_F0__FLD LPDDR4__DENALI_CTL_43__TMOD_F0
 
-#define LPDDR4__DENALI_CTL_44_READ_MASK				              0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_44_WRITE_MASK				             0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK				      0x0001FFFFU
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH				             17U
+#define LPDDR4__DENALI_CTL_44_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_44_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_MASK                      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_44__TRAS_MAX_F0_WIDTH                             17U
 #define LPDDR4__TRAS_MAX_F0__REG DENALI_CTL_44
 #define LPDDR4__TRAS_MAX_F0__FLD LPDDR4__DENALI_CTL_44__TRAS_MAX_F0
 
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK				          0x1F000000U
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH								  5U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_44__TCKE_F0_WIDTH                                  5U
 #define LPDDR4__TCKE_F0__REG DENALI_CTL_44
 #define LPDDR4__TCKE_F0__FLD LPDDR4__DENALI_CTL_44__TCKE_F0
 
-#define LPDDR4__DENALI_CTL_45_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_45_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK				        0x000000FFU
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT								0U
-#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH								8U
+#define LPDDR4__DENALI_CTL_45_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_45__TCKESR_F0_WIDTH                                8U
 #define LPDDR4__TCKESR_F0__REG DENALI_CTL_45
 #define LPDDR4__TCKESR_F0__FLD LPDDR4__DENALI_CTL_45__TCKESR_F0
 
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_45__TRTP_F1_WIDTH                                  8U
 #define LPDDR4__TRTP_F1__REG DENALI_CTL_45
 #define LPDDR4__TRTP_F1__FLD LPDDR4__DENALI_CTL_45__TRTP_F1
 
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_45__TMRD_F1_WIDTH                                  8U
 #define LPDDR4__TMRD_F1__REG DENALI_CTL_45
 #define LPDDR4__TMRD_F1__FLD LPDDR4__DENALI_CTL_45__TMRD_F1
 
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_45__TMOD_F1_WIDTH                                  8U
 #define LPDDR4__TMOD_F1__REG DENALI_CTL_45
 #define LPDDR4__TMOD_F1__FLD LPDDR4__DENALI_CTL_45__TMOD_F1
 
-#define LPDDR4__DENALI_CTL_46_READ_MASK				              0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_46_WRITE_MASK				             0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK				      0x0001FFFFU
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH				             17U
+#define LPDDR4__DENALI_CTL_46_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_46_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_MASK                      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_46__TRAS_MAX_F1_WIDTH                             17U
 #define LPDDR4__TRAS_MAX_F1__REG DENALI_CTL_46
 #define LPDDR4__TRAS_MAX_F1__FLD LPDDR4__DENALI_CTL_46__TRAS_MAX_F1
 
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK				          0x1F000000U
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH								  5U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_46__TCKE_F1_WIDTH                                  5U
 #define LPDDR4__TCKE_F1__REG DENALI_CTL_46
 #define LPDDR4__TCKE_F1__FLD LPDDR4__DENALI_CTL_46__TCKE_F1
 
-#define LPDDR4__DENALI_CTL_47_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_47_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK				        0x000000FFU
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH								8U
+#define LPDDR4__DENALI_CTL_47_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_47_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_47__TCKESR_F1_WIDTH                                8U
 #define LPDDR4__TCKESR_F1__REG DENALI_CTL_47
 #define LPDDR4__TCKESR_F1__FLD LPDDR4__DENALI_CTL_47__TCKESR_F1
 
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_47__TRTP_F2_WIDTH                                  8U
 #define LPDDR4__TRTP_F2__REG DENALI_CTL_47
 #define LPDDR4__TRTP_F2__FLD LPDDR4__DENALI_CTL_47__TRTP_F2
 
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_47__TMRD_F2_WIDTH                                  8U
 #define LPDDR4__TMRD_F2__REG DENALI_CTL_47
 #define LPDDR4__TMRD_F2__FLD LPDDR4__DENALI_CTL_47__TMRD_F2
 
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_47__TMOD_F2_WIDTH                                  8U
 #define LPDDR4__TMOD_F2__REG DENALI_CTL_47
 #define LPDDR4__TMOD_F2__FLD LPDDR4__DENALI_CTL_47__TMOD_F2
 
-#define LPDDR4__DENALI_CTL_48_READ_MASK				              0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_48_WRITE_MASK				             0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK				      0x0001FFFFU
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH				             17U
+#define LPDDR4__DENALI_CTL_48_READ_MASK                              0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_48_WRITE_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_MASK                      0x0001FFFFU
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_48__TRAS_MAX_F2_WIDTH                             17U
 #define LPDDR4__TRAS_MAX_F2__REG DENALI_CTL_48
 #define LPDDR4__TRAS_MAX_F2__FLD LPDDR4__DENALI_CTL_48__TRAS_MAX_F2
 
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK				          0x1F000000U
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH								  5U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_48__TCKE_F2_WIDTH                                  5U
 #define LPDDR4__TCKE_F2__REG DENALI_CTL_48
 #define LPDDR4__TCKE_F2__FLD LPDDR4__DENALI_CTL_48__TCKE_F2
 
-#define LPDDR4__DENALI_CTL_49_READ_MASK				              0x070707FFU
-#define LPDDR4__DENALI_CTL_49_WRITE_MASK				             0x070707FFU
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK				        0x000000FFU
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH								8U
+#define LPDDR4__DENALI_CTL_49_READ_MASK                              0x070707FFU
+#define LPDDR4__DENALI_CTL_49_WRITE_MASK                             0x070707FFU
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_49__TCKESR_F2_WIDTH                                8U
 #define LPDDR4__TCKESR_F2__REG DENALI_CTL_49
 #define LPDDR4__TCKESR_F2__FLD LPDDR4__DENALI_CTL_49__TCKESR_F2
 
-#define LPDDR4__DENALI_CTL_49__TPPD_MASK				             0x00000700U
-#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT								     8U
-#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH								     3U
+#define LPDDR4__DENALI_CTL_49__TPPD_MASK                             0x00000700U
+#define LPDDR4__DENALI_CTL_49__TPPD_SHIFT                                     8U
+#define LPDDR4__DENALI_CTL_49__TPPD_WIDTH                                     3U
 #define LPDDR4__TPPD__REG DENALI_CTL_49
 #define LPDDR4__TPPD__FLD LPDDR4__DENALI_CTL_49__TPPD
 
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK				     0x00070000U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH				             3U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_MASK                     0x00070000U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED4_WIDTH                             3U
 #define LPDDR4__MC_RESERVED4__REG DENALI_CTL_49
 #define LPDDR4__MC_RESERVED4__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED4
 
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK				     0x07000000U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH				             3U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_49__MC_RESERVED5_WIDTH                             3U
 #define LPDDR4__MC_RESERVED5__REG DENALI_CTL_49
 #define LPDDR4__MC_RESERVED5__FLD LPDDR4__DENALI_CTL_49__MC_RESERVED5
 
-#define LPDDR4__DENALI_CTL_50_READ_MASK				              0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_50_WRITE_MASK				             0xFFFFFF01U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK				      0x00000001U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET				              0U
+#define LPDDR4__DENALI_CTL_50_READ_MASK                              0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_50_WRITE_MASK                             0xFFFFFF01U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_50__WRITEINTERP_WOSET                              0U
 #define LPDDR4__WRITEINTERP__REG DENALI_CTL_50
 #define LPDDR4__WRITEINTERP__FLD LPDDR4__DENALI_CTL_50__WRITEINTERP
 
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_50__TRCD_F0_WIDTH                                  8U
 #define LPDDR4__TRCD_F0__REG DENALI_CTL_50
 #define LPDDR4__TRCD_F0__FLD LPDDR4__DENALI_CTL_50__TRCD_F0
 
-#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK				           0x00FF0000U
-#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT								  16U
-#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_MASK                           0x00FF0000U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_50__TWR_F0_WIDTH                                   8U
 #define LPDDR4__TWR_F0__REG DENALI_CTL_50
 #define LPDDR4__TWR_F0__FLD LPDDR4__DENALI_CTL_50__TWR_F0
 
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_50__TRCD_F1_WIDTH                                  8U
 #define LPDDR4__TRCD_F1__REG DENALI_CTL_50
 #define LPDDR4__TRCD_F1__FLD LPDDR4__DENALI_CTL_50__TRCD_F1
 
-#define LPDDR4__DENALI_CTL_51_READ_MASK				              0x0FFFFFFFU
-#define LPDDR4__DENALI_CTL_51_WRITE_MASK				             0x0FFFFFFFU
-#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK				           0x000000FFU
-#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_51_READ_MASK                              0x0FFFFFFFU
+#define LPDDR4__DENALI_CTL_51_WRITE_MASK                             0x0FFFFFFFU
+#define LPDDR4__DENALI_CTL_51__TWR_F1_MASK                           0x000000FFU
+#define LPDDR4__DENALI_CTL_51__TWR_F1_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_51__TWR_F1_WIDTH                                   8U
 #define LPDDR4__TWR_F1__REG DENALI_CTL_51
 #define LPDDR4__TWR_F1__FLD LPDDR4__DENALI_CTL_51__TWR_F1
 
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_51__TRCD_F2_WIDTH                                  8U
 #define LPDDR4__TRCD_F2__REG DENALI_CTL_51
 #define LPDDR4__TRCD_F2__FLD LPDDR4__DENALI_CTL_51__TRCD_F2
 
-#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK				           0x00FF0000U
-#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT								  16U
-#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_MASK                           0x00FF0000U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_51__TWR_F2_WIDTH                                   8U
 #define LPDDR4__TWR_F2__REG DENALI_CTL_51
 #define LPDDR4__TWR_F2__FLD LPDDR4__DENALI_CTL_51__TWR_F2
 
-#define LPDDR4__DENALI_CTL_51__TMRR_MASK				             0x0F000000U
-#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT								    24U
-#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH								     4U
+#define LPDDR4__DENALI_CTL_51__TMRR_MASK                             0x0F000000U
+#define LPDDR4__DENALI_CTL_51__TMRR_SHIFT                                    24U
+#define LPDDR4__DENALI_CTL_51__TMRR_WIDTH                                     4U
 #define LPDDR4__TMRR__REG DENALI_CTL_51
 #define LPDDR4__TMRR__FLD LPDDR4__DENALI_CTL_51__TMRR
 
-#define LPDDR4__DENALI_CTL_52_READ_MASK				              0x3F03FF1FU
-#define LPDDR4__DENALI_CTL_52_WRITE_MASK				             0x3F03FF1FU
-#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK				          0x0000001FU
-#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH								  5U
+#define LPDDR4__DENALI_CTL_52_READ_MASK                              0x3F03FF1FU
+#define LPDDR4__DENALI_CTL_52_WRITE_MASK                             0x3F03FF1FU
+#define LPDDR4__DENALI_CTL_52__TCACKEL_MASK                          0x0000001FU
+#define LPDDR4__DENALI_CTL_52__TCACKEL_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_52__TCACKEL_WIDTH                                  5U
 #define LPDDR4__TCACKEL__REG DENALI_CTL_52
 #define LPDDR4__TCACKEL__FLD LPDDR4__DENALI_CTL_52__TCACKEL
 
-#define LPDDR4__DENALI_CTL_52__TCAENT_MASK				           0x0003FF00U
-#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT								   8U
-#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH								  10U
+#define LPDDR4__DENALI_CTL_52__TCAENT_MASK                           0x0003FF00U
+#define LPDDR4__DENALI_CTL_52__TCAENT_SHIFT                                   8U
+#define LPDDR4__DENALI_CTL_52__TCAENT_WIDTH                                  10U
 #define LPDDR4__TCAENT__REG DENALI_CTL_52
 #define LPDDR4__TCAENT__FLD LPDDR4__DENALI_CTL_52__TCAENT
 
-#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK				           0x3F000000U
-#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH								   6U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_MASK                           0x3F000000U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_52__TCAMRD_WIDTH                                   6U
 #define LPDDR4__TCAMRD__REG DENALI_CTL_52
 #define LPDDR4__TCAMRD__FLD LPDDR4__DENALI_CTL_52__TCAMRD
 
-#define LPDDR4__DENALI_CTL_53_READ_MASK				              0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_53_WRITE_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK				           0x0000001FU
-#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH								   5U
+#define LPDDR4__DENALI_CTL_53_READ_MASK                              0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_53_WRITE_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_53__TCAEXT_MASK                           0x0000001FU
+#define LPDDR4__DENALI_CTL_53__TCAEXT_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_53__TCAEXT_WIDTH                                   5U
 #define LPDDR4__TCAEXT__REG DENALI_CTL_53
 #define LPDDR4__TCAEXT__FLD LPDDR4__DENALI_CTL_53__TCAEXT
 
-#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK				          0x00001F00U
-#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH								  5U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_MASK                          0x00001F00U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_53__TCACKEH_WIDTH                                  5U
 #define LPDDR4__TCACKEH__REG DENALI_CTL_53
 #define LPDDR4__TCACKEH__FLD LPDDR4__DENALI_CTL_53__TCACKEH
 
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK				          0x001F0000U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH								  5U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_MASK                          0x001F0000U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F0_WIDTH                                  5U
 #define LPDDR4__TMRZ_F0__REG DENALI_CTL_53
 #define LPDDR4__TMRZ_F0__FLD LPDDR4__DENALI_CTL_53__TMRZ_F0
 
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK				          0x1F000000U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH								  5U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_MASK                          0x1F000000U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_53__TMRZ_F1_WIDTH                                  5U
 #define LPDDR4__TMRZ_F1__REG DENALI_CTL_53
 #define LPDDR4__TMRZ_F1__FLD LPDDR4__DENALI_CTL_53__TMRZ_F1
 
-#define LPDDR4__DENALI_CTL_54_READ_MASK				              0x0101011FU
-#define LPDDR4__DENALI_CTL_54_WRITE_MASK				             0x0101011FU
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK				          0x0000001FU
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH								  5U
+#define LPDDR4__DENALI_CTL_54_READ_MASK                              0x0101011FU
+#define LPDDR4__DENALI_CTL_54_WRITE_MASK                             0x0101011FU
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_MASK                          0x0000001FU
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_54__TMRZ_F2_WIDTH                                  5U
 #define LPDDR4__TMRZ_F2__REG DENALI_CTL_54
 #define LPDDR4__TMRZ_F2__FLD LPDDR4__DENALI_CTL_54__TMRZ_F2
 
-#define LPDDR4__DENALI_CTL_54__AP_MASK				               0x00000100U
-#define LPDDR4__DENALI_CTL_54__AP_SHIFT								       8U
-#define LPDDR4__DENALI_CTL_54__AP_WIDTH								       1U
-#define LPDDR4__DENALI_CTL_54__AP_WOCLR								       0U
-#define LPDDR4__DENALI_CTL_54__AP_WOSET								       0U
+#define LPDDR4__DENALI_CTL_54__AP_MASK                               0x00000100U
+#define LPDDR4__DENALI_CTL_54__AP_SHIFT                                       8U
+#define LPDDR4__DENALI_CTL_54__AP_WIDTH                                       1U
+#define LPDDR4__DENALI_CTL_54__AP_WOCLR                                       0U
+#define LPDDR4__DENALI_CTL_54__AP_WOSET                                       0U
 #define LPDDR4__AP__REG DENALI_CTL_54
 #define LPDDR4__AP__FLD LPDDR4__DENALI_CTL_54__AP
 
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK				     0x00010000U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET				             0U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_54__CONCURRENTAP_WOSET                             0U
 #define LPDDR4__CONCURRENTAP__REG DENALI_CTL_54
 #define LPDDR4__CONCURRENTAP__FLD LPDDR4__DENALI_CTL_54__CONCURRENTAP
 
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET				             0U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT_WOSET                             0U
 #define LPDDR4__TRAS_LOCKOUT__REG DENALI_CTL_54
 #define LPDDR4__TRAS_LOCKOUT__FLD LPDDR4__DENALI_CTL_54__TRAS_LOCKOUT
 
-#define LPDDR4__DENALI_CTL_55_READ_MASK				              0x1FFFFFFFU
-#define LPDDR4__DENALI_CTL_55_WRITE_MASK				             0x1FFFFFFFU
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK				          0x000000FFU
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_55_READ_MASK                              0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_55_WRITE_MASK                             0x1FFFFFFFU
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_55__TDAL_F0_WIDTH                                  8U
 #define LPDDR4__TDAL_F0__REG DENALI_CTL_55
 #define LPDDR4__TDAL_F0__FLD LPDDR4__DENALI_CTL_55__TDAL_F0
 
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK				          0x0000FF00U
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_MASK                          0x0000FF00U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_55__TDAL_F1_WIDTH                                  8U
 #define LPDDR4__TDAL_F1__REG DENALI_CTL_55
 #define LPDDR4__TDAL_F1__FLD LPDDR4__DENALI_CTL_55__TDAL_F1
 
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_55__TDAL_F2_WIDTH                                  8U
 #define LPDDR4__TDAL_F2__REG DENALI_CTL_55
 #define LPDDR4__TDAL_F2__FLD LPDDR4__DENALI_CTL_55__TDAL_F2
 
-#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK				           0x1F000000U
-#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH								   5U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_MASK                           0x1F000000U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_55__BSTLEN_WIDTH                                   5U
 #define LPDDR4__BSTLEN__REG DENALI_CTL_55
 #define LPDDR4__BSTLEN__FLD LPDDR4__DENALI_CTL_55__BSTLEN
 
-#define LPDDR4__DENALI_CTL_56_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_56_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK				      0x000000FFU
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_56_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_56_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_0_WIDTH                              8U
 #define LPDDR4__TRP_AB_F0_0__REG DENALI_CTL_56
 #define LPDDR4__TRP_AB_F0_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_0
 
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F1_0_WIDTH                              8U
 #define LPDDR4__TRP_AB_F1_0__REG DENALI_CTL_56
 #define LPDDR4__TRP_AB_F1_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F1_0
 
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK				      0x00FF0000U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_MASK                      0x00FF0000U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F2_0_WIDTH                              8U
 #define LPDDR4__TRP_AB_F2_0__REG DENALI_CTL_56
 #define LPDDR4__TRP_AB_F2_0__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F2_0
 
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK				      0xFF000000U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_56__TRP_AB_F0_1_WIDTH                              8U
 #define LPDDR4__TRP_AB_F0_1__REG DENALI_CTL_56
 #define LPDDR4__TRP_AB_F0_1__FLD LPDDR4__DENALI_CTL_56__TRP_AB_F0_1
 
-#define LPDDR4__DENALI_CTL_57_READ_MASK				              0x0301FFFFU
-#define LPDDR4__DENALI_CTL_57_WRITE_MASK				             0x0301FFFFU
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK				      0x000000FFU
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_57_READ_MASK                              0x0301FFFFU
+#define LPDDR4__DENALI_CTL_57_WRITE_MASK                             0x0301FFFFU
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F1_1_WIDTH                              8U
 #define LPDDR4__TRP_AB_F1_1__REG DENALI_CTL_57
 #define LPDDR4__TRP_AB_F1_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F1_1
 
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_57__TRP_AB_F2_1_WIDTH                              8U
 #define LPDDR4__TRP_AB_F2_1__REG DENALI_CTL_57
 #define LPDDR4__TRP_AB_F2_1__FLD LPDDR4__DENALI_CTL_57__TRP_AB_F2_1
 
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK				  0x00010000U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET				          0U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE_WOSET                          0U
 #define LPDDR4__REG_DIMM_ENABLE__REG DENALI_CTL_57
 #define LPDDR4__REG_DIMM_ENABLE__FLD LPDDR4__DENALI_CTL_57__REG_DIMM_ENABLE
 
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK				     0x03000000U
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH				             2U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_MASK                     0x03000000U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_57__MC_RESERVED6_WIDTH                             2U
 #define LPDDR4__MC_RESERVED6__REG DENALI_CTL_57
 #define LPDDR4__MC_RESERVED6__FLD LPDDR4__DENALI_CTL_57__MC_RESERVED6
 
-#define LPDDR4__DENALI_CTL_58_READ_MASK				              0x0101017FU
-#define LPDDR4__DENALI_CTL_58_WRITE_MASK				             0x0101017FU
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK				     0x0000007FU
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH				             7U
+#define LPDDR4__DENALI_CTL_58_READ_MASK                              0x0101017FU
+#define LPDDR4__DENALI_CTL_58_WRITE_MASK                             0x0101017FU
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_MASK                     0x0000007FU
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED7_WIDTH                             7U
 #define LPDDR4__MC_RESERVED7__REG DENALI_CTL_58
 #define LPDDR4__MC_RESERVED7__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED7
 
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK				 0x00000100U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET				         0U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_MASK                 0x00000100U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN_WOSET                         0U
 #define LPDDR4__OPTIMAL_RMODW_EN__REG DENALI_CTL_58
 #define LPDDR4__OPTIMAL_RMODW_EN__FLD LPDDR4__DENALI_CTL_58__OPTIMAL_RMODW_EN
 
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK				     0x00010000U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET				             0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_58__MC_RESERVED8_WOSET                             0U
 #define LPDDR4__MC_RESERVED8__REG DENALI_CTL_58
 #define LPDDR4__MC_RESERVED8__FLD LPDDR4__DENALI_CTL_58__MC_RESERVED8
 
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET				             0U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_58__NO_MEMORY_DM_WOSET                             0U
 #define LPDDR4__NO_MEMORY_DM__REG DENALI_CTL_58
 #define LPDDR4__NO_MEMORY_DM__FLD LPDDR4__DENALI_CTL_58__NO_MEMORY_DM
 
-#define LPDDR4__DENALI_CTL_59_READ_MASK				              0x07010100U
-#define LPDDR4__DENALI_CTL_59_WRITE_MASK				             0x07010100U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK				         0x00000001U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH								 1U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR								 0U
-#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET								 0U
+#define LPDDR4__DENALI_CTL_59_READ_MASK                              0x07010100U
+#define LPDDR4__DENALI_CTL_59_WRITE_MASK                             0x07010100U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_MASK                         0x00000001U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_59__AREFRESH_WOSET                                 0U
 #define LPDDR4__AREFRESH__REG DENALI_CTL_59
 #define LPDDR4__AREFRESH__FLD LPDDR4__DENALI_CTL_59__AREFRESH
 
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK				      0x00000100U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET				              0U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_59__AREF_STATUS_WOSET                              0U
 #define LPDDR4__AREF_STATUS__REG DENALI_CTL_59
 #define LPDDR4__AREF_STATUS__FLD LPDDR4__DENALI_CTL_59__AREF_STATUS
 
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK				      0x00010000U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET				              0U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_59__TREF_ENABLE_WOSET                              0U
 #define LPDDR4__TREF_ENABLE__REG DENALI_CTL_59
 #define LPDDR4__TREF_ENABLE__FLD LPDDR4__DENALI_CTL_59__TREF_ENABLE
 
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK				     0x07000000U
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH				             3U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_59__MC_RESERVED9_WIDTH                             3U
 #define LPDDR4__MC_RESERVED9__REG DENALI_CTL_59
 #define LPDDR4__MC_RESERVED9__FLD LPDDR4__DENALI_CTL_59__MC_RESERVED9
 
-#define LPDDR4__DENALI_CTL_60_READ_MASK				              0x0003FF3FU
-#define LPDDR4__DENALI_CTL_60_WRITE_MASK				             0x0003FF3FU
+#define LPDDR4__DENALI_CTL_60_READ_MASK                              0x0003FF3FU
+#define LPDDR4__DENALI_CTL_60_WRITE_MASK                             0x0003FF3FU
 #define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_MASK  0x0000003FU
 #define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_SHIFT          0U
 #define LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH_WIDTH          6U
 #define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__REG DENALI_CTL_60
 #define LPDDR4__CS_COMPARISON_FOR_REFRESH_DEPTH__FLD LPDDR4__DENALI_CTL_60__CS_COMPARISON_FOR_REFRESH_DEPTH
 
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK				          0x0003FF00U
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT								  8U
-#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH								 10U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_MASK                          0x0003FF00U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_SHIFT                                  8U
+#define LPDDR4__DENALI_CTL_60__TRFC_F0_WIDTH                                 10U
 #define LPDDR4__TRFC_F0__REG DENALI_CTL_60
 #define LPDDR4__TRFC_F0__FLD LPDDR4__DENALI_CTL_60__TRFC_F0
 
-#define LPDDR4__DENALI_CTL_61_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK				          0x000FFFFFU
-#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH								 20U
+#define LPDDR4__DENALI_CTL_61_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TREF_F0_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_61__TREF_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_61__TREF_F0_WIDTH                                 20U
 #define LPDDR4__TREF_F0__REG DENALI_CTL_61
 #define LPDDR4__TREF_F0__FLD LPDDR4__DENALI_CTL_61__TREF_F0
 
-#define LPDDR4__DENALI_CTL_62_READ_MASK				              0x000003FFU
-#define LPDDR4__DENALI_CTL_62_WRITE_MASK				             0x000003FFU
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK				          0x000003FFU
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH								 10U
+#define LPDDR4__DENALI_CTL_62_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_62_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_62__TRFC_F1_WIDTH                                 10U
 #define LPDDR4__TRFC_F1__REG DENALI_CTL_62
 #define LPDDR4__TRFC_F1__FLD LPDDR4__DENALI_CTL_62__TRFC_F1
 
-#define LPDDR4__DENALI_CTL_63_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK				          0x000FFFFFU
-#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH								 20U
+#define LPDDR4__DENALI_CTL_63_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TREF_F1_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_63__TREF_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_63__TREF_F1_WIDTH                                 20U
 #define LPDDR4__TREF_F1__REG DENALI_CTL_63
 #define LPDDR4__TREF_F1__FLD LPDDR4__DENALI_CTL_63__TREF_F1
 
-#define LPDDR4__DENALI_CTL_64_READ_MASK				              0x000003FFU
-#define LPDDR4__DENALI_CTL_64_WRITE_MASK				             0x000003FFU
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK				          0x000003FFU
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH								 10U
+#define LPDDR4__DENALI_CTL_64_READ_MASK                              0x000003FFU
+#define LPDDR4__DENALI_CTL_64_WRITE_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_64__TRFC_F2_WIDTH                                 10U
 #define LPDDR4__TRFC_F2__REG DENALI_CTL_64
 #define LPDDR4__TRFC_F2__FLD LPDDR4__DENALI_CTL_64__TRFC_F2
 
-#define LPDDR4__DENALI_CTL_65_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK				          0x000FFFFFU
-#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH								 20U
+#define LPDDR4__DENALI_CTL_65_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65__TREF_F2_MASK                          0x000FFFFFU
+#define LPDDR4__DENALI_CTL_65__TREF_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_65__TREF_F2_WIDTH                                 20U
 #define LPDDR4__TREF_F2__REG DENALI_CTL_65
 #define LPDDR4__TREF_F2__FLD LPDDR4__DENALI_CTL_65__TREF_F2
 
-#define LPDDR4__DENALI_CTL_66_READ_MASK				              0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66_WRITE_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK				    0x000FFFFFU
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH				           20U
+#define LPDDR4__DENALI_CTL_66_READ_MASK                              0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66_WRITE_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_MASK                    0x000FFFFFU
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_66__TREF_INTERVAL_WIDTH                           20U
 #define LPDDR4__TREF_INTERVAL__REG DENALI_CTL_66
 #define LPDDR4__TREF_INTERVAL__FLD LPDDR4__DENALI_CTL_66__TREF_INTERVAL
 
-#define LPDDR4__DENALI_CTL_67_READ_MASK				              0x03FF0101U
-#define LPDDR4__DENALI_CTL_67_WRITE_MASK				             0x03FF0101U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK				           0x00000001U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT								   0U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH								   1U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR								   0U
-#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET								   0U
+#define LPDDR4__DENALI_CTL_67_READ_MASK                              0x03FF0101U
+#define LPDDR4__DENALI_CTL_67_WRITE_MASK                             0x03FF0101U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_MASK                           0x00000001U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_SHIFT                                   0U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WIDTH                                   1U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WOCLR                                   0U
+#define LPDDR4__DENALI_CTL_67__PBR_EN_WOSET                                   0U
 #define LPDDR4__PBR_EN__REG DENALI_CTL_67
 #define LPDDR4__PBR_EN__FLD LPDDR4__DENALI_CTL_67__PBR_EN
 
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK				0x00000100U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET				        0U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_MASK                0x00000100U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER_WOSET                        0U
 #define LPDDR4__PBR_NUMERIC_ORDER__REG DENALI_CTL_67
 #define LPDDR4__PBR_NUMERIC_ORDER__FLD LPDDR4__DENALI_CTL_67__PBR_NUMERIC_ORDER
 
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK				       0x03FF0000U
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH				              10U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_MASK                       0x03FF0000U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_67__TRFC_PB_F0_WIDTH                              10U
 #define LPDDR4__TRFC_PB_F0__REG DENALI_CTL_67
 #define LPDDR4__TRFC_PB_F0__FLD LPDDR4__DENALI_CTL_67__TRFC_PB_F0
 
-#define LPDDR4__DENALI_CTL_68_READ_MASK				              0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_68_WRITE_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH				             16U
+#define LPDDR4__DENALI_CTL_68_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_68_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_68__TREFI_PB_F0_WIDTH                             16U
 #define LPDDR4__TREFI_PB_F0__REG DENALI_CTL_68
 #define LPDDR4__TREFI_PB_F0__FLD LPDDR4__DENALI_CTL_68__TREFI_PB_F0
 
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK				       0x03FF0000U
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH				              10U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_MASK                       0x03FF0000U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_68__TRFC_PB_F1_WIDTH                              10U
 #define LPDDR4__TRFC_PB_F1__REG DENALI_CTL_68
 #define LPDDR4__TRFC_PB_F1__FLD LPDDR4__DENALI_CTL_68__TRFC_PB_F1
 
-#define LPDDR4__DENALI_CTL_69_READ_MASK				              0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_69_WRITE_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH				             16U
+#define LPDDR4__DENALI_CTL_69_READ_MASK                              0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_69_WRITE_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_69__TREFI_PB_F1_WIDTH                             16U
 #define LPDDR4__TREFI_PB_F1__REG DENALI_CTL_69
 #define LPDDR4__TREFI_PB_F1__FLD LPDDR4__DENALI_CTL_69__TREFI_PB_F1
 
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK				       0x03FF0000U
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH				              10U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_MASK                       0x03FF0000U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_69__TRFC_PB_F2_WIDTH                              10U
 #define LPDDR4__TRFC_PB_F2__REG DENALI_CTL_69
 #define LPDDR4__TRFC_PB_F2__FLD LPDDR4__DENALI_CTL_69__TRFC_PB_F2
 
-#define LPDDR4__DENALI_CTL_70_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_70_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK				      0x0000FFFFU
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH				             16U
+#define LPDDR4__DENALI_CTL_70_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_70_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_MASK                      0x0000FFFFU
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_70__TREFI_PB_F2_WIDTH                             16U
 #define LPDDR4__TREFI_PB_F2__REG DENALI_CTL_70
 #define LPDDR4__TREFI_PB_F2__FLD LPDDR4__DENALI_CTL_70__TREFI_PB_F2
 
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT_WIDTH                       16U
 #define LPDDR4__PBR_MAX_BANK_WAIT__REG DENALI_CTL_70
 #define LPDDR4__PBR_MAX_BANK_WAIT__FLD LPDDR4__DENALI_CTL_70__PBR_MAX_BANK_WAIT
 
-#define LPDDR4__DENALI_CTL_71_READ_MASK				              0x1F1F010FU
-#define LPDDR4__DENALI_CTL_71_WRITE_MASK				             0x1F1F010FU
+#define LPDDR4__DENALI_CTL_71_READ_MASK                              0x1F1F010FU
+#define LPDDR4__DENALI_CTL_71_WRITE_MASK                             0x1F1F010FU
 #define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_MASK            0x0000000FU
-#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH				    4U
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY_WIDTH                    4U
 #define LPDDR4__PBR_BANK_SELECT_DELAY__REG DENALI_CTL_71
 #define LPDDR4__PBR_BANK_SELECT_DELAY__FLD LPDDR4__DENALI_CTL_71__PBR_BANK_SELECT_DELAY
 
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET				          0U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN_WOSET                          0U
 #define LPDDR4__PBR_CONT_REQ_EN__REG DENALI_CTL_71
 #define LPDDR4__PBR_CONT_REQ_EN__FLD LPDDR4__DENALI_CTL_71__PBR_CONT_REQ_EN
 
@@ -1290,518 +1290,518 @@
 #define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__REG DENALI_CTL_71
 #define LPDDR4__AREF_PBR_CONT_DIS_THRESHOLD__FLD LPDDR4__DENALI_CTL_71__AREF_PBR_CONT_DIS_THRESHOLD
 
-#define LPDDR4__DENALI_CTL_72_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_72_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK				         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH								16U
+#define LPDDR4__DENALI_CTL_72_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_72_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F0_WIDTH                                16U
 #define LPDDR4__TPDEX_F0__REG DENALI_CTL_72
 #define LPDDR4__TPDEX_F0__FLD LPDDR4__DENALI_CTL_72__TPDEX_F0
 
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK				         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT								16U
-#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH								16U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_72__TPDEX_F1_WIDTH                                16U
 #define LPDDR4__TPDEX_F1__REG DENALI_CTL_72
 #define LPDDR4__TPDEX_F1__FLD LPDDR4__DENALI_CTL_72__TPDEX_F1
 
-#define LPDDR4__DENALI_CTL_73_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_73_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK				         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH								16U
+#define LPDDR4__DENALI_CTL_73_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_73_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_MASK                         0x0000FFFFU
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_73__TPDEX_F2_WIDTH                                16U
 #define LPDDR4__TPDEX_F2__REG DENALI_CTL_73
 #define LPDDR4__TPDEX_F2__FLD LPDDR4__DENALI_CTL_73__TPDEX_F2
 
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK				         0x00FF0000U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT								16U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH								 8U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_MASK                         0x00FF0000U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F0_WIDTH                                 8U
 #define LPDDR4__TMRRI_F0__REG DENALI_CTL_73
 #define LPDDR4__TMRRI_F0__FLD LPDDR4__DENALI_CTL_73__TMRRI_F0
 
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK				         0xFF000000U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT								24U
-#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH								 8U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_MASK                         0xFF000000U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_73__TMRRI_F1_WIDTH                                 8U
 #define LPDDR4__TMRRI_F1__REG DENALI_CTL_73
 #define LPDDR4__TMRRI_F1__FLD LPDDR4__DENALI_CTL_73__TMRRI_F1
 
-#define LPDDR4__DENALI_CTL_74_READ_MASK				              0x1F1F1FFFU
-#define LPDDR4__DENALI_CTL_74_WRITE_MASK				             0x1F1F1FFFU
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK				         0x000000FFU
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH								 8U
+#define LPDDR4__DENALI_CTL_74_READ_MASK                              0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_74_WRITE_MASK                             0x1F1F1FFFU
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_MASK                         0x000000FFU
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_74__TMRRI_F2_WIDTH                                 8U
 #define LPDDR4__TMRRI_F2__REG DENALI_CTL_74
 #define LPDDR4__TMRRI_F2__FLD LPDDR4__DENALI_CTL_74__TMRRI_F2
 
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK				        0x00001F00U
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT								8U
-#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH								5U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_MASK                        0x00001F00U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_74__TCSCKE_F0_WIDTH                                5U
 #define LPDDR4__TCSCKE_F0__REG DENALI_CTL_74
 #define LPDDR4__TCSCKE_F0__FLD LPDDR4__DENALI_CTL_74__TCSCKE_F0
 
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_74__TCKELCS_F0_WIDTH                               5U
 #define LPDDR4__TCKELCS_F0__REG DENALI_CTL_74
 #define LPDDR4__TCKELCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKELCS_F0
 
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_74__TCKEHCS_F0_WIDTH                               5U
 #define LPDDR4__TCKEHCS_F0__REG DENALI_CTL_74
 #define LPDDR4__TCKEHCS_F0__FLD LPDDR4__DENALI_CTL_74__TCKEHCS_F0
 
-#define LPDDR4__DENALI_CTL_75_READ_MASK				              0x1F010F1FU
-#define LPDDR4__DENALI_CTL_75_WRITE_MASK				             0x1F010F1FU
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_75_READ_MASK                              0x1F010F1FU
+#define LPDDR4__DENALI_CTL_75_WRITE_MASK                             0x1F010F1FU
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_75__TMRWCKEL_F0_WIDTH                              5U
 #define LPDDR4__TMRWCKEL_F0__REG DENALI_CTL_75
 #define LPDDR4__TMRWCKEL_F0__FLD LPDDR4__DENALI_CTL_75__TMRWCKEL_F0
 
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK				        0x00000F00U
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT								8U
-#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH								4U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_75__TZQCKE_F0_WIDTH                                4U
 #define LPDDR4__TZQCKE_F0__REG DENALI_CTL_75
 #define LPDDR4__TZQCKE_F0__FLD LPDDR4__DENALI_CTL_75__TZQCKE_F0
 
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET				        0U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0_WOSET                        0U
 #define LPDDR4__CA_DEFAULT_VAL_F0__REG DENALI_CTL_75
 #define LPDDR4__CA_DEFAULT_VAL_F0__FLD LPDDR4__DENALI_CTL_75__CA_DEFAULT_VAL_F0
 
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK				        0x1F000000U
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH								5U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_MASK                        0x1F000000U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_75__TCSCKE_F1_WIDTH                                5U
 #define LPDDR4__TCSCKE_F1__REG DENALI_CTL_75
 #define LPDDR4__TCSCKE_F1__FLD LPDDR4__DENALI_CTL_75__TCSCKE_F1
 
-#define LPDDR4__DENALI_CTL_76_READ_MASK				              0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_76_WRITE_MASK				             0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK				       0x0000001FU
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_76_READ_MASK                              0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_76_WRITE_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_MASK                       0x0000001FU
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_76__TCKELCS_F1_WIDTH                               5U
 #define LPDDR4__TCKELCS_F1__REG DENALI_CTL_76
 #define LPDDR4__TCKELCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKELCS_F1
 
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK				       0x00001F00U
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_76__TCKEHCS_F1_WIDTH                               5U
 #define LPDDR4__TCKEHCS_F1__REG DENALI_CTL_76
 #define LPDDR4__TCKEHCS_F1__FLD LPDDR4__DENALI_CTL_76__TCKEHCS_F1
 
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK				      0x001F0000U
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_76__TMRWCKEL_F1_WIDTH                              5U
 #define LPDDR4__TMRWCKEL_F1__REG DENALI_CTL_76
 #define LPDDR4__TMRWCKEL_F1__FLD LPDDR4__DENALI_CTL_76__TMRWCKEL_F1
 
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK				        0x0F000000U
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH								4U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_MASK                        0x0F000000U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_76__TZQCKE_F1_WIDTH                                4U
 #define LPDDR4__TZQCKE_F1__REG DENALI_CTL_76
 #define LPDDR4__TZQCKE_F1__FLD LPDDR4__DENALI_CTL_76__TZQCKE_F1
 
-#define LPDDR4__DENALI_CTL_77_READ_MASK				              0x1F1F1F01U
-#define LPDDR4__DENALI_CTL_77_WRITE_MASK				             0x1F1F1F01U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK				0x00000001U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET				        0U
+#define LPDDR4__DENALI_CTL_77_READ_MASK                              0x1F1F1F01U
+#define LPDDR4__DENALI_CTL_77_WRITE_MASK                             0x1F1F1F01U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_MASK                0x00000001U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1_WOSET                        0U
 #define LPDDR4__CA_DEFAULT_VAL_F1__REG DENALI_CTL_77
 #define LPDDR4__CA_DEFAULT_VAL_F1__FLD LPDDR4__DENALI_CTL_77__CA_DEFAULT_VAL_F1
 
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK				        0x00001F00U
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT								8U
-#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH								5U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_MASK                        0x00001F00U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_77__TCSCKE_F2_WIDTH                                5U
 #define LPDDR4__TCSCKE_F2__REG DENALI_CTL_77
 #define LPDDR4__TCSCKE_F2__FLD LPDDR4__DENALI_CTL_77__TCSCKE_F2
 
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_77__TCKELCS_F2_WIDTH                               5U
 #define LPDDR4__TCKELCS_F2__REG DENALI_CTL_77
 #define LPDDR4__TCKELCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKELCS_F2
 
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_77__TCKEHCS_F2_WIDTH                               5U
 #define LPDDR4__TCKEHCS_F2__REG DENALI_CTL_77
 #define LPDDR4__TCKEHCS_F2__FLD LPDDR4__DENALI_CTL_77__TCKEHCS_F2
 
-#define LPDDR4__DENALI_CTL_78_READ_MASK				              0x00010F1FU
-#define LPDDR4__DENALI_CTL_78_WRITE_MASK				             0x00010F1FU
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_78_READ_MASK                              0x00010F1FU
+#define LPDDR4__DENALI_CTL_78_WRITE_MASK                             0x00010F1FU
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_78__TMRWCKEL_F2_WIDTH                              5U
 #define LPDDR4__TMRWCKEL_F2__REG DENALI_CTL_78
 #define LPDDR4__TMRWCKEL_F2__FLD LPDDR4__DENALI_CTL_78__TMRWCKEL_F2
 
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK				        0x00000F00U
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT								8U
-#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH								4U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_MASK                        0x00000F00U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_78__TZQCKE_F2_WIDTH                                4U
 #define LPDDR4__TZQCKE_F2__REG DENALI_CTL_78
 #define LPDDR4__TZQCKE_F2__FLD LPDDR4__DENALI_CTL_78__TZQCKE_F2
 
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET				        0U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2_WOSET                        0U
 #define LPDDR4__CA_DEFAULT_VAL_F2__REG DENALI_CTL_78
 #define LPDDR4__CA_DEFAULT_VAL_F2__FLD LPDDR4__DENALI_CTL_78__CA_DEFAULT_VAL_F2
 
-#define LPDDR4__DENALI_CTL_79_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_79_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK				          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH								 16U
+#define LPDDR4__DENALI_CTL_79_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_79_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_79__TXSR_F0_WIDTH                                 16U
 #define LPDDR4__TXSR_F0__REG DENALI_CTL_79
 #define LPDDR4__TXSR_F0__FLD LPDDR4__DENALI_CTL_79__TXSR_F0
 
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK				         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT								16U
-#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH								16U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_79__TXSNR_F0_WIDTH                                16U
 #define LPDDR4__TXSNR_F0__REG DENALI_CTL_79
 #define LPDDR4__TXSNR_F0__FLD LPDDR4__DENALI_CTL_79__TXSNR_F0
 
-#define LPDDR4__DENALI_CTL_80_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_80_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK				          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH								 16U
+#define LPDDR4__DENALI_CTL_80_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_80_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_80__TXSR_F1_WIDTH                                 16U
 #define LPDDR4__TXSR_F1__REG DENALI_CTL_80
 #define LPDDR4__TXSR_F1__FLD LPDDR4__DENALI_CTL_80__TXSR_F1
 
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK				         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT								16U
-#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH								16U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_80__TXSNR_F1_WIDTH                                16U
 #define LPDDR4__TXSNR_F1__REG DENALI_CTL_80
 #define LPDDR4__TXSNR_F1__FLD LPDDR4__DENALI_CTL_80__TXSNR_F1
 
-#define LPDDR4__DENALI_CTL_81_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_81_WRITE_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK				          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH								 16U
+#define LPDDR4__DENALI_CTL_81_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_81_WRITE_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_MASK                          0x0000FFFFU
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_81__TXSR_F2_WIDTH                                 16U
 #define LPDDR4__TXSR_F2__REG DENALI_CTL_81
 #define LPDDR4__TXSR_F2__FLD LPDDR4__DENALI_CTL_81__TXSR_F2
 
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK				         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT								16U
-#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH								16U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_MASK                         0xFFFF0000U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_81__TXSNR_F2_WIDTH                                16U
 #define LPDDR4__TXSNR_F2__REG DENALI_CTL_81
 #define LPDDR4__TXSNR_F2__FLD LPDDR4__DENALI_CTL_81__TXSNR_F2
 
-#define LPDDR4__DENALI_CTL_82_READ_MASK				              0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_82_WRITE_MASK				             0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_82_READ_MASK                              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_82_WRITE_MASK                             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_82__TCKELCMD_F0_WIDTH                              5U
 #define LPDDR4__TCKELCMD_F0__REG DENALI_CTL_82
 #define LPDDR4__TCKELCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKELCMD_F0
 
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_82__TCKEHCMD_F0_WIDTH                              5U
 #define LPDDR4__TCKEHCMD_F0__REG DENALI_CTL_82
 #define LPDDR4__TCKEHCMD_F0__FLD LPDDR4__DENALI_CTL_82__TCKEHCMD_F0
 
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_82__TCKCKEL_F0_WIDTH                               5U
 #define LPDDR4__TCKCKEL_F0__REG DENALI_CTL_82
 #define LPDDR4__TCKCKEL_F0__FLD LPDDR4__DENALI_CTL_82__TCKCKEL_F0
 
-#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK				           0xFF000000U
-#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_82__TSR_F0_WIDTH                                   8U
 #define LPDDR4__TSR_F0__REG DENALI_CTL_82
 #define LPDDR4__TSR_F0__FLD LPDDR4__DENALI_CTL_82__TSR_F0
 
-#define LPDDR4__DENALI_CTL_83_READ_MASK				              0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_83_WRITE_MASK				             0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK				        0x00000007U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT								0U
-#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH								3U
+#define LPDDR4__DENALI_CTL_83_READ_MASK                              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_83_WRITE_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_MASK                        0x00000007U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_83__TESCKE_F0_WIDTH                                3U
 #define LPDDR4__TESCKE_F0__REG DENALI_CTL_83
 #define LPDDR4__TESCKE_F0__FLD LPDDR4__DENALI_CTL_83__TESCKE_F0
 
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK				       0x00001F00U
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_83__TCKELPD_F0_WIDTH                               5U
 #define LPDDR4__TCKELPD_F0__REG DENALI_CTL_83
 #define LPDDR4__TCKELPD_F0__FLD LPDDR4__DENALI_CTL_83__TCKELPD_F0
 
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_83__TCSCKEH_F0_WIDTH                               5U
 #define LPDDR4__TCSCKEH_F0__REG DENALI_CTL_83
 #define LPDDR4__TCSCKEH_F0__FLD LPDDR4__DENALI_CTL_83__TCSCKEH_F0
 
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_83__TCMDCKE_F0_WIDTH                               5U
 #define LPDDR4__TCMDCKE_F0__REG DENALI_CTL_83
 #define LPDDR4__TCMDCKE_F0__FLD LPDDR4__DENALI_CTL_83__TCMDCKE_F0
 
-#define LPDDR4__DENALI_CTL_84_READ_MASK				              0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_84_WRITE_MASK				             0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_84_READ_MASK                              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_84_WRITE_MASK                             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_84__TCKELCMD_F1_WIDTH                              5U
 #define LPDDR4__TCKELCMD_F1__REG DENALI_CTL_84
 #define LPDDR4__TCKELCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKELCMD_F1
 
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_84__TCKEHCMD_F1_WIDTH                              5U
 #define LPDDR4__TCKEHCMD_F1__REG DENALI_CTL_84
 #define LPDDR4__TCKEHCMD_F1__FLD LPDDR4__DENALI_CTL_84__TCKEHCMD_F1
 
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_84__TCKCKEL_F1_WIDTH                               5U
 #define LPDDR4__TCKCKEL_F1__REG DENALI_CTL_84
 #define LPDDR4__TCKCKEL_F1__FLD LPDDR4__DENALI_CTL_84__TCKCKEL_F1
 
-#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK				           0xFF000000U
-#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_84__TSR_F1_WIDTH                                   8U
 #define LPDDR4__TSR_F1__REG DENALI_CTL_84
 #define LPDDR4__TSR_F1__FLD LPDDR4__DENALI_CTL_84__TSR_F1
 
-#define LPDDR4__DENALI_CTL_85_READ_MASK				              0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_85_WRITE_MASK				             0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK				        0x00000007U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH								3U
+#define LPDDR4__DENALI_CTL_85_READ_MASK                              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_85_WRITE_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_MASK                        0x00000007U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_85__TESCKE_F1_WIDTH                                3U
 #define LPDDR4__TESCKE_F1__REG DENALI_CTL_85
 #define LPDDR4__TESCKE_F1__FLD LPDDR4__DENALI_CTL_85__TESCKE_F1
 
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK				       0x00001F00U
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_85__TCKELPD_F1_WIDTH                               5U
 #define LPDDR4__TCKELPD_F1__REG DENALI_CTL_85
 #define LPDDR4__TCKELPD_F1__FLD LPDDR4__DENALI_CTL_85__TCKELPD_F1
 
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_85__TCSCKEH_F1_WIDTH                               5U
 #define LPDDR4__TCSCKEH_F1__REG DENALI_CTL_85
 #define LPDDR4__TCSCKEH_F1__FLD LPDDR4__DENALI_CTL_85__TCSCKEH_F1
 
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_85__TCMDCKE_F1_WIDTH                               5U
 #define LPDDR4__TCMDCKE_F1__REG DENALI_CTL_85
 #define LPDDR4__TCMDCKE_F1__FLD LPDDR4__DENALI_CTL_85__TCMDCKE_F1
 
-#define LPDDR4__DENALI_CTL_86_READ_MASK				              0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_86_WRITE_MASK				             0xFF1F1F1FU
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_86_READ_MASK                              0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_86_WRITE_MASK                             0xFF1F1F1FU
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_86__TCKELCMD_F2_WIDTH                              5U
 #define LPDDR4__TCKELCMD_F2__REG DENALI_CTL_86
 #define LPDDR4__TCKELCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKELCMD_F2
 
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_86__TCKEHCMD_F2_WIDTH                              5U
 #define LPDDR4__TCKEHCMD_F2__REG DENALI_CTL_86
 #define LPDDR4__TCKEHCMD_F2__FLD LPDDR4__DENALI_CTL_86__TCKEHCMD_F2
 
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_86__TCKCKEL_F2_WIDTH                               5U
 #define LPDDR4__TCKCKEL_F2__REG DENALI_CTL_86
 #define LPDDR4__TCKCKEL_F2__FLD LPDDR4__DENALI_CTL_86__TCKCKEL_F2
 
-#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK				           0xFF000000U
-#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH								   8U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_MASK                           0xFF000000U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_86__TSR_F2_WIDTH                                   8U
 #define LPDDR4__TSR_F2__REG DENALI_CTL_86
 #define LPDDR4__TSR_F2__FLD LPDDR4__DENALI_CTL_86__TSR_F2
 
-#define LPDDR4__DENALI_CTL_87_READ_MASK				              0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_87_WRITE_MASK				             0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK				        0x00000007U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT								0U
-#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH								3U
+#define LPDDR4__DENALI_CTL_87_READ_MASK                              0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_87_WRITE_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_MASK                        0x00000007U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_87__TESCKE_F2_WIDTH                                3U
 #define LPDDR4__TESCKE_F2__REG DENALI_CTL_87
 #define LPDDR4__TESCKE_F2__FLD LPDDR4__DENALI_CTL_87__TESCKE_F2
 
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK				       0x00001F00U
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_MASK                       0x00001F00U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_87__TCKELPD_F2_WIDTH                               5U
 #define LPDDR4__TCKELPD_F2__REG DENALI_CTL_87
 #define LPDDR4__TCKELPD_F2__FLD LPDDR4__DENALI_CTL_87__TCKELPD_F2
 
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK				       0x001F0000U
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_MASK                       0x001F0000U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_87__TCSCKEH_F2_WIDTH                               5U
 #define LPDDR4__TCSCKEH_F2__REG DENALI_CTL_87
 #define LPDDR4__TCSCKEH_F2__FLD LPDDR4__DENALI_CTL_87__TCSCKEH_F2
 
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_87__TCMDCKE_F2_WIDTH                               5U
 #define LPDDR4__TCMDCKE_F2__REG DENALI_CTL_87
 #define LPDDR4__TCMDCKE_F2__FLD LPDDR4__DENALI_CTL_87__TCMDCKE_F2
 
-#define LPDDR4__DENALI_CTL_88_READ_MASK				              0x07010101U
-#define LPDDR4__DENALI_CTL_88_WRITE_MASK				             0x07010101U
+#define LPDDR4__DENALI_CTL_88_READ_MASK                              0x07010101U
+#define LPDDR4__DENALI_CTL_88_WRITE_MASK                             0x07010101U
 #define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_MASK              0x00000001U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET				      0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT_WOSET                      0U
 #define LPDDR4__PWRUP_SREFRESH_EXIT__REG DENALI_CTL_88
 #define LPDDR4__PWRUP_SREFRESH_EXIT__FLD LPDDR4__DENALI_CTL_88__PWRUP_SREFRESH_EXIT
 
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK				    0x00000100U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET				            0U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_88__MC_RESERVED10_WOSET                            0U
 #define LPDDR4__MC_RESERVED10__REG DENALI_CTL_88
 #define LPDDR4__MC_RESERVED10__FLD LPDDR4__DENALI_CTL_88__MC_RESERVED10
 
 #define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_MASK            0x00010000U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET				    0U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH_WOSET                    0U
 #define LPDDR4__ENABLE_QUICK_SREFRESH__REG DENALI_CTL_88
 #define LPDDR4__ENABLE_QUICK_SREFRESH__FLD LPDDR4__DENALI_CTL_88__ENABLE_QUICK_SREFRESH
 
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK				        0x07000000U
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH								3U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_MASK                        0x07000000U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_88__CKE_DELAY_WIDTH                                3U
 #define LPDDR4__CKE_DELAY__REG DENALI_CTL_88
 #define LPDDR4__CKE_DELAY__FLD LPDDR4__DENALI_CTL_88__CKE_DELAY
 
-#define LPDDR4__DENALI_CTL_89_READ_MASK				              0x01010300U
-#define LPDDR4__DENALI_CTL_89_WRITE_MASK				             0x01010300U
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK				    0x0000001FU
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH				            5U
+#define LPDDR4__DENALI_CTL_89_READ_MASK                              0x01010300U
+#define LPDDR4__DENALI_CTL_89_WRITE_MASK                             0x01010300U
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_MASK                    0x0000001FU
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_89__MC_RESERVED11_WIDTH                            5U
 #define LPDDR4__MC_RESERVED11__REG DENALI_CTL_89
 #define LPDDR4__MC_RESERVED11__FLD LPDDR4__DENALI_CTL_89__MC_RESERVED11
 
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK				       0x00000300U
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH				               2U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_MASK                       0x00000300U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_89__DFS_STATUS_WIDTH                               2U
 #define LPDDR4__DFS_STATUS__REG DENALI_CTL_89
 #define LPDDR4__DFS_STATUS__FLD LPDDR4__DENALI_CTL_89__DFS_STATUS
 
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK				        0x00010000U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH								1U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR								0U
-#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET								0U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_MASK                        0x00010000U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_89__DFS_ZQ_EN_WOSET                                0U
 #define LPDDR4__DFS_ZQ_EN__REG DENALI_CTL_89
 #define LPDDR4__DFS_ZQ_EN__FLD LPDDR4__DENALI_CTL_89__DFS_ZQ_EN
 
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET				             0U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_89__DFS_CALVL_EN_WOSET                             0U
 #define LPDDR4__DFS_CALVL_EN__REG DENALI_CTL_89
 #define LPDDR4__DFS_CALVL_EN__FLD LPDDR4__DENALI_CTL_89__DFS_CALVL_EN
 
-#define LPDDR4__DENALI_CTL_90_READ_MASK				              0x00010101U
-#define LPDDR4__DENALI_CTL_90_WRITE_MASK				             0x00010101U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK				     0x00000001U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET				             0U
+#define LPDDR4__DENALI_CTL_90_READ_MASK                              0x00010101U
+#define LPDDR4__DENALI_CTL_90_WRITE_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN_WOSET                             0U
 #define LPDDR4__DFS_WRLVL_EN__REG DENALI_CTL_90
 #define LPDDR4__DFS_WRLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_WRLVL_EN
 
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK				     0x00000100U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET				             0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN_WOSET                             0U
 #define LPDDR4__DFS_RDLVL_EN__REG DENALI_CTL_90
 #define LPDDR4__DFS_RDLVL_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_EN
 
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET				        0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN_WOSET                        0U
 #define LPDDR4__DFS_RDLVL_GATE_EN__REG DENALI_CTL_90
 #define LPDDR4__DFS_RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_90__DFS_RDLVL_GATE_EN
 
-#define LPDDR4__DENALI_CTL_91_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_91_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_91_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_91_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_91
 #define LPDDR4__DFS_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_91
 #define LPDDR4__DFS_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_91__DFS_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_92_READ_MASK				              0x0707FFFFU
-#define LPDDR4__DENALI_CTL_92_WRITE_MASK				             0x0707FFFFU
+#define LPDDR4__DENALI_CTL_92_READ_MASK                              0x0707FFFFU
+#define LPDDR4__DENALI_CTL_92_WRITE_MASK                             0x0707FFFFU
 #define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_92
 #define LPDDR4__DFS_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_92__DFS_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK				    0x00070000U
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH				            3U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_MASK                    0x00070000U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG_WIDTH                            3U
 #define LPDDR4__ZQ_STATUS_LOG__REG DENALI_CTL_92
 #define LPDDR4__ZQ_STATUS_LOG__FLD LPDDR4__DENALI_CTL_92__ZQ_STATUS_LOG
 
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK				    0x07000000U
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH				            3U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_MASK                    0x07000000U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_92__MC_RESERVED12_WIDTH                            3U
 #define LPDDR4__MC_RESERVED12__REG DENALI_CTL_92
 #define LPDDR4__MC_RESERVED12__FLD LPDDR4__DENALI_CTL_92__MC_RESERVED12
 
-#define LPDDR4__DENALI_CTL_93_READ_MASK				              0xFFFFFF07U
-#define LPDDR4__DENALI_CTL_93_WRITE_MASK				             0xFFFFFF07U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK				    0x00000007U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH				            3U
+#define LPDDR4__DENALI_CTL_93_READ_MASK                              0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_93_WRITE_MASK                             0xFFFFFF07U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED13_WIDTH                            3U
 #define LPDDR4__MC_RESERVED13__REG DENALI_CTL_93
 #define LPDDR4__MC_RESERVED13__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED13
 
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK				    0x0000FF00U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH				            8U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_MASK                    0x0000FF00U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED14_WIDTH                            8U
 #define LPDDR4__MC_RESERVED14__REG DENALI_CTL_93
 #define LPDDR4__MC_RESERVED14__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED14
 
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK				    0x00FF0000U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH				            8U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_MASK                    0x00FF0000U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED15_WIDTH                            8U
 #define LPDDR4__MC_RESERVED15__REG DENALI_CTL_93
 #define LPDDR4__MC_RESERVED15__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED15
 
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK				    0xFF000000U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH				            8U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_MASK                    0xFF000000U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_93__MC_RESERVED16_WIDTH                            8U
 #define LPDDR4__MC_RESERVED16__REG DENALI_CTL_93
 #define LPDDR4__MC_RESERVED16__FLD LPDDR4__DENALI_CTL_93__MC_RESERVED16
 
-#define LPDDR4__DENALI_CTL_94_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_94_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_94_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_94_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_MASK    0x0000FFFFU
 #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_SHIFT            0U
 #define LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_NORM_THRESHOLD_F0_WIDTH           16U
@@ -1814,11 +1814,11 @@
 #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__REG DENALI_CTL_94
 #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_94__UPD_CTRLUPD_HIGH_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_95_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_95_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_95_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_95_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_MASK           0x0000FFFFU
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH				  16U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0_WIDTH                  16U
 #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__REG DENALI_CTL_95
 #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_TIMEOUT_F0
 
@@ -1828,8 +1828,8 @@
 #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_95
 #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_95__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_96_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_96_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_96_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_SHIFT      0U
 #define LPDDR4__DENALI_CTL_96__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0_WIDTH     16U
@@ -1842,8 +1842,8 @@
 #define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__REG DENALI_CTL_96
 #define LPDDR4__UPD_CTRLUPD_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_96__UPD_CTRLUPD_NORM_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_97_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_97_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_97_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_MASK    0x0000FFFFU
 #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_SHIFT            0U
 #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1_WIDTH           16U
@@ -1851,13 +1851,13 @@
 #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_HIGH_THRESHOLD_F1
 
 #define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH				  16U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1_WIDTH                  16U
 #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__REG DENALI_CTL_97
 #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_97__UPD_CTRLUPD_TIMEOUT_F1
 
-#define LPDDR4__DENALI_CTL_98_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_98_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_98_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_SHIFT      0U
 #define LPDDR4__DENALI_CTL_98__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1_WIDTH     16U
@@ -1870,8 +1870,8 @@
 #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_98
 #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_98__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_99_READ_MASK				              0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_99_WRITE_MASK				             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_READ_MASK                              0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_99_WRITE_MASK                             0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_MASK    0x0000FFFFU
 #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_SHIFT            0U
 #define LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_NORM_THRESHOLD_F2_WIDTH           16U
@@ -1884,11 +1884,11 @@
 #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__REG DENALI_CTL_99
 #define LPDDR4__UPD_CTRLUPD_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_99__UPD_CTRLUPD_HIGH_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_100_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_100_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_100_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_100_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2_WIDTH                 16U
 #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__REG DENALI_CTL_100
 #define LPDDR4__UPD_CTRLUPD_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_TIMEOUT_F2
 
@@ -1898,195 +1898,195 @@
 #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_100
 #define LPDDR4__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_100__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_101_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_101_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_101_WRITE_MASK                            0x0000FFFFU
 #define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_SHIFT     0U
 #define LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2_WIDTH    16U
 #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_101
 #define LPDDR4__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_101__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_102_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_102_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_102_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH				    32U
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0_WIDTH                    32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_F0__REG DENALI_CTL_102
 #define LPDDR4__TDFI_PHYMSTR_MAX_F0__FLD LPDDR4__DENALI_CTL_102__TDFI_PHYMSTR_MAX_F0
 
-#define LPDDR4__DENALI_CTL_103_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_103_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_103_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_SHIFT               0U
 #define LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__REG DENALI_CTL_103
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F0__FLD LPDDR4__DENALI_CTL_103__TDFI_PHYMSTR_MAX_TYPE0_F0
 
-#define LPDDR4__DENALI_CTL_104_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_104_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_104_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_SHIFT               0U
 #define LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__REG DENALI_CTL_104
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F0__FLD LPDDR4__DENALI_CTL_104__TDFI_PHYMSTR_MAX_TYPE1_F0
 
-#define LPDDR4__DENALI_CTL_105_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_105_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_105_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_SHIFT               0U
 #define LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__REG DENALI_CTL_105
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F0__FLD LPDDR4__DENALI_CTL_105__TDFI_PHYMSTR_MAX_TYPE2_F0
 
-#define LPDDR4__DENALI_CTL_106_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_106_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_106_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_SHIFT               0U
 #define LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__REG DENALI_CTL_106
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F0__FLD LPDDR4__DENALI_CTL_106__TDFI_PHYMSTR_MAX_TYPE3_F0
 
-#define LPDDR4__DENALI_CTL_107_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_107_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_107_WRITE_MASK                            0x0000FFFFU
 #define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_SHIFT       0U
 #define LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0_WIDTH      16U
 #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_107
 #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_107__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_108_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_108_WRITE_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_108_WRITE_MASK                            0x000FFFFFU
 #define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_MASK            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH				   20U
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0_WIDTH                   20U
 #define LPDDR4__TDFI_PHYMSTR_RESP_F0__REG DENALI_CTL_108
 #define LPDDR4__TDFI_PHYMSTR_RESP_F0__FLD LPDDR4__DENALI_CTL_108__TDFI_PHYMSTR_RESP_F0
 
-#define LPDDR4__DENALI_CTL_109_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_109_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_109_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH				    32U
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1_WIDTH                    32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_F1__REG DENALI_CTL_109
 #define LPDDR4__TDFI_PHYMSTR_MAX_F1__FLD LPDDR4__DENALI_CTL_109__TDFI_PHYMSTR_MAX_F1
 
-#define LPDDR4__DENALI_CTL_110_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_110_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_110_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_SHIFT               0U
 #define LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__REG DENALI_CTL_110
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F1__FLD LPDDR4__DENALI_CTL_110__TDFI_PHYMSTR_MAX_TYPE0_F1
 
-#define LPDDR4__DENALI_CTL_111_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_111_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_111_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_SHIFT               0U
 #define LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__REG DENALI_CTL_111
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F1__FLD LPDDR4__DENALI_CTL_111__TDFI_PHYMSTR_MAX_TYPE1_F1
 
-#define LPDDR4__DENALI_CTL_112_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_112_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_112_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_SHIFT               0U
 #define LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__REG DENALI_CTL_112
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F1__FLD LPDDR4__DENALI_CTL_112__TDFI_PHYMSTR_MAX_TYPE2_F1
 
-#define LPDDR4__DENALI_CTL_113_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_113_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_113_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_SHIFT               0U
 #define LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__REG DENALI_CTL_113
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F1__FLD LPDDR4__DENALI_CTL_113__TDFI_PHYMSTR_MAX_TYPE3_F1
 
-#define LPDDR4__DENALI_CTL_114_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_114_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_114_WRITE_MASK                            0x0000FFFFU
 #define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_SHIFT       0U
 #define LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1_WIDTH      16U
 #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_114
 #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_114__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_115_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_115_WRITE_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_115_WRITE_MASK                            0x000FFFFFU
 #define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_MASK            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH				   20U
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1_WIDTH                   20U
 #define LPDDR4__TDFI_PHYMSTR_RESP_F1__REG DENALI_CTL_115
 #define LPDDR4__TDFI_PHYMSTR_RESP_F1__FLD LPDDR4__DENALI_CTL_115__TDFI_PHYMSTR_RESP_F1
 
-#define LPDDR4__DENALI_CTL_116_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_116_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_116_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH				    32U
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2_WIDTH                    32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_F2__REG DENALI_CTL_116
 #define LPDDR4__TDFI_PHYMSTR_MAX_F2__FLD LPDDR4__DENALI_CTL_116__TDFI_PHYMSTR_MAX_F2
 
-#define LPDDR4__DENALI_CTL_117_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_117_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_117_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_SHIFT               0U
 #define LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__REG DENALI_CTL_117
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE0_F2__FLD LPDDR4__DENALI_CTL_117__TDFI_PHYMSTR_MAX_TYPE0_F2
 
-#define LPDDR4__DENALI_CTL_118_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_118_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_118_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_SHIFT               0U
 #define LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__REG DENALI_CTL_118
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE1_F2__FLD LPDDR4__DENALI_CTL_118__TDFI_PHYMSTR_MAX_TYPE1_F2
 
-#define LPDDR4__DENALI_CTL_119_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_119_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_119_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_SHIFT               0U
 #define LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__REG DENALI_CTL_119
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE2_F2__FLD LPDDR4__DENALI_CTL_119__TDFI_PHYMSTR_MAX_TYPE2_F2
 
-#define LPDDR4__DENALI_CTL_120_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_120_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_120_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_SHIFT               0U
 #define LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2_WIDTH              32U
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__REG DENALI_CTL_120
 #define LPDDR4__TDFI_PHYMSTR_MAX_TYPE3_F2__FLD LPDDR4__DENALI_CTL_120__TDFI_PHYMSTR_MAX_TYPE3_F2
 
-#define LPDDR4__DENALI_CTL_121_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_121_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_121_WRITE_MASK                            0x0000FFFFU
 #define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_SHIFT       0U
 #define LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2_WIDTH      16U
 #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_121
 #define LPDDR4__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_121__PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_122_READ_MASK				             0x010FFFFFU
-#define LPDDR4__DENALI_CTL_122_WRITE_MASK				            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_122_READ_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_122_WRITE_MASK                            0x010FFFFFU
 #define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_MASK            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH				   20U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2_WIDTH                   20U
 #define LPDDR4__TDFI_PHYMSTR_RESP_F2__REG DENALI_CTL_122
 #define LPDDR4__TDFI_PHYMSTR_RESP_F2__FLD LPDDR4__DENALI_CTL_122__TDFI_PHYMSTR_RESP_F2
 
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET				         0U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF_WOSET                         0U
 #define LPDDR4__PHYMSTR_NO_AREF__REG DENALI_CTL_122
 #define LPDDR4__PHYMSTR_NO_AREF__FLD LPDDR4__DENALI_CTL_122__PHYMSTR_NO_AREF
 
-#define LPDDR4__DENALI_CTL_123_READ_MASK				             0x00010103U
-#define LPDDR4__DENALI_CTL_123_WRITE_MASK				            0x00010103U
+#define LPDDR4__DENALI_CTL_123_READ_MASK                             0x00010103U
+#define LPDDR4__DENALI_CTL_123_WRITE_MASK                            0x00010103U
 #define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_MASK            0x00000003U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH				    2U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS_WIDTH                    2U
 #define LPDDR4__PHYMSTR_ERROR_STATUS__REG DENALI_CTL_123
 #define LPDDR4__PHYMSTR_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_ERROR_STATUS
 
@@ -2106,8 +2106,8 @@
 #define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__REG DENALI_CTL_123
 #define LPDDR4__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE__FLD LPDDR4__DENALI_CTL_123__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE
 
-#define LPDDR4__DENALI_CTL_124_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_124_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_124_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_124_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_SHIFT           0U
 #define LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_NORM_THRESHOLD_F0_WIDTH          16U
@@ -2120,11 +2120,11 @@
 #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__REG DENALI_CTL_124
 #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_124__MRR_TEMPCHK_HIGH_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_125_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_125_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_125_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_125_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0_WIDTH                 16U
 #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__REG DENALI_CTL_125
 #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_TIMEOUT_F0
 
@@ -2134,8 +2134,8 @@
 #define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__REG DENALI_CTL_125
 #define LPDDR4__MRR_TEMPCHK_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_125__MRR_TEMPCHK_NORM_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_126_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_126_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_126_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_SHIFT           0U
 #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1_WIDTH          16U
@@ -2143,13 +2143,13 @@
 #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_HIGH_THRESHOLD_F1
 
 #define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_MASK          0xFFFF0000U
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1_WIDTH                 16U
 #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__REG DENALI_CTL_126
 #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_126__MRR_TEMPCHK_TIMEOUT_F1
 
-#define LPDDR4__DENALI_CTL_127_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_127_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_127_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_SHIFT           0U
 #define LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_NORM_THRESHOLD_F2_WIDTH          16U
@@ -2162,141 +2162,141 @@
 #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__REG DENALI_CTL_127
 #define LPDDR4__MRR_TEMPCHK_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_127__MRR_TEMPCHK_HIGH_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_128_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_CTL_128_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_128_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_128_WRITE_MASK                            0x0001FFFFU
 #define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2_WIDTH                 16U
 #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__REG DENALI_CTL_128
 #define LPDDR4__MRR_TEMPCHK_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_128__MRR_TEMPCHK_TIMEOUT_F2
 
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK				     0x00010000U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET				             0U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_128__PPR_CONTROL_WOSET                             0U
 #define LPDDR4__PPR_CONTROL__REG DENALI_CTL_128
 #define LPDDR4__PPR_CONTROL__FLD LPDDR4__DENALI_CTL_128__PPR_CONTROL
 
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK				     0x07000000U
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH				             3U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_MASK                     0x07000000U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_128__PPR_COMMAND_WIDTH                             3U
 #define LPDDR4__PPR_COMMAND__REG DENALI_CTL_128
 #define LPDDR4__PPR_COMMAND__FLD LPDDR4__DENALI_CTL_128__PPR_COMMAND
 
-#define LPDDR4__DENALI_CTL_129_READ_MASK				             0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_129_WRITE_MASK				            0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK				 0x000000FFU
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH				         8U
+#define LPDDR4__DENALI_CTL_129_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_129_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW_WIDTH                         8U
 #define LPDDR4__PPR_COMMAND_MRW__REG DENALI_CTL_129
 #define LPDDR4__PPR_COMMAND_MRW__FLD LPDDR4__DENALI_CTL_129__PPR_COMMAND_MRW
 
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK				 0x01FFFF00U
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH				        17U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_MASK                 0x01FFFF00U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS_WIDTH                        17U
 #define LPDDR4__PPR_ROW_ADDRESS__REG DENALI_CTL_129
 #define LPDDR4__PPR_ROW_ADDRESS__FLD LPDDR4__DENALI_CTL_129__PPR_ROW_ADDRESS
 
-#define LPDDR4__DENALI_CTL_130_READ_MASK				             0x01030107U
-#define LPDDR4__DENALI_CTL_130_WRITE_MASK				            0x01030107U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK				0x00000007U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH				        3U
+#define LPDDR4__DENALI_CTL_130_READ_MASK                             0x01030107U
+#define LPDDR4__DENALI_CTL_130_WRITE_MASK                            0x01030107U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS_WIDTH                        3U
 #define LPDDR4__PPR_BANK_ADDRESS__REG DENALI_CTL_130
 #define LPDDR4__PPR_BANK_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_BANK_ADDRESS
 
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET				          0U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS_WOSET                          0U
 #define LPDDR4__PPR_CS_ADDRESS__REG DENALI_CTL_130
 #define LPDDR4__PPR_CS_ADDRESS__FLD LPDDR4__DENALI_CTL_130__PPR_CS_ADDRESS
 
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK				      0x00030000U
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH				              2U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_MASK                      0x00030000U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_130__PPR_STATUS_WIDTH                              2U
 #define LPDDR4__PPR_STATUS__REG DENALI_CTL_130
 #define LPDDR4__PPR_STATUS__FLD LPDDR4__DENALI_CTL_130__PPR_STATUS
 
 #define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_MASK               0x01000000U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH				       1U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR				       0U
-#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET				       0U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL_WOSET                       0U
 #define LPDDR4__FM_OVRIDE_CONTROL__REG DENALI_CTL_130
 #define LPDDR4__FM_OVRIDE_CONTROL__FLD LPDDR4__DENALI_CTL_130__FM_OVRIDE_CONTROL
 
-#define LPDDR4__DENALI_CTL_131_READ_MASK				             0xFFFFFF03U
-#define LPDDR4__DENALI_CTL_131_WRITE_MASK				            0xFFFFFF03U
+#define LPDDR4__DENALI_CTL_131_READ_MASK                             0xFFFFFF03U
+#define LPDDR4__DENALI_CTL_131_WRITE_MASK                            0xFFFFFF03U
 #define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_MASK         0x00000003U
-#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH				 2U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE_WIDTH                 2U
 #define LPDDR4__LOWPOWER_REFRESH_ENABLE__REG DENALI_CTL_131
 #define LPDDR4__LOWPOWER_REFRESH_ENABLE__FLD LPDDR4__DENALI_CTL_131__LOWPOWER_REFRESH_ENABLE
 
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK				        0x0000FF00U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT								8U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH								8U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F0_WIDTH                                8U
 #define LPDDR4__CKSRE_F0__REG DENALI_CTL_131
 #define LPDDR4__CKSRE_F0__FLD LPDDR4__DENALI_CTL_131__CKSRE_F0
 
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH								8U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_131__CKSRX_F0_WIDTH                                8U
 #define LPDDR4__CKSRX_F0__REG DENALI_CTL_131
 #define LPDDR4__CKSRX_F0__FLD LPDDR4__DENALI_CTL_131__CKSRX_F0
 
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK				        0xFF000000U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH								8U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_MASK                        0xFF000000U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_131__CKSRE_F1_WIDTH                                8U
 #define LPDDR4__CKSRE_F1__REG DENALI_CTL_131
 #define LPDDR4__CKSRE_F1__FLD LPDDR4__DENALI_CTL_131__CKSRE_F1
 
-#define LPDDR4__DENALI_CTL_132_READ_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_132_WRITE_MASK				            0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK				        0x000000FFU
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH								8U
+#define LPDDR4__DENALI_CTL_132_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_132_WRITE_MASK                            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_MASK                        0x000000FFU
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F1_WIDTH                                8U
 #define LPDDR4__CKSRX_F1__REG DENALI_CTL_132
 #define LPDDR4__CKSRX_F1__FLD LPDDR4__DENALI_CTL_132__CKSRX_F1
 
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK				        0x0000FF00U
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT								8U
-#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH								8U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_MASK                        0x0000FF00U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_132__CKSRE_F2_WIDTH                                8U
 #define LPDDR4__CKSRE_F2__REG DENALI_CTL_132
 #define LPDDR4__CKSRE_F2__FLD LPDDR4__DENALI_CTL_132__CKSRE_F2
 
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK				        0x00FF0000U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH								8U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_MASK                        0x00FF0000U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_132__CKSRX_F2_WIDTH                                8U
 #define LPDDR4__CKSRX_F2__REG DENALI_CTL_132
 #define LPDDR4__CKSRX_F2__FLD LPDDR4__DENALI_CTL_132__CKSRX_F2
 
-#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK				          0x7F000000U
-#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH								  7U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_MASK                          0x7F000000U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_132__LP_CMD_WIDTH                                  7U
 #define LPDDR4__LP_CMD__REG DENALI_CTL_132
 #define LPDDR4__LP_CMD__FLD LPDDR4__DENALI_CTL_132__LP_CMD
 
-#define LPDDR4__DENALI_CTL_133_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_133_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_133_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_133_WRITE_MASK                            0x0F0F0F0FU
 #define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_MASK         0x0000000FU
-#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH				 4U
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0_WIDTH                 4U
 #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__REG DENALI_CTL_133
 #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_CTRL_IDLE_WAKEUP_F0
 
 #define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_MASK          0x00000F00U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH				  4U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0_WIDTH                  4U
 #define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG DENALI_CTL_133
 #define LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_SHORT_WAKEUP_F0
 
 #define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_MASK           0x000F0000U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH				   4U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0_WIDTH                   4U
 #define LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG DENALI_CTL_133
 #define LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_WAKEUP_F0
 
@@ -2306,23 +2306,23 @@
 #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_133
 #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_133__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0
 
-#define LPDDR4__DENALI_CTL_134_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_134_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK				0x0000000FU
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH				        4U
+#define LPDDR4__DENALI_CTL_134_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_134_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_MASK                0x0000000FU
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0_WIDTH                        4U
 #define LPDDR4__LPI_PD_WAKEUP_F0__REG DENALI_CTL_134
 #define LPDDR4__LPI_PD_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_PD_WAKEUP_F0
 
 #define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_MASK        0x00000F00U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT				8U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH				4U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_SHIFT                8U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0_WIDTH                4U
 #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG DENALI_CTL_134
 #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_SHORT_WAKEUP_F0
 
 #define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_MASK         0x000F0000U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH				 4U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0_WIDTH                 4U
 #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG DENALI_CTL_134
 #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_WAKEUP_F0
 
@@ -2332,60 +2332,60 @@
 #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG DENALI_CTL_134
 #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_134__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0
 
-#define LPDDR4__DENALI_CTL_135_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_135_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_135_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_135_WRITE_MASK                            0x0F0F0F0FU
 #define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_MASK             0x0000000FU
-#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH				     4U
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0_WIDTH                     4U
 #define LPDDR4__LPI_TIMER_WAKEUP_F0__REG DENALI_CTL_135
 #define LPDDR4__LPI_TIMER_WAKEUP_F0__FLD LPDDR4__DENALI_CTL_135__LPI_TIMER_WAKEUP_F0
 
 #define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_MASK         0x00000F00U
-#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT				 8U
-#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH				 4U
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1_WIDTH                 4U
 #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__REG DENALI_CTL_135
 #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_CTRL_IDLE_WAKEUP_F1
 
 #define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_MASK          0x000F0000U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH				  4U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1_WIDTH                  4U
 #define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG DENALI_CTL_135
 #define LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_SHORT_WAKEUP_F1
 
 #define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_MASK           0x0F000000U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT				  24U
-#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH				   4U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_SHIFT                  24U
+#define LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1_WIDTH                   4U
 #define LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG DENALI_CTL_135
 #define LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_135__LPI_SR_LONG_WAKEUP_F1
 
-#define LPDDR4__DENALI_CTL_136_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_136_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_136_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_136_WRITE_MASK                            0x0F0F0F0FU
 #define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
 #define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT        0U
 #define LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH        4U
 #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG DENALI_CTL_136
 #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1
 
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK				0x00000F00U
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH				        4U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_MASK                0x00000F00U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1_WIDTH                        4U
 #define LPDDR4__LPI_PD_WAKEUP_F1__REG DENALI_CTL_136
 #define LPDDR4__LPI_PD_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_PD_WAKEUP_F1
 
 #define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_MASK        0x000F0000U
 #define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_SHIFT               16U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH				4U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1_WIDTH                4U
 #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG DENALI_CTL_136
 #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_SHORT_WAKEUP_F1
 
 #define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_MASK         0x0F000000U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT				24U
-#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH				 4U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_SHIFT                24U
+#define LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1_WIDTH                 4U
 #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG DENALI_CTL_136
 #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_136__LPI_SRPD_LONG_WAKEUP_F1
 
-#define LPDDR4__DENALI_CTL_137_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_137_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_137_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_137_WRITE_MASK                            0x0F0F0F0FU
 #define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_MASK 0x0000000FU
 #define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_SHIFT      0U
 #define LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1_WIDTH      4U
@@ -2393,28 +2393,28 @@
 #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1
 
 #define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_MASK             0x00000F00U
-#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH				     4U
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1_WIDTH                     4U
 #define LPDDR4__LPI_TIMER_WAKEUP_F1__REG DENALI_CTL_137
 #define LPDDR4__LPI_TIMER_WAKEUP_F1__FLD LPDDR4__DENALI_CTL_137__LPI_TIMER_WAKEUP_F1
 
 #define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_MASK         0x000F0000U
-#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH				 4U
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2_WIDTH                 4U
 #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__REG DENALI_CTL_137
 #define LPDDR4__LPI_CTRL_IDLE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_CTRL_IDLE_WAKEUP_F2
 
 #define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_MASK          0x0F000000U
-#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT				 24U
-#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH				  4U
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2_WIDTH                  4U
 #define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG DENALI_CTL_137
 #define LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_137__LPI_SR_SHORT_WAKEUP_F2
 
-#define LPDDR4__DENALI_CTL_138_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_138_WRITE_MASK				            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_138_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_138_WRITE_MASK                            0x0F0F0F0FU
 #define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_MASK           0x0000000FU
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH				   4U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2_WIDTH                   4U
 #define LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG DENALI_CTL_138
 #define LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_WAKEUP_F2
 
@@ -2424,23 +2424,23 @@
 #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG DENALI_CTL_138
 #define LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2
 
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK				0x000F0000U
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH				        4U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2_WIDTH                        4U
 #define LPDDR4__LPI_PD_WAKEUP_F2__REG DENALI_CTL_138
 #define LPDDR4__LPI_PD_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_PD_WAKEUP_F2
 
 #define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_MASK        0x0F000000U
 #define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_SHIFT               24U
-#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH				4U
+#define LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2_WIDTH                4U
 #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG DENALI_CTL_138
 #define LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_138__LPI_SRPD_SHORT_WAKEUP_F2
 
-#define LPDDR4__DENALI_CTL_139_READ_MASK				             0x3F0F0F0FU
-#define LPDDR4__DENALI_CTL_139_WRITE_MASK				            0x3F0F0F0FU
+#define LPDDR4__DENALI_CTL_139_READ_MASK                             0x3F0F0F0FU
+#define LPDDR4__DENALI_CTL_139_WRITE_MASK                            0x3F0F0F0FU
 #define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_MASK         0x0000000FU
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH				 4U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2_WIDTH                 4U
 #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG DENALI_CTL_139
 #define LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_WAKEUP_F2
 
@@ -2451,90 +2451,90 @@
 #define LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2
 
 #define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_MASK             0x000F0000U
-#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH				     4U
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2_WIDTH                     4U
 #define LPDDR4__LPI_TIMER_WAKEUP_F2__REG DENALI_CTL_139
 #define LPDDR4__LPI_TIMER_WAKEUP_F2__FLD LPDDR4__DENALI_CTL_139__LPI_TIMER_WAKEUP_F2
 
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK				   0x3F000000U
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH				           6U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_MASK                   0x3F000000U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN_WIDTH                           6U
 #define LPDDR4__LPI_WAKEUP_EN__REG DENALI_CTL_139
 #define LPDDR4__LPI_WAKEUP_EN__FLD LPDDR4__DENALI_CTL_139__LPI_WAKEUP_EN
 
-#define LPDDR4__DENALI_CTL_140_READ_MASK				             0x070FFF01U
-#define LPDDR4__DENALI_CTL_140_WRITE_MASK				            0x070FFF01U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK				 0x00000001U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET				         0U
+#define LPDDR4__DENALI_CTL_140_READ_MASK                             0x070FFF01U
+#define LPDDR4__DENALI_CTL_140_WRITE_MASK                            0x070FFF01U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN_WOSET                         0U
 #define LPDDR4__LPI_CTRL_REQ_EN__REG DENALI_CTL_140
 #define LPDDR4__LPI_CTRL_REQ_EN__FLD LPDDR4__DENALI_CTL_140__LPI_CTRL_REQ_EN
 
 #define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_MASK              0x000FFF00U
-#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH				     12U
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT_WIDTH                     12U
 #define LPDDR4__LPI_WAKEUP_TIMEOUT__REG DENALI_CTL_140
 #define LPDDR4__LPI_WAKEUP_TIMEOUT__FLD LPDDR4__DENALI_CTL_140__LPI_WAKEUP_TIMEOUT
 
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK				    0x07000000U
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH				            3U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_MASK                    0x07000000U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_140__TDFI_LP_RESP_WIDTH                            3U
 #define LPDDR4__TDFI_LP_RESP__REG DENALI_CTL_140
 #define LPDDR4__TDFI_LP_RESP__FLD LPDDR4__DENALI_CTL_140__TDFI_LP_RESP
 
-#define LPDDR4__DENALI_CTL_141_READ_MASK				             0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_141_WRITE_MASK				            0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_141_READ_MASK                             0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_141_WRITE_MASK                            0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS0_WIDTH                            7U
 #define LPDDR4__LP_STATE_CS0__REG DENALI_CTL_141
 #define LPDDR4__LP_STATE_CS0__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS0
 
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK				    0x00007F00U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_MASK                    0x00007F00U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_141__LP_STATE_CS1_WIDTH                            7U
 #define LPDDR4__LP_STATE_CS1__REG DENALI_CTL_141
 #define LPDDR4__LP_STATE_CS1__FLD LPDDR4__DENALI_CTL_141__LP_STATE_CS1
 
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK				0x000F0000U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH				        4U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_MASK                0x000F0000U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN_WIDTH                        4U
 #define LPDDR4__LP_AUTO_ENTRY_EN__REG DENALI_CTL_141
 #define LPDDR4__LP_AUTO_ENTRY_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_ENTRY_EN
 
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK				 0x0F000000U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH				         4U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN_WIDTH                         4U
 #define LPDDR4__LP_AUTO_EXIT_EN__REG DENALI_CTL_141
 #define LPDDR4__LP_AUTO_EXIT_EN__FLD LPDDR4__DENALI_CTL_141__LP_AUTO_EXIT_EN
 
-#define LPDDR4__DENALI_CTL_142_READ_MASK				             0x000FFF07U
-#define LPDDR4__DENALI_CTL_142_WRITE_MASK				            0x000FFF07U
+#define LPDDR4__DENALI_CTL_142_READ_MASK                             0x000FFF07U
+#define LPDDR4__DENALI_CTL_142_WRITE_MASK                            0x000FFF07U
 #define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_MASK             0x00000007U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH				     3U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN_WIDTH                     3U
 #define LPDDR4__LP_AUTO_MEM_GATE_EN__REG DENALI_CTL_142
 #define LPDDR4__LP_AUTO_MEM_GATE_EN__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_MEM_GATE_EN
 
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK				 0x000FFF00U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH				        12U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_MASK                 0x000FFF00U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE_WIDTH                        12U
 #define LPDDR4__LP_AUTO_PD_IDLE__REG DENALI_CTL_142
 #define LPDDR4__LP_AUTO_PD_IDLE__FLD LPDDR4__DENALI_CTL_142__LP_AUTO_PD_IDLE
 
-#define LPDDR4__DENALI_CTL_143_READ_MASK				             0xFFFF0FFFU
-#define LPDDR4__DENALI_CTL_143_WRITE_MASK				            0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_143_READ_MASK                             0xFFFF0FFFU
+#define LPDDR4__DENALI_CTL_143_WRITE_MASK                            0xFFFF0FFFU
 #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_MASK           0x00000FFFU
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH				  12U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE_WIDTH                  12U
 #define LPDDR4__LP_AUTO_SR_SHORT_IDLE__REG DENALI_CTL_143
 #define LPDDR4__LP_AUTO_SR_SHORT_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_SHORT_IDLE
 
 #define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_MASK            0x00FF0000U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH				    8U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE_WIDTH                    8U
 #define LPDDR4__LP_AUTO_SR_LONG_IDLE__REG DENALI_CTL_143
 #define LPDDR4__LP_AUTO_SR_LONG_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_IDLE
 
@@ -2544,25 +2544,25 @@
 #define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__REG DENALI_CTL_143
 #define LPDDR4__LP_AUTO_SR_LONG_MC_GATE_IDLE__FLD LPDDR4__DENALI_CTL_143__LP_AUTO_SR_LONG_MC_GATE_IDLE
 
-#define LPDDR4__DENALI_CTL_144_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_144_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_144_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_144_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__HW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_144
 #define LPDDR4__HW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__HW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_144
 #define LPDDR4__HW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_144__HW_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_145_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_145_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_145_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_145_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__HW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_145
 #define LPDDR4__HW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_145__HW_PROMOTE_THRESHOLD_F2
 
@@ -2572,10 +2572,10 @@
 #define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_145
 #define LPDDR4__LPC_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_145__LPC_PROMOTE_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_146_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_146_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_146_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_146_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT				0U
+#define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_SHIFT                0U
 #define LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1_WIDTH               16U
 #define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_146
 #define LPDDR4__LPC_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F1
@@ -2586,396 +2586,396 @@
 #define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_146
 #define LPDDR4__LPC_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_146__LPC_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_147_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_147_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_147_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_147_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_MASK               0x00000001U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH				       1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR				       0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET				       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN_WOSET                       0U
 #define LPDDR4__LPC_SR_CTRLUPD_EN__REG DENALI_CTL_147
 #define LPDDR4__LPC_SR_CTRLUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_CTRLUPD_EN
 
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK				0x00000100U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET				        0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_MASK                0x00000100U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN_WOSET                        0U
 #define LPDDR4__LPC_SR_PHYUPD_EN__REG DENALI_CTL_147
 #define LPDDR4__LPC_SR_PHYUPD_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYUPD_EN
 
 #define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_MASK               0x00010000U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH				       1U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR				       0U
-#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET				       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN_WOSET                       0U
 #define LPDDR4__LPC_SR_PHYMSTR_EN__REG DENALI_CTL_147
 #define LPDDR4__LPC_SR_PHYMSTR_EN__FLD LPDDR4__DENALI_CTL_147__LPC_SR_PHYMSTR_EN
 
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET				           0U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_147__MC_RESERVED17_WOSET                           0U
 #define LPDDR4__MC_RESERVED17__REG DENALI_CTL_147
 #define LPDDR4__MC_RESERVED17__FLD LPDDR4__DENALI_CTL_147__MC_RESERVED17
 
-#define LPDDR4__DENALI_CTL_148_READ_MASK				             0x3F3F0101U
-#define LPDDR4__DENALI_CTL_148_WRITE_MASK				            0x3F3F0101U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK				    0x00000001U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET				            0U
+#define LPDDR4__DENALI_CTL_148_READ_MASK                             0x3F3F0101U
+#define LPDDR4__DENALI_CTL_148_WRITE_MASK                            0x3F3F0101U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN_WOSET                            0U
 #define LPDDR4__LPC_SR_ZQ_EN__REG DENALI_CTL_148
 #define LPDDR4__LPC_SR_ZQ_EN__FLD LPDDR4__DENALI_CTL_148__LPC_SR_ZQ_EN
 
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK				     0x00000100U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET				             0U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_MASK                     0x00000100U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EN_WOSET                             0U
 #define LPDDR4__PCPCS_PD_EN__REG DENALI_CTL_148
 #define LPDDR4__PCPCS_PD_EN__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EN
 
 #define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_MASK            0x003F0000U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH				    6U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH_WIDTH                    6U
 #define LPDDR4__PCPCS_PD_ENTER_DEPTH__REG DENALI_CTL_148
 #define LPDDR4__PCPCS_PD_ENTER_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_ENTER_DEPTH
 
 #define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_MASK             0x3F000000U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT				    24U
-#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH				     6U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH_WIDTH                     6U
 #define LPDDR4__PCPCS_PD_EXIT_DEPTH__REG DENALI_CTL_148
 #define LPDDR4__PCPCS_PD_EXIT_DEPTH__FLD LPDDR4__DENALI_CTL_148__PCPCS_PD_EXIT_DEPTH
 
-#define LPDDR4__DENALI_CTL_149_READ_MASK				             0x01FF03FFU
-#define LPDDR4__DENALI_CTL_149_WRITE_MASK				            0x01FF03FFU
+#define LPDDR4__DENALI_CTL_149_READ_MASK                             0x01FF03FFU
+#define LPDDR4__DENALI_CTL_149_WRITE_MASK                            0x01FF03FFU
 #define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_MASK            0x000000FFU
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH				    8U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER_WIDTH                    8U
 #define LPDDR4__PCPCS_PD_ENTER_TIMER__REG DENALI_CTL_149
 #define LPDDR4__PCPCS_PD_ENTER_TIMER__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_ENTER_TIMER
 
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK				   0x00000300U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH				           2U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_MASK                   0x00000300U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK_WIDTH                           2U
 #define LPDDR4__PCPCS_PD_MASK__REG DENALI_CTL_149
 #define LPDDR4__PCPCS_PD_MASK__FLD LPDDR4__DENALI_CTL_149__PCPCS_PD_MASK
 
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_149__MC_RESERVED18_WIDTH                           8U
 #define LPDDR4__MC_RESERVED18__REG DENALI_CTL_149
 #define LPDDR4__MC_RESERVED18__FLD LPDDR4__DENALI_CTL_149__MC_RESERVED18
 
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK				      0x01000000U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET				              0U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_149__DFS_ENABLE_WOSET                              0U
 #define LPDDR4__DFS_ENABLE__REG DENALI_CTL_149
 #define LPDDR4__DFS_ENABLE__FLD LPDDR4__DENALI_CTL_149__DFS_ENABLE
 
-#define LPDDR4__DENALI_CTL_150_READ_MASK				             0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_150_WRITE_MASK				            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_150_READ_MASK                             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_150_WRITE_MASK                            0xFFFF03FFU
 #define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_MASK              0x000003FFU
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH				     10U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0_WIDTH                     10U
 #define LPDDR4__TDFI_INIT_START_F0__REG DENALI_CTL_150
 #define LPDDR4__TDFI_INIT_START_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_START_F0
 
 #define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH				  16U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0_WIDTH                  16U
 #define LPDDR4__TDFI_INIT_COMPLETE_F0__REG DENALI_CTL_150
 #define LPDDR4__TDFI_INIT_COMPLETE_F0__FLD LPDDR4__DENALI_CTL_150__TDFI_INIT_COMPLETE_F0
 
-#define LPDDR4__DENALI_CTL_151_READ_MASK				             0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_151_WRITE_MASK				            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_151_READ_MASK                             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_151_WRITE_MASK                            0xFFFF03FFU
 #define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_MASK              0x000003FFU
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH				     10U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1_WIDTH                     10U
 #define LPDDR4__TDFI_INIT_START_F1__REG DENALI_CTL_151
 #define LPDDR4__TDFI_INIT_START_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_START_F1
 
 #define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH				  16U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1_WIDTH                  16U
 #define LPDDR4__TDFI_INIT_COMPLETE_F1__REG DENALI_CTL_151
 #define LPDDR4__TDFI_INIT_COMPLETE_F1__FLD LPDDR4__DENALI_CTL_151__TDFI_INIT_COMPLETE_F1
 
-#define LPDDR4__DENALI_CTL_152_READ_MASK				             0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_152_WRITE_MASK				            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_152_READ_MASK                             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_152_WRITE_MASK                            0xFFFF03FFU
 #define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_MASK              0x000003FFU
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH				     10U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2_WIDTH                     10U
 #define LPDDR4__TDFI_INIT_START_F2__REG DENALI_CTL_152
 #define LPDDR4__TDFI_INIT_START_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_START_F2
 
 #define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH				  16U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2_WIDTH                  16U
 #define LPDDR4__TDFI_INIT_COMPLETE_F2__REG DENALI_CTL_152
 #define LPDDR4__TDFI_INIT_COMPLETE_F2__FLD LPDDR4__DENALI_CTL_152__TDFI_INIT_COMPLETE_F2
 
-#define LPDDR4__DENALI_CTL_153_READ_MASK				             0x00000103U
-#define LPDDR4__DENALI_CTL_153_WRITE_MASK				            0x00000103U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK				0x00000003U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH				        2U
+#define LPDDR4__DENALI_CTL_153_READ_MASK                             0x00000103U
+#define LPDDR4__DENALI_CTL_153_WRITE_MASK                            0x00000103U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_MASK                0x00000003U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY_WIDTH                        2U
 #define LPDDR4__CURRENT_REG_COPY__REG DENALI_CTL_153
 #define LPDDR4__CURRENT_REG_COPY__FLD LPDDR4__DENALI_CTL_153__CURRENT_REG_COPY
 
 #define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_MASK            0x00000100U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT				    8U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET				    0U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN_WOSET                    0U
 #define LPDDR4__DFS_PHY_REG_WRITE_EN__REG DENALI_CTL_153
 #define LPDDR4__DFS_PHY_REG_WRITE_EN__FLD LPDDR4__DENALI_CTL_153__DFS_PHY_REG_WRITE_EN
 
-#define LPDDR4__DENALI_CTL_154_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_154_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_154_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH				 32U
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR_WIDTH                 32U
 #define LPDDR4__DFS_PHY_REG_WRITE_ADDR__REG DENALI_CTL_154
 #define LPDDR4__DFS_PHY_REG_WRITE_ADDR__FLD LPDDR4__DENALI_CTL_154__DFS_PHY_REG_WRITE_ADDR
 
-#define LPDDR4__DENALI_CTL_155_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_155_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_155_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_SHIFT               0U
 #define LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0_WIDTH              32U
 #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__REG DENALI_CTL_155
 #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F0__FLD LPDDR4__DENALI_CTL_155__DFS_PHY_REG_WRITE_DATA_F0
 
-#define LPDDR4__DENALI_CTL_156_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_156_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_156_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_SHIFT               0U
 #define LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1_WIDTH              32U
 #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__REG DENALI_CTL_156
 #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F1__FLD LPDDR4__DENALI_CTL_156__DFS_PHY_REG_WRITE_DATA_F1
 
-#define LPDDR4__DENALI_CTL_157_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_157_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_157_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_SHIFT               0U
 #define LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2_WIDTH              32U
 #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__REG DENALI_CTL_157
 #define LPDDR4__DFS_PHY_REG_WRITE_DATA_F2__FLD LPDDR4__DENALI_CTL_157__DFS_PHY_REG_WRITE_DATA_F2
 
-#define LPDDR4__DENALI_CTL_158_READ_MASK				             0x00FFFF0FU
-#define LPDDR4__DENALI_CTL_158_WRITE_MASK				            0x00FFFF0FU
+#define LPDDR4__DENALI_CTL_158_READ_MASK                             0x00FFFF0FU
+#define LPDDR4__DENALI_CTL_158_WRITE_MASK                            0x00FFFF0FU
 #define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_MASK          0x0000000FU
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH				  4U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK_WIDTH                  4U
 #define LPDDR4__DFS_PHY_REG_WRITE_MASK__REG DENALI_CTL_158
 #define LPDDR4__DFS_PHY_REG_WRITE_MASK__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_MASK
 
 #define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_MASK          0x00FFFF00U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT_WIDTH                 16U
 #define LPDDR4__DFS_PHY_REG_WRITE_WAIT__REG DENALI_CTL_158
 #define LPDDR4__DFS_PHY_REG_WRITE_WAIT__FLD LPDDR4__DENALI_CTL_158__DFS_PHY_REG_WRITE_WAIT
 
-#define LPDDR4__DENALI_CTL_159_READ_MASK				             0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159_WRITE_MASK				            0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK				   0x07FFFFFFU
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH				          27U
+#define LPDDR4__DENALI_CTL_159_READ_MASK                             0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159_WRITE_MASK                            0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_MASK                   0x07FFFFFFU
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_159__WRITE_MODEREG_WIDTH                          27U
 #define LPDDR4__WRITE_MODEREG__REG DENALI_CTL_159
 #define LPDDR4__WRITE_MODEREG__FLD LPDDR4__DENALI_CTL_159__WRITE_MODEREG
 
-#define LPDDR4__DENALI_CTL_160_READ_MASK				             0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_160_WRITE_MASK				            0x01FFFFFFU
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK				      0x000000FFU
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_160_READ_MASK                             0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_160_WRITE_MASK                            0x01FFFFFFU
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_MASK                      0x000000FFU
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_160__MRW_STATUS_WIDTH                              8U
 #define LPDDR4__MRW_STATUS__REG DENALI_CTL_160
 #define LPDDR4__MRW_STATUS__FLD LPDDR4__DENALI_CTL_160__MRW_STATUS
 
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK				    0x01FFFF00U
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH				           17U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_MASK                    0x01FFFF00U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_160__READ_MODEREG_WIDTH                           17U
 #define LPDDR4__READ_MODEREG__REG DENALI_CTL_160
 #define LPDDR4__READ_MODEREG__FLD LPDDR4__DENALI_CTL_160__READ_MODEREG
 
-#define LPDDR4__DENALI_CTL_161_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_161_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_161_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH				  32U
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0_WIDTH                  32U
 #define LPDDR4__PERIPHERAL_MRR_DATA_0__REG DENALI_CTL_161
 #define LPDDR4__PERIPHERAL_MRR_DATA_0__FLD LPDDR4__DENALI_CTL_161__PERIPHERAL_MRR_DATA_0
 
-#define LPDDR4__DENALI_CTL_162_READ_MASK				             0x00FFFFFFU
-#define LPDDR4__DENALI_CTL_162_WRITE_MASK				            0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_162_READ_MASK                             0x00FFFFFFU
+#define LPDDR4__DENALI_CTL_162_WRITE_MASK                            0x00FFFFFFU
 #define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_MASK           0x000000FFU
-#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH				   8U
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1_WIDTH                   8U
 #define LPDDR4__PERIPHERAL_MRR_DATA_1__REG DENALI_CTL_162
 #define LPDDR4__PERIPHERAL_MRR_DATA_1__FLD LPDDR4__DENALI_CTL_162__PERIPHERAL_MRR_DATA_1
 
 #define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_MASK              0x00FFFF00U
-#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH				     16U
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0_WIDTH                     16U
 #define LPDDR4__AUTO_TEMPCHK_VAL_0__REG DENALI_CTL_162
 #define LPDDR4__AUTO_TEMPCHK_VAL_0__FLD LPDDR4__DENALI_CTL_162__AUTO_TEMPCHK_VAL_0
 
-#define LPDDR4__DENALI_CTL_163_READ_MASK				             0x0001FFFFU
-#define LPDDR4__DENALI_CTL_163_WRITE_MASK				            0x0001FFFFU
+#define LPDDR4__DENALI_CTL_163_READ_MASK                             0x0001FFFFU
+#define LPDDR4__DENALI_CTL_163_WRITE_MASK                            0x0001FFFFU
 #define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_MASK              0x0000FFFFU
-#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH				     16U
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1_WIDTH                     16U
 #define LPDDR4__AUTO_TEMPCHK_VAL_1__REG DENALI_CTL_163
 #define LPDDR4__AUTO_TEMPCHK_VAL_1__FLD LPDDR4__DENALI_CTL_163__AUTO_TEMPCHK_VAL_1
 
 #define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_MASK            0x00010000U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET				    0U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG_WOSET                    0U
 #define LPDDR4__DISABLE_UPDATE_TVRCG__REG DENALI_CTL_163
 #define LPDDR4__DISABLE_UPDATE_TVRCG__FLD LPDDR4__DENALI_CTL_163__DISABLE_UPDATE_TVRCG
 
-#define LPDDR4__DENALI_CTL_164_READ_MASK				             0x03FF0003U
-#define LPDDR4__DENALI_CTL_164_WRITE_MASK				            0x03FF0003U
+#define LPDDR4__DENALI_CTL_164_READ_MASK                             0x03FF0003U
+#define LPDDR4__DENALI_CTL_164_WRITE_MASK                            0x03FF0003U
 #define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_MASK              0x00000003U
-#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH				      2U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC_WIDTH                      2U
 #define LPDDR4__MRW_DFS_UPDATE_FRC__REG DENALI_CTL_164
 #define LPDDR4__MRW_DFS_UPDATE_FRC__FLD LPDDR4__DENALI_CTL_164__MRW_DFS_UPDATE_FRC
 
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK				 0x03FF0000U
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH				        10U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0_WIDTH                        10U
 #define LPDDR4__TVRCG_ENABLE_F0__REG DENALI_CTL_164
 #define LPDDR4__TVRCG_ENABLE_F0__FLD LPDDR4__DENALI_CTL_164__TVRCG_ENABLE_F0
 
-#define LPDDR4__DENALI_CTL_165_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_165_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH				       10U
+#define LPDDR4__DENALI_CTL_165_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_165_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0_WIDTH                       10U
 #define LPDDR4__TVRCG_DISABLE_F0__REG DENALI_CTL_165
 #define LPDDR4__TVRCG_DISABLE_F0__FLD LPDDR4__DENALI_CTL_165__TVRCG_DISABLE_F0
 
-#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK				          0x03FF0000U
-#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH								 10U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_MASK                          0x03FF0000U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_165__TFC_F0_WIDTH                                 10U
 #define LPDDR4__TFC_F0__REG DENALI_CTL_165
 #define LPDDR4__TFC_F0__FLD LPDDR4__DENALI_CTL_165__TFC_F0
 
-#define LPDDR4__DENALI_CTL_166_READ_MASK				             0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_166_WRITE_MASK				            0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_166_READ_MASK                             0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_166_WRITE_MASK                            0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_166__TCKFSPE_F0_WIDTH                              5U
 #define LPDDR4__TCKFSPE_F0__REG DENALI_CTL_166
 #define LPDDR4__TCKFSPE_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPE_F0
 
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_166__TCKFSPX_F0_WIDTH                              5U
 #define LPDDR4__TCKFSPX_F0__REG DENALI_CTL_166
 #define LPDDR4__TCKFSPX_F0__FLD LPDDR4__DENALI_CTL_166__TCKFSPX_F0
 
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK				   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH				          16U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_166__TVREF_LONG_F0_WIDTH                          16U
 #define LPDDR4__TVREF_LONG_F0__REG DENALI_CTL_166
 #define LPDDR4__TVREF_LONG_F0__FLD LPDDR4__DENALI_CTL_166__TVREF_LONG_F0
 
-#define LPDDR4__DENALI_CTL_167_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_167_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK				 0x000003FFU
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH				        10U
+#define LPDDR4__DENALI_CTL_167_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_167_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_MASK                 0x000003FFU
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1_WIDTH                        10U
 #define LPDDR4__TVRCG_ENABLE_F1__REG DENALI_CTL_167
 #define LPDDR4__TVRCG_ENABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_ENABLE_F1
 
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK				0x03FF0000U
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH				       10U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_MASK                0x03FF0000U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1_WIDTH                       10U
 #define LPDDR4__TVRCG_DISABLE_F1__REG DENALI_CTL_167
 #define LPDDR4__TVRCG_DISABLE_F1__FLD LPDDR4__DENALI_CTL_167__TVRCG_DISABLE_F1
 
-#define LPDDR4__DENALI_CTL_168_READ_MASK				             0x1F1F03FFU
-#define LPDDR4__DENALI_CTL_168_WRITE_MASK				            0x1F1F03FFU
-#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK				          0x000003FFU
-#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH								 10U
+#define LPDDR4__DENALI_CTL_168_READ_MASK                             0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_168_WRITE_MASK                            0x1F1F03FFU
+#define LPDDR4__DENALI_CTL_168__TFC_F1_MASK                          0x000003FFU
+#define LPDDR4__DENALI_CTL_168__TFC_F1_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_168__TFC_F1_WIDTH                                 10U
 #define LPDDR4__TFC_F1__REG DENALI_CTL_168
 #define LPDDR4__TFC_F1__FLD LPDDR4__DENALI_CTL_168__TFC_F1
 
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK				      0x001F0000U
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_168__TCKFSPE_F1_WIDTH                              5U
 #define LPDDR4__TCKFSPE_F1__REG DENALI_CTL_168
 #define LPDDR4__TCKFSPE_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPE_F1
 
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK				      0x1F000000U
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_MASK                      0x1F000000U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_168__TCKFSPX_F1_WIDTH                              5U
 #define LPDDR4__TCKFSPX_F1__REG DENALI_CTL_168
 #define LPDDR4__TCKFSPX_F1__FLD LPDDR4__DENALI_CTL_168__TCKFSPX_F1
 
-#define LPDDR4__DENALI_CTL_169_READ_MASK				             0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_169_WRITE_MASK				            0x03FFFFFFU
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK				   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH				          16U
+#define LPDDR4__DENALI_CTL_169_READ_MASK                             0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_169_WRITE_MASK                            0x03FFFFFFU
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_169__TVREF_LONG_F1_WIDTH                          16U
 #define LPDDR4__TVREF_LONG_F1__REG DENALI_CTL_169
 #define LPDDR4__TVREF_LONG_F1__FLD LPDDR4__DENALI_CTL_169__TVREF_LONG_F1
 
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK				 0x03FF0000U
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH				        10U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_MASK                 0x03FF0000U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2_WIDTH                        10U
 #define LPDDR4__TVRCG_ENABLE_F2__REG DENALI_CTL_169
 #define LPDDR4__TVRCG_ENABLE_F2__FLD LPDDR4__DENALI_CTL_169__TVRCG_ENABLE_F2
 
-#define LPDDR4__DENALI_CTL_170_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_170_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH				       10U
+#define LPDDR4__DENALI_CTL_170_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_170_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2_WIDTH                       10U
 #define LPDDR4__TVRCG_DISABLE_F2__REG DENALI_CTL_170
 #define LPDDR4__TVRCG_DISABLE_F2__FLD LPDDR4__DENALI_CTL_170__TVRCG_DISABLE_F2
 
-#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK				          0x03FF0000U
-#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH								 10U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_MASK                          0x03FF0000U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_170__TFC_F2_WIDTH                                 10U
 #define LPDDR4__TFC_F2__REG DENALI_CTL_170
 #define LPDDR4__TFC_F2__FLD LPDDR4__DENALI_CTL_170__TFC_F2
 
-#define LPDDR4__DENALI_CTL_171_READ_MASK				             0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_171_WRITE_MASK				            0xFFFF1F1FU
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK				      0x0000001FU
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_171_READ_MASK                             0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_171_WRITE_MASK                            0xFFFF1F1FU
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_MASK                      0x0000001FU
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_171__TCKFSPE_F2_WIDTH                              5U
 #define LPDDR4__TCKFSPE_F2__REG DENALI_CTL_171
 #define LPDDR4__TCKFSPE_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPE_F2
 
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK				      0x00001F00U
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_MASK                      0x00001F00U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_171__TCKFSPX_F2_WIDTH                              5U
 #define LPDDR4__TCKFSPX_F2__REG DENALI_CTL_171
 #define LPDDR4__TCKFSPX_F2__FLD LPDDR4__DENALI_CTL_171__TCKFSPX_F2
 
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK				   0xFFFF0000U
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH				          16U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_MASK                   0xFFFF0000U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_171__TVREF_LONG_F2_WIDTH                          16U
 #define LPDDR4__TVREF_LONG_F2__REG DENALI_CTL_171
 #define LPDDR4__TVREF_LONG_F2__FLD LPDDR4__DENALI_CTL_171__TVREF_LONG_F2
 
-#define LPDDR4__DENALI_CTL_172_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_172_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_172_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT				0U
+#define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_SHIFT                0U
 #define LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0_WIDTH               16U
 #define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_172
 #define LPDDR4__MRR_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F0
@@ -2986,10 +2986,10 @@
 #define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_172
 #define LPDDR4__MRR_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_172__MRR_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_173_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_173_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_173_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT				0U
+#define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_SHIFT                0U
 #define LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2_WIDTH               16U
 #define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_173
 #define LPDDR4__MRR_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_173__MRR_PROMOTE_THRESHOLD_F2
@@ -3000,10 +3000,10 @@
 #define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_173
 #define LPDDR4__MRW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_173__MRW_PROMOTE_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_174_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_174_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_174_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_MASK        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT				0U
+#define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_SHIFT                0U
 #define LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1_WIDTH               16U
 #define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_174
 #define LPDDR4__MRW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F1
@@ -3014,833 +3014,833 @@
 #define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_174
 #define LPDDR4__MRW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_174__MRW_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_175_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_175_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_175_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_175_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0_WIDTH                           8U
 #define LPDDR4__MR1_DATA_F0_0__REG DENALI_CTL_175
 #define LPDDR4__MR1_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F0_0
 
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0_WIDTH                           8U
 #define LPDDR4__MR2_DATA_F0_0__REG DENALI_CTL_175
 #define LPDDR4__MR2_DATA_F0_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F0_0
 
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0_WIDTH                           8U
 #define LPDDR4__MR1_DATA_F1_0__REG DENALI_CTL_175
 #define LPDDR4__MR1_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR1_DATA_F1_0
 
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0_WIDTH                           8U
 #define LPDDR4__MR2_DATA_F1_0__REG DENALI_CTL_175
 #define LPDDR4__MR2_DATA_F1_0__FLD LPDDR4__DENALI_CTL_175__MR2_DATA_F1_0
 
-#define LPDDR4__DENALI_CTL_176_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_176_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_176_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0_WIDTH                           8U
 #define LPDDR4__MR1_DATA_F2_0__REG DENALI_CTL_176
 #define LPDDR4__MR1_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR1_DATA_F2_0
 
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0_WIDTH                           8U
 #define LPDDR4__MR2_DATA_F2_0__REG DENALI_CTL_176
 #define LPDDR4__MR2_DATA_F2_0__FLD LPDDR4__DENALI_CTL_176__MR2_DATA_F2_0
 
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH				         8U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0_WIDTH                         8U
 #define LPDDR4__MRSINGLE_DATA_0__REG DENALI_CTL_176
 #define LPDDR4__MRSINGLE_DATA_0__FLD LPDDR4__DENALI_CTL_176__MRSINGLE_DATA_0
 
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0_WIDTH                           8U
 #define LPDDR4__MR3_DATA_F0_0__REG DENALI_CTL_176
 #define LPDDR4__MR3_DATA_F0_0__FLD LPDDR4__DENALI_CTL_176__MR3_DATA_F0_0
 
-#define LPDDR4__DENALI_CTL_177_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_177_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_177_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_177_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0_WIDTH                           8U
 #define LPDDR4__MR3_DATA_F1_0__REG DENALI_CTL_177
 #define LPDDR4__MR3_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F1_0
 
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0_WIDTH                           8U
 #define LPDDR4__MR3_DATA_F2_0__REG DENALI_CTL_177
 #define LPDDR4__MR3_DATA_F2_0__FLD LPDDR4__DENALI_CTL_177__MR3_DATA_F2_0
 
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0_WIDTH                           8U
 #define LPDDR4__MR4_DATA_F0_0__REG DENALI_CTL_177
 #define LPDDR4__MR4_DATA_F0_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F0_0
 
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0_WIDTH                           8U
 #define LPDDR4__MR4_DATA_F1_0__REG DENALI_CTL_177
 #define LPDDR4__MR4_DATA_F1_0__FLD LPDDR4__DENALI_CTL_177__MR4_DATA_F1_0
 
-#define LPDDR4__DENALI_CTL_178_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_178_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_178_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0_WIDTH                           8U
 #define LPDDR4__MR4_DATA_F2_0__REG DENALI_CTL_178
 #define LPDDR4__MR4_DATA_F2_0__FLD LPDDR4__DENALI_CTL_178__MR4_DATA_F2_0
 
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_178__MR8_DATA_0_WIDTH                              8U
 #define LPDDR4__MR8_DATA_0__REG DENALI_CTL_178
 #define LPDDR4__MR8_DATA_0__FLD LPDDR4__DENALI_CTL_178__MR8_DATA_0
 
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0_WIDTH                          8U
 #define LPDDR4__MR11_DATA_F0_0__REG DENALI_CTL_178
 #define LPDDR4__MR11_DATA_F0_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F0_0
 
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0_WIDTH                          8U
 #define LPDDR4__MR11_DATA_F1_0__REG DENALI_CTL_178
 #define LPDDR4__MR11_DATA_F1_0__FLD LPDDR4__DENALI_CTL_178__MR11_DATA_F1_0
 
-#define LPDDR4__DENALI_CTL_179_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_179_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_179_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0_WIDTH                          8U
 #define LPDDR4__MR11_DATA_F2_0__REG DENALI_CTL_179
 #define LPDDR4__MR11_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR11_DATA_F2_0
 
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0_WIDTH                          8U
 #define LPDDR4__MR12_DATA_F0_0__REG DENALI_CTL_179
 #define LPDDR4__MR12_DATA_F0_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F0_0
 
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0_WIDTH                          8U
 #define LPDDR4__MR12_DATA_F1_0__REG DENALI_CTL_179
 #define LPDDR4__MR12_DATA_F1_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F1_0
 
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0_WIDTH                          8U
 #define LPDDR4__MR12_DATA_F2_0__REG DENALI_CTL_179
 #define LPDDR4__MR12_DATA_F2_0__FLD LPDDR4__DENALI_CTL_179__MR12_DATA_F2_0
 
-#define LPDDR4__DENALI_CTL_180_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_180_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK				     0x000000FFU
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_180_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_180__MR13_DATA_0_WIDTH                             8U
 #define LPDDR4__MR13_DATA_0__REG DENALI_CTL_180
 #define LPDDR4__MR13_DATA_0__FLD LPDDR4__DENALI_CTL_180__MR13_DATA_0
 
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0_WIDTH                          8U
 #define LPDDR4__MR14_DATA_F0_0__REG DENALI_CTL_180
 #define LPDDR4__MR14_DATA_F0_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F0_0
 
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0_WIDTH                          8U
 #define LPDDR4__MR14_DATA_F1_0__REG DENALI_CTL_180
 #define LPDDR4__MR14_DATA_F1_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F1_0
 
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0_WIDTH                          8U
 #define LPDDR4__MR14_DATA_F2_0__REG DENALI_CTL_180
 #define LPDDR4__MR14_DATA_F2_0__FLD LPDDR4__DENALI_CTL_180__MR14_DATA_F2_0
 
-#define LPDDR4__DENALI_CTL_181_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_181_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK				     0x000000FFU
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_181_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_181__MR16_DATA_0_WIDTH                             8U
 #define LPDDR4__MR16_DATA_0__REG DENALI_CTL_181
 #define LPDDR4__MR16_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR16_DATA_0
 
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK				     0x0000FF00U
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_MASK                     0x0000FF00U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_181__MR17_DATA_0_WIDTH                             8U
 #define LPDDR4__MR17_DATA_0__REG DENALI_CTL_181
 #define LPDDR4__MR17_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR17_DATA_0
 
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK				     0x00FF0000U
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_181__MR20_DATA_0_WIDTH                             8U
 #define LPDDR4__MR20_DATA_0__REG DENALI_CTL_181
 #define LPDDR4__MR20_DATA_0__FLD LPDDR4__DENALI_CTL_181__MR20_DATA_0
 
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0_WIDTH                          8U
 #define LPDDR4__MR22_DATA_F0_0__REG DENALI_CTL_181
 #define LPDDR4__MR22_DATA_F0_0__FLD LPDDR4__DENALI_CTL_181__MR22_DATA_F0_0
 
-#define LPDDR4__DENALI_CTL_182_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_182_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_182_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0_WIDTH                          8U
 #define LPDDR4__MR22_DATA_F1_0__REG DENALI_CTL_182
 #define LPDDR4__MR22_DATA_F1_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F1_0
 
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0_WIDTH                          8U
 #define LPDDR4__MR22_DATA_F2_0__REG DENALI_CTL_182
 #define LPDDR4__MR22_DATA_F2_0__FLD LPDDR4__DENALI_CTL_182__MR22_DATA_F2_0
 
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1_WIDTH                           8U
 #define LPDDR4__MR1_DATA_F0_1__REG DENALI_CTL_182
 #define LPDDR4__MR1_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR1_DATA_F0_1
 
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1_WIDTH                           8U
 #define LPDDR4__MR2_DATA_F0_1__REG DENALI_CTL_182
 #define LPDDR4__MR2_DATA_F0_1__FLD LPDDR4__DENALI_CTL_182__MR2_DATA_F0_1
 
-#define LPDDR4__DENALI_CTL_183_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_183_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_183_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1_WIDTH                           8U
 #define LPDDR4__MR1_DATA_F1_1__REG DENALI_CTL_183
 #define LPDDR4__MR1_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F1_1
 
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1_WIDTH                           8U
 #define LPDDR4__MR2_DATA_F1_1__REG DENALI_CTL_183
 #define LPDDR4__MR2_DATA_F1_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F1_1
 
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1_WIDTH                           8U
 #define LPDDR4__MR1_DATA_F2_1__REG DENALI_CTL_183
 #define LPDDR4__MR1_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR1_DATA_F2_1
 
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1_WIDTH                           8U
 #define LPDDR4__MR2_DATA_F2_1__REG DENALI_CTL_183
 #define LPDDR4__MR2_DATA_F2_1__FLD LPDDR4__DENALI_CTL_183__MR2_DATA_F2_1
 
-#define LPDDR4__DENALI_CTL_184_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_184_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK				 0x000000FFU
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH				         8U
+#define LPDDR4__DENALI_CTL_184_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_184_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1_WIDTH                         8U
 #define LPDDR4__MRSINGLE_DATA_1__REG DENALI_CTL_184
 #define LPDDR4__MRSINGLE_DATA_1__FLD LPDDR4__DENALI_CTL_184__MRSINGLE_DATA_1
 
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1_WIDTH                           8U
 #define LPDDR4__MR3_DATA_F0_1__REG DENALI_CTL_184
 #define LPDDR4__MR3_DATA_F0_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F0_1
 
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1_WIDTH                           8U
 #define LPDDR4__MR3_DATA_F1_1__REG DENALI_CTL_184
 #define LPDDR4__MR3_DATA_F1_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F1_1
 
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1_WIDTH                           8U
 #define LPDDR4__MR3_DATA_F2_1__REG DENALI_CTL_184
 #define LPDDR4__MR3_DATA_F2_1__FLD LPDDR4__DENALI_CTL_184__MR3_DATA_F2_1
 
-#define LPDDR4__DENALI_CTL_185_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_185_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_185_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_185_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1_WIDTH                           8U
 #define LPDDR4__MR4_DATA_F0_1__REG DENALI_CTL_185
 #define LPDDR4__MR4_DATA_F0_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F0_1
 
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1_WIDTH                           8U
 #define LPDDR4__MR4_DATA_F1_1__REG DENALI_CTL_185
 #define LPDDR4__MR4_DATA_F1_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F1_1
 
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1_WIDTH                           8U
 #define LPDDR4__MR4_DATA_F2_1__REG DENALI_CTL_185
 #define LPDDR4__MR4_DATA_F2_1__FLD LPDDR4__DENALI_CTL_185__MR4_DATA_F2_1
 
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK				      0xFF000000U
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_MASK                      0xFF000000U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_185__MR8_DATA_1_WIDTH                              8U
 #define LPDDR4__MR8_DATA_1__REG DENALI_CTL_185
 #define LPDDR4__MR8_DATA_1__FLD LPDDR4__DENALI_CTL_185__MR8_DATA_1
 
-#define LPDDR4__DENALI_CTL_186_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_186_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_186_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_186_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1_WIDTH                          8U
 #define LPDDR4__MR11_DATA_F0_1__REG DENALI_CTL_186
 #define LPDDR4__MR11_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F0_1
 
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1_WIDTH                          8U
 #define LPDDR4__MR11_DATA_F1_1__REG DENALI_CTL_186
 #define LPDDR4__MR11_DATA_F1_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F1_1
 
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1_WIDTH                          8U
 #define LPDDR4__MR11_DATA_F2_1__REG DENALI_CTL_186
 #define LPDDR4__MR11_DATA_F2_1__FLD LPDDR4__DENALI_CTL_186__MR11_DATA_F2_1
 
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1_WIDTH                          8U
 #define LPDDR4__MR12_DATA_F0_1__REG DENALI_CTL_186
 #define LPDDR4__MR12_DATA_F0_1__FLD LPDDR4__DENALI_CTL_186__MR12_DATA_F0_1
 
-#define LPDDR4__DENALI_CTL_187_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_187_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_187_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_187_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1_WIDTH                          8U
 #define LPDDR4__MR12_DATA_F1_1__REG DENALI_CTL_187
 #define LPDDR4__MR12_DATA_F1_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F1_1
 
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1_WIDTH                          8U
 #define LPDDR4__MR12_DATA_F2_1__REG DENALI_CTL_187
 #define LPDDR4__MR12_DATA_F2_1__FLD LPDDR4__DENALI_CTL_187__MR12_DATA_F2_1
 
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK				     0x00FF0000U
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_187__MR13_DATA_1_WIDTH                             8U
 #define LPDDR4__MR13_DATA_1__REG DENALI_CTL_187
 #define LPDDR4__MR13_DATA_1__FLD LPDDR4__DENALI_CTL_187__MR13_DATA_1
 
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1_WIDTH                          8U
 #define LPDDR4__MR14_DATA_F0_1__REG DENALI_CTL_187
 #define LPDDR4__MR14_DATA_F0_1__FLD LPDDR4__DENALI_CTL_187__MR14_DATA_F0_1
 
-#define LPDDR4__DENALI_CTL_188_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_188_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK				  0x000000FFU
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_188_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_188_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_MASK                  0x000000FFU
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1_WIDTH                          8U
 #define LPDDR4__MR14_DATA_F1_1__REG DENALI_CTL_188
 #define LPDDR4__MR14_DATA_F1_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F1_1
 
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1_WIDTH                          8U
 #define LPDDR4__MR14_DATA_F2_1__REG DENALI_CTL_188
 #define LPDDR4__MR14_DATA_F2_1__FLD LPDDR4__DENALI_CTL_188__MR14_DATA_F2_1
 
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK				     0x00FF0000U
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_MASK                     0x00FF0000U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_188__MR16_DATA_1_WIDTH                             8U
 #define LPDDR4__MR16_DATA_1__REG DENALI_CTL_188
 #define LPDDR4__MR16_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR16_DATA_1
 
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK				     0xFF000000U
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_MASK                     0xFF000000U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_188__MR17_DATA_1_WIDTH                             8U
 #define LPDDR4__MR17_DATA_1__REG DENALI_CTL_188
 #define LPDDR4__MR17_DATA_1__FLD LPDDR4__DENALI_CTL_188__MR17_DATA_1
 
-#define LPDDR4__DENALI_CTL_189_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_189_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK				     0x000000FFU
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH				             8U
+#define LPDDR4__DENALI_CTL_189_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_189_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_MASK                     0x000000FFU
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_189__MR20_DATA_1_WIDTH                             8U
 #define LPDDR4__MR20_DATA_1__REG DENALI_CTL_189
 #define LPDDR4__MR20_DATA_1__FLD LPDDR4__DENALI_CTL_189__MR20_DATA_1
 
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK				  0x0000FF00U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_MASK                  0x0000FF00U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1_WIDTH                          8U
 #define LPDDR4__MR22_DATA_F0_1__REG DENALI_CTL_189
 #define LPDDR4__MR22_DATA_F0_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F0_1
 
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK				  0x00FF0000U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_MASK                  0x00FF0000U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1_WIDTH                          8U
 #define LPDDR4__MR22_DATA_F1_1__REG DENALI_CTL_189
 #define LPDDR4__MR22_DATA_F1_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F1_1
 
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK				  0xFF000000U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH				          8U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_MASK                  0xFF000000U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1_WIDTH                          8U
 #define LPDDR4__MR22_DATA_F2_1__REG DENALI_CTL_189
 #define LPDDR4__MR22_DATA_F2_1__FLD LPDDR4__DENALI_CTL_189__MR22_DATA_F2_1
 
-#define LPDDR4__DENALI_CTL_190_READ_MASK				             0x010101FFU
-#define LPDDR4__DENALI_CTL_190_WRITE_MASK				            0x010101FFU
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK				       0x000000FFU
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH				               8U
+#define LPDDR4__DENALI_CTL_190_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_CTL_190_WRITE_MASK                            0x010101FFU
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_MASK                       0x000000FFU
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_190__MR23_DATA_WIDTH                               8U
 #define LPDDR4__MR23_DATA__REG DENALI_CTL_190
 #define LPDDR4__MR23_DATA__FLD LPDDR4__DENALI_CTL_190__MR23_DATA
 
 #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_MASK            0x00000100U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT				    8U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET				    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_SHIFT                    8U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0_WOSET                    0U
 #define LPDDR4__MR_FSP_DATA_VALID_F0__REG DENALI_CTL_190
 #define LPDDR4__MR_FSP_DATA_VALID_F0__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F0
 
 #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_MASK            0x00010000U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET				    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1_WOSET                    0U
 #define LPDDR4__MR_FSP_DATA_VALID_F1__REG DENALI_CTL_190
 #define LPDDR4__MR_FSP_DATA_VALID_F1__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F1
 
 #define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_MASK            0x01000000U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT				   24U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET				    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_SHIFT                   24U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2_WOSET                    0U
 #define LPDDR4__MR_FSP_DATA_VALID_F2__REG DENALI_CTL_190
 #define LPDDR4__MR_FSP_DATA_VALID_F2__FLD LPDDR4__DENALI_CTL_190__MR_FSP_DATA_VALID_F2
 
-#define LPDDR4__DENALI_CTL_191_READ_MASK				             0x01010103U
-#define LPDDR4__DENALI_CTL_191_WRITE_MASK				            0x01010103U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK				  0x00000003U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH				          2U
+#define LPDDR4__DENALI_CTL_191_READ_MASK                             0x01010103U
+#define LPDDR4__DENALI_CTL_191_WRITE_MASK                            0x01010103U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_MASK                  0x00000003U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN_WIDTH                          2U
 #define LPDDR4__RL3_SUPPORT_EN__REG DENALI_CTL_191
 #define LPDDR4__RL3_SUPPORT_EN__FLD LPDDR4__DENALI_CTL_191__RL3_SUPPORT_EN
 
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET				           0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED19_WOSET                           0U
 #define LPDDR4__MC_RESERVED19__REG DENALI_CTL_191
 #define LPDDR4__MC_RESERVED19__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED19
 
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK				   0x00010000U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET				           0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_191__MC_RESERVED20_WOSET                           0U
 #define LPDDR4__MC_RESERVED20__REG DENALI_CTL_191
 #define LPDDR4__MC_RESERVED20__FLD LPDDR4__DENALI_CTL_191__MC_RESERVED20
 
 #define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_MASK              0x01000000U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET				      0U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW_WOSET                      0U
 #define LPDDR4__FSP_PHY_UPDATE_MRW__REG DENALI_CTL_191
 #define LPDDR4__FSP_PHY_UPDATE_MRW__FLD LPDDR4__DENALI_CTL_191__FSP_PHY_UPDATE_MRW
 
-#define LPDDR4__DENALI_CTL_192_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_192_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_192_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_192_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_MASK            0x00000001U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET				    0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP_WOSET                    0U
 #define LPDDR4__DFS_ALWAYS_WRITE_FSP__REG DENALI_CTL_192
 #define LPDDR4__DFS_ALWAYS_WRITE_FSP__FLD LPDDR4__DENALI_CTL_192__DFS_ALWAYS_WRITE_FSP
 
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK				      0x00000100U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET				              0U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_192__FSP_STATUS_WOSET                              0U
 #define LPDDR4__FSP_STATUS__REG DENALI_CTL_192
 #define LPDDR4__FSP_STATUS__FLD LPDDR4__DENALI_CTL_192__FSP_STATUS
 
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK				  0x00010000U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET				          0U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_MASK                  0x00010000U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT_WOSET                          0U
 #define LPDDR4__FSP_OP_CURRENT__REG DENALI_CTL_192
 #define LPDDR4__FSP_OP_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_OP_CURRENT
 
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET				          0U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT_WOSET                          0U
 #define LPDDR4__FSP_WR_CURRENT__REG DENALI_CTL_192
 #define LPDDR4__FSP_WR_CURRENT__FLD LPDDR4__DENALI_CTL_192__FSP_WR_CURRENT
 
-#define LPDDR4__DENALI_CTL_193_READ_MASK				             0x03030101U
-#define LPDDR4__DENALI_CTL_193_WRITE_MASK				            0x03030101U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK				  0x00000001U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET				          0U
+#define LPDDR4__DENALI_CTL_193_READ_MASK                             0x03030101U
+#define LPDDR4__DENALI_CTL_193_WRITE_MASK                            0x03030101U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_MASK                  0x00000001U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID_WOSET                          0U
 #define LPDDR4__FSP0_FRC_VALID__REG DENALI_CTL_193
 #define LPDDR4__FSP0_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC_VALID
 
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET				          0U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID_WOSET                          0U
 #define LPDDR4__FSP1_FRC_VALID__REG DENALI_CTL_193
 #define LPDDR4__FSP1_FRC_VALID__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC_VALID
 
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK				        0x00030000U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH								2U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_MASK                        0x00030000U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_193__FSP0_FRC_WIDTH                                2U
 #define LPDDR4__FSP0_FRC__REG DENALI_CTL_193
 #define LPDDR4__FSP0_FRC__FLD LPDDR4__DENALI_CTL_193__FSP0_FRC
 
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK				        0x03000000U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH								2U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_MASK                        0x03000000U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_193__FSP1_FRC_WIDTH                                2U
 #define LPDDR4__FSP1_FRC__REG DENALI_CTL_193
 #define LPDDR4__FSP1_FRC__FLD LPDDR4__DENALI_CTL_193__FSP1_FRC
 
-#define LPDDR4__DENALI_CTL_194_READ_MASK				             0x013F0300U
-#define LPDDR4__DENALI_CTL_194_WRITE_MASK				            0x013F0300U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK				         0x00000001U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH								 1U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR								 0U
-#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET								 0U
+#define LPDDR4__DENALI_CTL_194_READ_MASK                             0x013F0300U
+#define LPDDR4__DENALI_CTL_194_WRITE_MASK                            0x013F0300U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_MASK                         0x00000001U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_194__BIST_GO_WOSET                                 0U
 #define LPDDR4__BIST_GO__REG DENALI_CTL_194
 #define LPDDR4__BIST_GO__FLD LPDDR4__DENALI_CTL_194__BIST_GO
 
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK				     0x00000300U
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH				             2U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_MASK                     0x00000300U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_194__BIST_RESULT_WIDTH                             2U
 #define LPDDR4__BIST_RESULT__REG DENALI_CTL_194
 #define LPDDR4__BIST_RESULT__FLD LPDDR4__DENALI_CTL_194__BIST_RESULT
 
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK				      0x003F0000U
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH				              6U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_MASK                      0x003F0000U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_194__ADDR_SPACE_WIDTH                              6U
 #define LPDDR4__ADDR_SPACE__REG DENALI_CTL_194
 #define LPDDR4__ADDR_SPACE__FLD LPDDR4__DENALI_CTL_194__ADDR_SPACE
 
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET				         0U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK_WOSET                         0U
 #define LPDDR4__BIST_DATA_CHECK__REG DENALI_CTL_194
 #define LPDDR4__BIST_DATA_CHECK__FLD LPDDR4__DENALI_CTL_194__BIST_DATA_CHECK
 
-#define LPDDR4__DENALI_CTL_195_READ_MASK				             0x00000001U
-#define LPDDR4__DENALI_CTL_195_WRITE_MASK				            0x00000001U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK				 0x00000001U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET				         0U
+#define LPDDR4__DENALI_CTL_195_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_195_WRITE_MASK                            0x00000001U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK_WOSET                         0U
 #define LPDDR4__BIST_ADDR_CHECK__REG DENALI_CTL_195
 #define LPDDR4__BIST_ADDR_CHECK__FLD LPDDR4__DENALI_CTL_195__BIST_ADDR_CHECK
 
-#define LPDDR4__DENALI_CTL_196_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_196_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_196_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0_WIDTH                   32U
 #define LPDDR4__BIST_START_ADDRESS_0__REG DENALI_CTL_196
 #define LPDDR4__BIST_START_ADDRESS_0__FLD LPDDR4__DENALI_CTL_196__BIST_START_ADDRESS_0
 
-#define LPDDR4__DENALI_CTL_197_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_197_WRITE_MASK				            0x00000007U
+#define LPDDR4__DENALI_CTL_197_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_197_WRITE_MASK                            0x00000007U
 #define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_MASK            0x00000007U
-#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH				    3U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1_WIDTH                    3U
 #define LPDDR4__BIST_START_ADDRESS_1__REG DENALI_CTL_197
 #define LPDDR4__BIST_START_ADDRESS_1__FLD LPDDR4__DENALI_CTL_197__BIST_START_ADDRESS_1
 
-#define LPDDR4__DENALI_CTL_198_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH				       32U
+#define LPDDR4__DENALI_CTL_198_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0_WIDTH                       32U
 #define LPDDR4__BIST_DATA_MASK_0__REG DENALI_CTL_198
 #define LPDDR4__BIST_DATA_MASK_0__FLD LPDDR4__DENALI_CTL_198__BIST_DATA_MASK_0
 
-#define LPDDR4__DENALI_CTL_199_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH				       32U
+#define LPDDR4__DENALI_CTL_199_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1_WIDTH                       32U
 #define LPDDR4__BIST_DATA_MASK_1__REG DENALI_CTL_199
 #define LPDDR4__BIST_DATA_MASK_1__FLD LPDDR4__DENALI_CTL_199__BIST_DATA_MASK_1
 
-#define LPDDR4__DENALI_CTL_200_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_200_WRITE_MASK				            0x00000007U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK				  0x00000007U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH				          3U
+#define LPDDR4__DENALI_CTL_200_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_200_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_MASK                  0x00000007U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_200__BIST_TEST_MODE_WIDTH                          3U
 #define LPDDR4__BIST_TEST_MODE__REG DENALI_CTL_200
 #define LPDDR4__BIST_TEST_MODE__FLD LPDDR4__DENALI_CTL_200__BIST_TEST_MODE
 
-#define LPDDR4__DENALI_CTL_201_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_201_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_201_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH				    32U
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0_WIDTH                    32U
 #define LPDDR4__BIST_DATA_PATTERN_0__REG DENALI_CTL_201
 #define LPDDR4__BIST_DATA_PATTERN_0__FLD LPDDR4__DENALI_CTL_201__BIST_DATA_PATTERN_0
 
-#define LPDDR4__DENALI_CTL_202_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_202_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_202_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH				    32U
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1_WIDTH                    32U
 #define LPDDR4__BIST_DATA_PATTERN_1__REG DENALI_CTL_202
 #define LPDDR4__BIST_DATA_PATTERN_1__FLD LPDDR4__DENALI_CTL_202__BIST_DATA_PATTERN_1
 
-#define LPDDR4__DENALI_CTL_203_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_203_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_203_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH				    32U
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2_WIDTH                    32U
 #define LPDDR4__BIST_DATA_PATTERN_2__REG DENALI_CTL_203
 #define LPDDR4__BIST_DATA_PATTERN_2__FLD LPDDR4__DENALI_CTL_203__BIST_DATA_PATTERN_2
 
-#define LPDDR4__DENALI_CTL_204_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_204_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_204_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH				    32U
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3_WIDTH                    32U
 #define LPDDR4__BIST_DATA_PATTERN_3__REG DENALI_CTL_204
 #define LPDDR4__BIST_DATA_PATTERN_3__FLD LPDDR4__DENALI_CTL_204__BIST_DATA_PATTERN_3
 
-#define LPDDR4__DENALI_CTL_205_READ_MASK				             0x0FFF0100U
-#define LPDDR4__DENALI_CTL_205_WRITE_MASK				            0x0FFF0100U
+#define LPDDR4__DENALI_CTL_205_READ_MASK                             0x0FFF0100U
+#define LPDDR4__DENALI_CTL_205_WRITE_MASK                            0x0FFF0100U
 #define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_MASK             0x00000001U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH				     1U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR				     0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET				     0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT_WOSET                     0U
 #define LPDDR4__BIST_RET_STATE_EXIT__REG DENALI_CTL_205
 #define LPDDR4__BIST_RET_STATE_EXIT__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE_EXIT
 
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET				          0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_205__BIST_RET_STATE_WOSET                          0U
 #define LPDDR4__BIST_RET_STATE__REG DENALI_CTL_205
 #define LPDDR4__BIST_RET_STATE__FLD LPDDR4__DENALI_CTL_205__BIST_RET_STATE
 
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK				   0x0FFF0000U
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH				          12U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_MASK                   0x0FFF0000U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_205__BIST_ERR_STOP_WIDTH                          12U
 #define LPDDR4__BIST_ERR_STOP__REG DENALI_CTL_205
 #define LPDDR4__BIST_ERR_STOP__FLD LPDDR4__DENALI_CTL_205__BIST_ERR_STOP
 
-#define LPDDR4__DENALI_CTL_206_READ_MASK				             0x07030FFFU
-#define LPDDR4__DENALI_CTL_206_WRITE_MASK				            0x07030FFFU
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK				  0x00000FFFU
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH				         12U
+#define LPDDR4__DENALI_CTL_206_READ_MASK                             0x07030FFFU
+#define LPDDR4__DENALI_CTL_206_WRITE_MASK                            0x07030FFFU
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_MASK                  0x00000FFFU
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT_WIDTH                         12U
 #define LPDDR4__BIST_ERR_COUNT__REG DENALI_CTL_206
 #define LPDDR4__BIST_ERR_COUNT__FLD LPDDR4__DENALI_CTL_206__BIST_ERR_COUNT
 
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK				      0x00030000U
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH				              2U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_MASK                      0x00030000U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_206__ECC_ENABLE_WIDTH                              2U
 #define LPDDR4__ECC_ENABLE__REG DENALI_CTL_206
 #define LPDDR4__ECC_ENABLE__FLD LPDDR4__DENALI_CTL_206__ECC_ENABLE
 
 #define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_MASK          0x07000000U
-#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT				 24U
-#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH				  3U
+#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_SHIFT                 24U
+#define LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET_WIDTH                  3U
 #define LPDDR4__INLINE_ECC_BANK_OFFSET__REG DENALI_CTL_206
 #define LPDDR4__INLINE_ECC_BANK_OFFSET__FLD LPDDR4__DENALI_CTL_206__INLINE_ECC_BANK_OFFSET
 
-#define LPDDR4__DENALI_CTL_207_READ_MASK				             0x010F0101U
-#define LPDDR4__DENALI_CTL_207_WRITE_MASK				            0x010F0101U
+#define LPDDR4__DENALI_CTL_207_READ_MASK                             0x010F0101U
+#define LPDDR4__DENALI_CTL_207_WRITE_MASK                            0x010F0101U
 #define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_MASK             0x00000001U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH				     1U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR				     0U
-#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET				     0U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN_WOSET                     0U
 #define LPDDR4__ECC_READ_CACHING_EN__REG DENALI_CTL_207
 #define LPDDR4__ECC_READ_CACHING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_READ_CACHING_EN
 
 #define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_MASK          0x00000100U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH				  1U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR				  0U
-#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET				  0U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN_WOSET                  0U
 #define LPDDR4__ECC_WRITE_COMBINING_EN__REG DENALI_CTL_207
 #define LPDDR4__ECC_WRITE_COMBINING_EN__FLD LPDDR4__DENALI_CTL_207__ECC_WRITE_COMBINING_EN
 
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED21_WIDTH                           4U
 #define LPDDR4__MC_RESERVED21__REG DENALI_CTL_207
 #define LPDDR4__MC_RESERVED21__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED21
 
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET				           0U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_207__MC_RESERVED22_WOSET                           0U
 #define LPDDR4__MC_RESERVED22__REG DENALI_CTL_207
 #define LPDDR4__MC_RESERVED22__FLD LPDDR4__DENALI_CTL_207__MC_RESERVED22
 
-#define LPDDR4__DENALI_CTL_208_READ_MASK				             0x01FFFF01U
-#define LPDDR4__DENALI_CTL_208_WRITE_MASK				            0x01FFFF01U
-#define LPDDR4__DENALI_CTL_208__FWC_MASK				             0x00000001U
-#define LPDDR4__DENALI_CTL_208__FWC_SHIFT								     0U
-#define LPDDR4__DENALI_CTL_208__FWC_WIDTH								     1U
-#define LPDDR4__DENALI_CTL_208__FWC_WOCLR								     0U
-#define LPDDR4__DENALI_CTL_208__FWC_WOSET								     0U
+#define LPDDR4__DENALI_CTL_208_READ_MASK                             0x01FFFF01U
+#define LPDDR4__DENALI_CTL_208_WRITE_MASK                            0x01FFFF01U
+#define LPDDR4__DENALI_CTL_208__FWC_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_208__FWC_SHIFT                                     0U
+#define LPDDR4__DENALI_CTL_208__FWC_WIDTH                                     1U
+#define LPDDR4__DENALI_CTL_208__FWC_WOCLR                                     0U
+#define LPDDR4__DENALI_CTL_208__FWC_WOSET                                     0U
 #define LPDDR4__FWC__REG DENALI_CTL_208
 #define LPDDR4__FWC__FLD LPDDR4__DENALI_CTL_208__FWC
 
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK				  0x00FFFF00U
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH				         16U
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_MASK                  0x00FFFF00U
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS_WIDTH                         16U
 #define LPDDR4__XOR_CHECK_BITS__REG DENALI_CTL_208
 #define LPDDR4__XOR_CHECK_BITS__FLD LPDDR4__DENALI_CTL_208__XOR_CHECK_BITS
 
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK				0x01000000U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT				       24U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET				        0U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_MASK                0x01000000U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN_WOSET                        0U
 #define LPDDR4__ECC_WRITEBACK_EN__REG DENALI_CTL_208
 #define LPDDR4__ECC_WRITEBACK_EN__FLD LPDDR4__DENALI_CTL_208__ECC_WRITEBACK_EN
 
-#define LPDDR4__DENALI_CTL_209_READ_MASK				             0x00000001U
-#define LPDDR4__DENALI_CTL_209_WRITE_MASK				            0x00000001U
+#define LPDDR4__DENALI_CTL_209_READ_MASK                             0x00000001U
+#define LPDDR4__DENALI_CTL_209_WRITE_MASK                            0x00000001U
 #define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_MASK            0x00000001U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET				    0U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR_WOSET                    0U
 #define LPDDR4__ECC_DISABLE_W_UC_ERR__REG DENALI_CTL_209
 #define LPDDR4__ECC_DISABLE_W_UC_ERR__FLD LPDDR4__DENALI_CTL_209__ECC_DISABLE_W_UC_ERR
 
-#define LPDDR4__DENALI_CTL_210_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH				           32U
+#define LPDDR4__DENALI_CTL_210_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0_WIDTH                           32U
 #define LPDDR4__ECC_U_ADDR_0__REG DENALI_CTL_210
 #define LPDDR4__ECC_U_ADDR_0__FLD LPDDR4__DENALI_CTL_210__ECC_U_ADDR_0
 
-#define LPDDR4__DENALI_CTL_211_READ_MASK				             0x0000FF07U
-#define LPDDR4__DENALI_CTL_211_WRITE_MASK				            0x0000FF07U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK				    0x00000007U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH				            3U
+#define LPDDR4__DENALI_CTL_211_READ_MASK                             0x0000FF07U
+#define LPDDR4__DENALI_CTL_211_WRITE_MASK                            0x0000FF07U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1_WIDTH                            3U
 #define LPDDR4__ECC_U_ADDR_1__REG DENALI_CTL_211
 #define LPDDR4__ECC_U_ADDR_1__FLD LPDDR4__DENALI_CTL_211__ECC_U_ADDR_1
 
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_211__ECC_U_SYND_WIDTH                              8U
 #define LPDDR4__ECC_U_SYND__REG DENALI_CTL_211
 #define LPDDR4__ECC_U_SYND__FLD LPDDR4__DENALI_CTL_211__ECC_U_SYND
 
-#define LPDDR4__DENALI_CTL_212_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH				           32U
+#define LPDDR4__DENALI_CTL_212_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_212__ECC_U_DATA_0_WIDTH                           32U
 #define LPDDR4__ECC_U_DATA_0__REG DENALI_CTL_212
 #define LPDDR4__ECC_U_DATA_0__FLD LPDDR4__DENALI_CTL_212__ECC_U_DATA_0
 
-#define LPDDR4__DENALI_CTL_213_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH				           32U
+#define LPDDR4__DENALI_CTL_213_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_213__ECC_U_DATA_1_WIDTH                           32U
 #define LPDDR4__ECC_U_DATA_1__REG DENALI_CTL_213
 #define LPDDR4__ECC_U_DATA_1__FLD LPDDR4__DENALI_CTL_213__ECC_U_DATA_1
 
-#define LPDDR4__DENALI_CTL_214_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH				           32U
+#define LPDDR4__DENALI_CTL_214_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0_WIDTH                           32U
 #define LPDDR4__ECC_C_ADDR_0__REG DENALI_CTL_214
 #define LPDDR4__ECC_C_ADDR_0__FLD LPDDR4__DENALI_CTL_214__ECC_C_ADDR_0
 
-#define LPDDR4__DENALI_CTL_215_READ_MASK				             0x0000FF07U
-#define LPDDR4__DENALI_CTL_215_WRITE_MASK				            0x0000FF07U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK				    0x00000007U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH				            3U
+#define LPDDR4__DENALI_CTL_215_READ_MASK                             0x0000FF07U
+#define LPDDR4__DENALI_CTL_215_WRITE_MASK                            0x0000FF07U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_MASK                    0x00000007U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1_WIDTH                            3U
 #define LPDDR4__ECC_C_ADDR_1__REG DENALI_CTL_215
 #define LPDDR4__ECC_C_ADDR_1__FLD LPDDR4__DENALI_CTL_215__ECC_C_ADDR_1
 
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK				      0x0000FF00U
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH				              8U
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_MASK                      0x0000FF00U
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_215__ECC_C_SYND_WIDTH                              8U
 #define LPDDR4__ECC_C_SYND__REG DENALI_CTL_215
 #define LPDDR4__ECC_C_SYND__FLD LPDDR4__DENALI_CTL_215__ECC_C_SYND
 
-#define LPDDR4__DENALI_CTL_216_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH				           32U
+#define LPDDR4__DENALI_CTL_216_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_216__ECC_C_DATA_0_WIDTH                           32U
 #define LPDDR4__ECC_C_DATA_0__REG DENALI_CTL_216
 #define LPDDR4__ECC_C_DATA_0__FLD LPDDR4__DENALI_CTL_216__ECC_C_DATA_0
 
-#define LPDDR4__DENALI_CTL_217_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH				           32U
+#define LPDDR4__DENALI_CTL_217_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_217__ECC_C_DATA_1_WIDTH                           32U
 #define LPDDR4__ECC_C_DATA_1__REG DENALI_CTL_217
 #define LPDDR4__ECC_C_DATA_1__FLD LPDDR4__DENALI_CTL_217__ECC_C_DATA_1
 
-#define LPDDR4__DENALI_CTL_218_READ_MASK				             0x7FFF3F3FU
-#define LPDDR4__DENALI_CTL_218_WRITE_MASK				            0x7FFF3F3FU
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK				        0x0000003FU
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT								0U
-#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH								6U
+#define LPDDR4__DENALI_CTL_218_READ_MASK                             0x7FFF3F3FU
+#define LPDDR4__DENALI_CTL_218_WRITE_MASK                            0x7FFF3F3FU
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_MASK                        0x0000003FU
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_218__ECC_U_ID_WIDTH                                6U
 #define LPDDR4__ECC_U_ID__REG DENALI_CTL_218
 #define LPDDR4__ECC_U_ID__FLD LPDDR4__DENALI_CTL_218__ECC_U_ID
 
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK				        0x00003F00U
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT								8U
-#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH								6U
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_MASK                        0x00003F00U
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_218__ECC_C_ID_WIDTH                                6U
 #define LPDDR4__ECC_C_ID__REG DENALI_CTL_218
 #define LPDDR4__ECC_C_ID__FLD LPDDR4__DENALI_CTL_218__ECC_C_ID
 
@@ -3850,8 +3850,8 @@
 #define LPDDR4__NON_ECC_REGION_START_ADDR_0__REG DENALI_CTL_218
 #define LPDDR4__NON_ECC_REGION_START_ADDR_0__FLD LPDDR4__DENALI_CTL_218__NON_ECC_REGION_START_ADDR_0
 
-#define LPDDR4__DENALI_CTL_219_READ_MASK				             0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_219_WRITE_MASK				            0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_219_READ_MASK                             0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_219_WRITE_MASK                            0x7FFF7FFFU
 #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_MASK       0x00007FFFU
 #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_SHIFT               0U
 #define LPDDR4__DENALI_CTL_219__NON_ECC_REGION_END_ADDR_0_WIDTH              15U
@@ -3864,8 +3864,8 @@
 #define LPDDR4__NON_ECC_REGION_START_ADDR_1__REG DENALI_CTL_219
 #define LPDDR4__NON_ECC_REGION_START_ADDR_1__FLD LPDDR4__DENALI_CTL_219__NON_ECC_REGION_START_ADDR_1
 
-#define LPDDR4__DENALI_CTL_220_READ_MASK				             0x7FFF7FFFU
-#define LPDDR4__DENALI_CTL_220_WRITE_MASK				            0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_220_READ_MASK                             0x7FFF7FFFU
+#define LPDDR4__DENALI_CTL_220_WRITE_MASK                            0x7FFF7FFFU
 #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_MASK       0x00007FFFU
 #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_SHIFT               0U
 #define LPDDR4__DENALI_CTL_220__NON_ECC_REGION_END_ADDR_1_WIDTH              15U
@@ -3878,8 +3878,8 @@
 #define LPDDR4__NON_ECC_REGION_START_ADDR_2__REG DENALI_CTL_220
 #define LPDDR4__NON_ECC_REGION_START_ADDR_2__FLD LPDDR4__DENALI_CTL_220__NON_ECC_REGION_START_ADDR_2
 
-#define LPDDR4__DENALI_CTL_221_READ_MASK				             0x00077FFFU
-#define LPDDR4__DENALI_CTL_221_WRITE_MASK				            0x00077FFFU
+#define LPDDR4__DENALI_CTL_221_READ_MASK                             0x00077FFFU
+#define LPDDR4__DENALI_CTL_221_WRITE_MASK                            0x00077FFFU
 #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_MASK       0x00007FFFU
 #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_SHIFT               0U
 #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2_WIDTH              15U
@@ -3887,129 +3887,129 @@
 #define LPDDR4__NON_ECC_REGION_END_ADDR_2__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_END_ADDR_2
 
 #define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_MASK           0x00070000U
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH				   3U
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE_WIDTH                   3U
 #define LPDDR4__NON_ECC_REGION_ENABLE__REG DENALI_CTL_221
 #define LPDDR4__NON_ECC_REGION_ENABLE__FLD LPDDR4__DENALI_CTL_221__NON_ECC_REGION_ENABLE
 
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET				         0U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_221__ECC_SCRUB_START_WOSET                         0U
 #define LPDDR4__ECC_SCRUB_START__REG DENALI_CTL_221
 #define LPDDR4__ECC_SCRUB_START__FLD LPDDR4__DENALI_CTL_221__ECC_SCRUB_START
 
-#define LPDDR4__DENALI_CTL_222_READ_MASK				             0x010FFF01U
-#define LPDDR4__DENALI_CTL_222_WRITE_MASK				            0x010FFF01U
+#define LPDDR4__DENALI_CTL_222_READ_MASK                             0x010FFF01U
+#define LPDDR4__DENALI_CTL_222_WRITE_MASK                            0x010FFF01U
 #define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_MASK           0x00000001U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH				   1U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR				   0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET				   0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS_WOSET                   0U
 #define LPDDR4__ECC_SCRUB_IN_PROGRESS__REG DENALI_CTL_222
 #define LPDDR4__ECC_SCRUB_IN_PROGRESS__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_IN_PROGRESS
 
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK				   0x000FFF00U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH				          12U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_MASK                   0x000FFF00U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN_WIDTH                          12U
 #define LPDDR4__ECC_SCRUB_LEN__REG DENALI_CTL_222
 #define LPDDR4__ECC_SCRUB_LEN__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_LEN
 
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET				          0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE_WOSET                          0U
 #define LPDDR4__ECC_SCRUB_MODE__REG DENALI_CTL_222
 #define LPDDR4__ECC_SCRUB_MODE__FLD LPDDR4__DENALI_CTL_222__ECC_SCRUB_MODE
 
-#define LPDDR4__DENALI_CTL_223_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_223_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_223_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_223_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_MASK              0x0000FFFFU
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH				     16U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL_WIDTH                     16U
 #define LPDDR4__ECC_SCRUB_INTERVAL__REG DENALI_CTL_223
 #define LPDDR4__ECC_SCRUB_INTERVAL__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_INTERVAL
 
 #define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_MASK              0xFFFF0000U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH				     16U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT_WIDTH                     16U
 #define LPDDR4__ECC_SCRUB_IDLE_CNT__REG DENALI_CTL_223
 #define LPDDR4__ECC_SCRUB_IDLE_CNT__FLD LPDDR4__DENALI_CTL_223__ECC_SCRUB_IDLE_CNT
 
-#define LPDDR4__DENALI_CTL_224_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_224_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_224_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_224_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH				 32U
+#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0_WIDTH                 32U
 #define LPDDR4__ECC_SCRUB_START_ADDR_0__REG DENALI_CTL_224
 #define LPDDR4__ECC_SCRUB_START_ADDR_0__FLD LPDDR4__DENALI_CTL_224__ECC_SCRUB_START_ADDR_0
 
-#define LPDDR4__DENALI_CTL_225_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_225_WRITE_MASK				            0x00000007U
+#define LPDDR4__DENALI_CTL_225_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_225_WRITE_MASK                            0x00000007U
 #define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_MASK          0x00000007U
-#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH				  3U
+#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1_WIDTH                  3U
 #define LPDDR4__ECC_SCRUB_START_ADDR_1__REG DENALI_CTL_225
 #define LPDDR4__ECC_SCRUB_START_ADDR_1__FLD LPDDR4__DENALI_CTL_225__ECC_SCRUB_START_ADDR_1
 
-#define LPDDR4__DENALI_CTL_226_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_226_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_226_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_226_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0_WIDTH                   32U
 #define LPDDR4__ECC_SCRUB_END_ADDR_0__REG DENALI_CTL_226
 #define LPDDR4__ECC_SCRUB_END_ADDR_0__FLD LPDDR4__DENALI_CTL_226__ECC_SCRUB_END_ADDR_0
 
-#define LPDDR4__DENALI_CTL_227_READ_MASK				             0x1F1F1F07U
-#define LPDDR4__DENALI_CTL_227_WRITE_MASK				            0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_227_READ_MASK                             0x1F1F1F07U
+#define LPDDR4__DENALI_CTL_227_WRITE_MASK                            0x1F1F1F07U
 #define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_MASK            0x00000007U
-#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH				    3U
+#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1_WIDTH                    3U
 #define LPDDR4__ECC_SCRUB_END_ADDR_1__REG DENALI_CTL_227
 #define LPDDR4__ECC_SCRUB_END_ADDR_1__FLD LPDDR4__DENALI_CTL_227__ECC_SCRUB_END_ADDR_1
 
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK				 0x00001F00U
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH				         5U
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_MASK                 0x00001F00U
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK_WIDTH                         5U
 #define LPDDR4__LONG_COUNT_MASK__REG DENALI_CTL_227
 #define LPDDR4__LONG_COUNT_MASK__FLD LPDDR4__DENALI_CTL_227__LONG_COUNT_MASK
 
 #define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_MASK             0x001F0000U
-#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH				     5U
+#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD_WIDTH                     5U
 #define LPDDR4__AREF_NORM_THRESHOLD__REG DENALI_CTL_227
 #define LPDDR4__AREF_NORM_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_NORM_THRESHOLD
 
 #define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_MASK             0x1F000000U
-#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT				    24U
-#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH				     5U
+#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD_WIDTH                     5U
 #define LPDDR4__AREF_HIGH_THRESHOLD__REG DENALI_CTL_227
 #define LPDDR4__AREF_HIGH_THRESHOLD__FLD LPDDR4__DENALI_CTL_227__AREF_HIGH_THRESHOLD
 
-#define LPDDR4__DENALI_CTL_228_READ_MASK				             0x000F1F1FU
-#define LPDDR4__DENALI_CTL_228_WRITE_MASK				            0x000F1F1FU
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK				0x0000001FU
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH				        5U
+#define LPDDR4__DENALI_CTL_228_READ_MASK                             0x000F1F1FU
+#define LPDDR4__DENALI_CTL_228_WRITE_MASK                            0x000F1F1FU
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_MASK                0x0000001FU
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT_WIDTH                        5U
 #define LPDDR4__AREF_MAX_DEFICIT__REG DENALI_CTL_228
 #define LPDDR4__AREF_MAX_DEFICIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_DEFICIT
 
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK				 0x00001F00U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH				         5U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_MASK                 0x00001F00U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT_WIDTH                         5U
 #define LPDDR4__AREF_MAX_CREDIT__REG DENALI_CTL_228
 #define LPDDR4__AREF_MAX_CREDIT__FLD LPDDR4__DENALI_CTL_228__AREF_MAX_CREDIT
 
 #define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_MASK          0x000F0000U
-#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH				  4U
+#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI_WIDTH                  4U
 #define LPDDR4__AREF_CMD_MAX_PER_TREFI__REG DENALI_CTL_228
 #define LPDDR4__AREF_CMD_MAX_PER_TREFI__FLD LPDDR4__DENALI_CTL_228__AREF_CMD_MAX_PER_TREFI
 
-#define LPDDR4__DENALI_CTL_229_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_229_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_229_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_229_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_SHIFT           0U
 #define LPDDR4__DENALI_CTL_229__ZQ_CALSTART_NORM_THRESHOLD_F0_WIDTH          16U
@@ -4022,8 +4022,8 @@
 #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__REG DENALI_CTL_229
 #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_229__ZQ_CALSTART_HIGH_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_230_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_230_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_230_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_230_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_SHIFT           0U
 #define LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0_WIDTH          16U
@@ -4031,44 +4031,44 @@
 #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CALLATCH_HIGH_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__REG DENALI_CTL_230
 #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_230__ZQ_CS_NORM_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_231_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_231_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_231_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_231_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__REG DENALI_CTL_231
 #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CS_HIGH_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_MASK          0xFFFF0000U
-#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0_WIDTH                 16U
 #define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__REG DENALI_CTL_231
 #define LPDDR4__ZQ_CALSTART_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_231__ZQ_CALSTART_TIMEOUT_F0
 
-#define LPDDR4__DENALI_CTL_232_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_232_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_232_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_232_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0_WIDTH                 16U
 #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__REG DENALI_CTL_232
 #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CALLATCH_TIMEOUT_F0
 
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0_WIDTH                       16U
 #define LPDDR4__ZQ_CS_TIMEOUT_F0__REG DENALI_CTL_232
 #define LPDDR4__ZQ_CS_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_232__ZQ_CS_TIMEOUT_F0
 
-#define LPDDR4__DENALI_CTL_233_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_233_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_233_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_233_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_233
 #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_233__ZQ_PROMOTE_THRESHOLD_F0
 
@@ -4078,8 +4078,8 @@
 #define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__REG DENALI_CTL_233
 #define LPDDR4__ZQ_CALSTART_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_233__ZQ_CALSTART_NORM_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_234_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_234_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_234_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_234_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_SHIFT           0U
 #define LPDDR4__DENALI_CTL_234__ZQ_CALSTART_HIGH_THRESHOLD_F1_WIDTH          16U
@@ -4092,50 +4092,50 @@
 #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__REG DENALI_CTL_234
 #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_234__ZQ_CALLATCH_HIGH_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_235_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_235_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_235_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_235_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__REG DENALI_CTL_235
 #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_NORM_THRESHOLD_F1
 
 #define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__REG DENALI_CTL_235
 #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_235__ZQ_CS_HIGH_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_236_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_236_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_236_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_236_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1_WIDTH                 16U
 #define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__REG DENALI_CTL_236
 #define LPDDR4__ZQ_CALSTART_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALSTART_TIMEOUT_F1
 
 #define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_MASK          0xFFFF0000U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1_WIDTH                 16U
 #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__REG DENALI_CTL_236
 #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_236__ZQ_CALLATCH_TIMEOUT_F1
 
-#define LPDDR4__DENALI_CTL_237_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_237_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_237_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_237_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1_WIDTH                       16U
 #define LPDDR4__ZQ_CS_TIMEOUT_F1__REG DENALI_CTL_237
 #define LPDDR4__ZQ_CS_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_CS_TIMEOUT_F1
 
 #define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_237
 #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_237__ZQ_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_238_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_238_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_238_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_238_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_SHIFT           0U
 #define LPDDR4__DENALI_CTL_238__ZQ_CALSTART_NORM_THRESHOLD_F2_WIDTH          16U
@@ -4148,8 +4148,8 @@
 #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__REG DENALI_CTL_238
 #define LPDDR4__ZQ_CALSTART_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_238__ZQ_CALSTART_HIGH_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_239_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_239_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_239_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_239_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_SHIFT           0U
 #define LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2_WIDTH          16U
@@ -4157,55 +4157,55 @@
 #define LPDDR4__ZQ_CALLATCH_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CALLATCH_HIGH_THRESHOLD_F2
 
 #define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__REG DENALI_CTL_239
 #define LPDDR4__ZQ_CS_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_239__ZQ_CS_NORM_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_240_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_240_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_240_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_240_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__REG DENALI_CTL_240
 #define LPDDR4__ZQ_CS_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CS_HIGH_THRESHOLD_F2
 
 #define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_MASK          0xFFFF0000U
-#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT				 16U
-#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_SHIFT                 16U
+#define LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2_WIDTH                 16U
 #define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__REG DENALI_CTL_240
 #define LPDDR4__ZQ_CALSTART_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_240__ZQ_CALSTART_TIMEOUT_F2
 
-#define LPDDR4__DENALI_CTL_241_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_241_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_241_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_241_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_MASK          0x0000FFFFU
-#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH				 16U
+#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2_WIDTH                 16U
 #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__REG DENALI_CTL_241
 #define LPDDR4__ZQ_CALLATCH_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CALLATCH_TIMEOUT_F2
 
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2_WIDTH                       16U
 #define LPDDR4__ZQ_CS_TIMEOUT_F2__REG DENALI_CTL_241
 #define LPDDR4__ZQ_CS_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_241__ZQ_CS_TIMEOUT_F2
 
-#define LPDDR4__DENALI_CTL_242_READ_MASK				             0x0007FFFFU
-#define LPDDR4__DENALI_CTL_242_WRITE_MASK				            0x0007FFFFU
+#define LPDDR4__DENALI_CTL_242_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_CTL_242_WRITE_MASK                            0x0007FFFFU
 #define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_242
 #define LPDDR4__ZQ_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_242__ZQ_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK				   0x00070000U
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_242__MC_RESERVED23_WIDTH                           3U
 #define LPDDR4__MC_RESERVED23__REG DENALI_CTL_242
 #define LPDDR4__MC_RESERVED23__FLD LPDDR4__DENALI_CTL_242__MC_RESERVED23
 
-#define LPDDR4__DENALI_CTL_243_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_243_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_243_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_243_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_SHIFT          0U
 #define LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_TASK_ARB_F0_WIDTH         16U
@@ -4218,8 +4218,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__REG DENALI_CTL_243
 #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F0__FLD LPDDR4__DENALI_CTL_243__WATCHDOG_THRESHOLD_BUS_ARB_F0
 
-#define LPDDR4__DENALI_CTL_244_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_244_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_244_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_244_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_SHIFT     0U
 #define LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F0_WIDTH    16U
@@ -4232,8 +4232,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__REG DENALI_CTL_244
 #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F0__FLD LPDDR4__DENALI_CTL_244__WATCHDOG_THRESHOLD_SPLIT_F0
 
-#define LPDDR4__DENALI_CTL_245_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_245_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_245_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_245_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_SHIFT          0U
 #define LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_STRATEGY_F0_WIDTH         16U
@@ -4246,8 +4246,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__REG DENALI_CTL_245
 #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0__FLD LPDDR4__DENALI_CTL_245__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F0
 
-#define LPDDR4__DENALI_CTL_246_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_246_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_246_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_246_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_SHIFT   0U
 #define LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F0_WIDTH  16U
@@ -4260,8 +4260,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__REG DENALI_CTL_246
 #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0__FLD LPDDR4__DENALI_CTL_246__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F0
 
-#define LPDDR4__DENALI_CTL_247_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_247_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_247_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_247_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_SHIFT          0U
 #define LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_TASK_ARB_F1_WIDTH         16U
@@ -4274,8 +4274,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__REG DENALI_CTL_247
 #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F1__FLD LPDDR4__DENALI_CTL_247__WATCHDOG_THRESHOLD_BUS_ARB_F1
 
-#define LPDDR4__DENALI_CTL_248_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_248_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_248_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_248_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_SHIFT     0U
 #define LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F1_WIDTH    16U
@@ -4288,8 +4288,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__REG DENALI_CTL_248
 #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F1__FLD LPDDR4__DENALI_CTL_248__WATCHDOG_THRESHOLD_SPLIT_F1
 
-#define LPDDR4__DENALI_CTL_249_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_249_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_249_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_249_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_SHIFT          0U
 #define LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_STRATEGY_F1_WIDTH         16U
@@ -4302,8 +4302,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__REG DENALI_CTL_249
 #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1__FLD LPDDR4__DENALI_CTL_249__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F1
 
-#define LPDDR4__DENALI_CTL_250_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_250_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_250_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_250_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_SHIFT   0U
 #define LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F1_WIDTH  16U
@@ -4316,8 +4316,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__REG DENALI_CTL_250
 #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1__FLD LPDDR4__DENALI_CTL_250__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F1
 
-#define LPDDR4__DENALI_CTL_251_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_251_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_251_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_251_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_SHIFT          0U
 #define LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_TASK_ARB_F2_WIDTH         16U
@@ -4330,8 +4330,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__REG DENALI_CTL_251
 #define LPDDR4__WATCHDOG_THRESHOLD_BUS_ARB_F2__FLD LPDDR4__DENALI_CTL_251__WATCHDOG_THRESHOLD_BUS_ARB_F2
 
-#define LPDDR4__DENALI_CTL_252_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_252_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_252_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_252_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_SHIFT     0U
 #define LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_PORT0_CMD_ARB_F2_WIDTH    16U
@@ -4344,8 +4344,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__REG DENALI_CTL_252
 #define LPDDR4__WATCHDOG_THRESHOLD_SPLIT_F2__FLD LPDDR4__DENALI_CTL_252__WATCHDOG_THRESHOLD_SPLIT_F2
 
-#define LPDDR4__DENALI_CTL_253_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_253_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_253_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_253_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_SHIFT          0U
 #define LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_STRATEGY_F2_WIDTH         16U
@@ -4358,8 +4358,8 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__REG DENALI_CTL_253
 #define LPDDR4__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2__FLD LPDDR4__DENALI_CTL_253__WATCHDOG_THRESHOLD_PORT_TO_STRATEGY_F2
 
-#define LPDDR4__DENALI_CTL_254_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_254_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_254_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_SHIFT   0U
 #define LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_READ_DATA_FIFO0_F2_WIDTH  16U
@@ -4372,131 +4372,131 @@
 #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__REG DENALI_CTL_254
 #define LPDDR4__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2__FLD LPDDR4__DENALI_CTL_254__WATCHDOG_THRESHOLD_WRITE_DATA_FIFO_F2
 
-#define LPDDR4__DENALI_CTL_255_READ_MASK				             0x0000FF00U
-#define LPDDR4__DENALI_CTL_255_WRITE_MASK				            0x0000FF00U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK				 0x000000FFU
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH				         8U
+#define LPDDR4__DENALI_CTL_255_READ_MASK                             0x0000FF00U
+#define LPDDR4__DENALI_CTL_255_WRITE_MASK                            0x0000FF00U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD_WIDTH                         8U
 #define LPDDR4__WATCHDOG_RELOAD__REG DENALI_CTL_255
 #define LPDDR4__WATCHDOG_RELOAD__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_RELOAD
 
 #define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_MASK        0x0000FF00U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT				8U
-#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH				8U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_SHIFT                8U
+#define LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE_WIDTH                8U
 #define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__REG DENALI_CTL_255
 #define LPDDR4__WATCHDOG_DIAGNOSTIC_MODE__FLD LPDDR4__DENALI_CTL_255__WATCHDOG_DIAGNOSTIC_MODE
 
-#define LPDDR4__DENALI_CTL_256_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_256_WRITE_MASK				            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_256_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_256_WRITE_MASK                            0x000FFFFFU
 #define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_MASK               0x000FFFFFU
-#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH				      20U
+#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG_WIDTH                      20U
 #define LPDDR4__TIMEOUT_TIMER_LOG__REG DENALI_CTL_256
 #define LPDDR4__TIMEOUT_TIMER_LOG__FLD LPDDR4__DENALI_CTL_256__TIMEOUT_TIMER_LOG
 
-#define LPDDR4__DENALI_CTL_257_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_257_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK				       0x00000FFFU
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH				              12U
+#define LPDDR4__DENALI_CTL_257_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_257_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_257__ZQINIT_F0_WIDTH                              12U
 #define LPDDR4__ZQINIT_F0__REG DENALI_CTL_257
 #define LPDDR4__ZQINIT_F0__FLD LPDDR4__DENALI_CTL_257__ZQINIT_F0
 
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK				         0x0FFF0000U
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT								16U
-#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH								12U
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_257__ZQCL_F0_WIDTH                                12U
 #define LPDDR4__ZQCL_F0__REG DENALI_CTL_257
 #define LPDDR4__ZQCL_F0__FLD LPDDR4__DENALI_CTL_257__ZQCL_F0
 
-#define LPDDR4__DENALI_CTL_258_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_258_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK				         0x00000FFFU
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH								12U
+#define LPDDR4__DENALI_CTL_258_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_258_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_258__ZQCS_F0_WIDTH                                12U
 #define LPDDR4__ZQCS_F0__REG DENALI_CTL_258
 #define LPDDR4__ZQCS_F0__FLD LPDDR4__DENALI_CTL_258__ZQCS_F0
 
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK				       0x0FFF0000U
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH				              12U
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_MASK                       0x0FFF0000U
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_258__TZQCAL_F0_WIDTH                              12U
 #define LPDDR4__TZQCAL_F0__REG DENALI_CTL_258
 #define LPDDR4__TZQCAL_F0__FLD LPDDR4__DENALI_CTL_258__TZQCAL_F0
 
-#define LPDDR4__DENALI_CTL_259_READ_MASK				             0x000FFF7FU
-#define LPDDR4__DENALI_CTL_259_WRITE_MASK				            0x000FFF7FU
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK				       0x0000007FU
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH				               7U
+#define LPDDR4__DENALI_CTL_259_READ_MASK                             0x000FFF7FU
+#define LPDDR4__DENALI_CTL_259_WRITE_MASK                            0x000FFF7FU
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_MASK                       0x0000007FU
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_259__TZQLAT_F0_WIDTH                               7U
 #define LPDDR4__TZQLAT_F0__REG DENALI_CTL_259
 #define LPDDR4__TZQLAT_F0__FLD LPDDR4__DENALI_CTL_259__TZQLAT_F0
 
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK				       0x000FFF00U
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH				              12U
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_MASK                       0x000FFF00U
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_259__ZQINIT_F1_WIDTH                              12U
 #define LPDDR4__ZQINIT_F1__REG DENALI_CTL_259
 #define LPDDR4__ZQINIT_F1__FLD LPDDR4__DENALI_CTL_259__ZQINIT_F1
 
-#define LPDDR4__DENALI_CTL_260_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_260_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK				         0x00000FFFU
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH								12U
+#define LPDDR4__DENALI_CTL_260_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_260_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_260__ZQCL_F1_WIDTH                                12U
 #define LPDDR4__ZQCL_F1__REG DENALI_CTL_260
 #define LPDDR4__ZQCL_F1__FLD LPDDR4__DENALI_CTL_260__ZQCL_F1
 
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK				         0x0FFF0000U
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT								16U
-#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH								12U
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_260__ZQCS_F1_WIDTH                                12U
 #define LPDDR4__ZQCS_F1__REG DENALI_CTL_260
 #define LPDDR4__ZQCS_F1__FLD LPDDR4__DENALI_CTL_260__ZQCS_F1
 
-#define LPDDR4__DENALI_CTL_261_READ_MASK				             0x007F0FFFU
-#define LPDDR4__DENALI_CTL_261_WRITE_MASK				            0x007F0FFFU
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK				       0x00000FFFU
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH				              12U
+#define LPDDR4__DENALI_CTL_261_READ_MASK                             0x007F0FFFU
+#define LPDDR4__DENALI_CTL_261_WRITE_MASK                            0x007F0FFFU
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_261__TZQCAL_F1_WIDTH                              12U
 #define LPDDR4__TZQCAL_F1__REG DENALI_CTL_261
 #define LPDDR4__TZQCAL_F1__FLD LPDDR4__DENALI_CTL_261__TZQCAL_F1
 
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK				       0x007F0000U
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH				               7U
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_MASK                       0x007F0000U
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_261__TZQLAT_F1_WIDTH                               7U
 #define LPDDR4__TZQLAT_F1__REG DENALI_CTL_261
 #define LPDDR4__TZQLAT_F1__FLD LPDDR4__DENALI_CTL_261__TZQLAT_F1
 
-#define LPDDR4__DENALI_CTL_262_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_262_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK				       0x00000FFFU
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH				              12U
+#define LPDDR4__DENALI_CTL_262_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_262_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_262__ZQINIT_F2_WIDTH                              12U
 #define LPDDR4__ZQINIT_F2__REG DENALI_CTL_262
 #define LPDDR4__ZQINIT_F2__FLD LPDDR4__DENALI_CTL_262__ZQINIT_F2
 
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK				         0x0FFF0000U
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT								16U
-#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH								12U
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_MASK                         0x0FFF0000U
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_SHIFT                                16U
+#define LPDDR4__DENALI_CTL_262__ZQCL_F2_WIDTH                                12U
 #define LPDDR4__ZQCL_F2__REG DENALI_CTL_262
 #define LPDDR4__ZQCL_F2__FLD LPDDR4__DENALI_CTL_262__ZQCL_F2
 
-#define LPDDR4__DENALI_CTL_263_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_263_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK				         0x00000FFFU
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT								 0U
-#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH								12U
+#define LPDDR4__DENALI_CTL_263_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_263_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_MASK                         0x00000FFFU
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_SHIFT                                 0U
+#define LPDDR4__DENALI_CTL_263__ZQCS_F2_WIDTH                                12U
 #define LPDDR4__ZQCS_F2__REG DENALI_CTL_263
 #define LPDDR4__ZQCS_F2__FLD LPDDR4__DENALI_CTL_263__ZQCS_F2
 
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK				       0x0FFF0000U
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH				              12U
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_MASK                       0x0FFF0000U
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_263__TZQCAL_F2_WIDTH                              12U
 #define LPDDR4__TZQCAL_F2__REG DENALI_CTL_263
 #define LPDDR4__TZQCAL_F2__FLD LPDDR4__DENALI_CTL_263__TZQCAL_F2
 
-#define LPDDR4__DENALI_CTL_264_READ_MASK				             0x0100037FU
-#define LPDDR4__DENALI_CTL_264_WRITE_MASK				            0x0100037FU
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK				       0x0000007FU
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH				               7U
+#define LPDDR4__DENALI_CTL_264_READ_MASK                             0x0100037FU
+#define LPDDR4__DENALI_CTL_264_WRITE_MASK                            0x0100037FU
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_MASK                       0x0000007FU
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_264__TZQLAT_F2_WIDTH                               7U
 #define LPDDR4__TZQLAT_F2__REG DENALI_CTL_264
 #define LPDDR4__TZQLAT_F2__FLD LPDDR4__DENALI_CTL_264__TZQLAT_F2
 
@@ -4506,303 +4506,303 @@
 #define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__REG DENALI_CTL_264
 #define LPDDR4__ZQ_SW_REQ_START_LATCH_MAP__FLD LPDDR4__DENALI_CTL_264__ZQ_SW_REQ_START_LATCH_MAP
 
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK				          0x000F0000U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH								  4U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_MASK                          0x000F0000U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_WIDTH                                  4U
 #define LPDDR4__ZQ_REQ__REG DENALI_CTL_264
 #define LPDDR4__ZQ_REQ__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ
 
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET				          0U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING_WOSET                          0U
 #define LPDDR4__ZQ_REQ_PENDING__REG DENALI_CTL_264
 #define LPDDR4__ZQ_REQ_PENDING__FLD LPDDR4__DENALI_CTL_264__ZQ_REQ_PENDING
 
-#define LPDDR4__DENALI_CTL_265_READ_MASK				             0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_265_WRITE_MASK				            0x0FFF0FFFU
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK				      0x00000FFFU
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH				             12U
+#define LPDDR4__DENALI_CTL_265_READ_MASK                             0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_265_WRITE_MASK                            0x0FFF0FFFU
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_MASK                      0x00000FFFU
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F0_WIDTH                             12U
 #define LPDDR4__ZQRESET_F0__REG DENALI_CTL_265
 #define LPDDR4__ZQRESET_F0__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F0
 
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK				      0x0FFF0000U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH				             12U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_MASK                      0x0FFF0000U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_265__ZQRESET_F1_WIDTH                             12U
 #define LPDDR4__ZQRESET_F1__REG DENALI_CTL_265
 #define LPDDR4__ZQRESET_F1__FLD LPDDR4__DENALI_CTL_265__ZQRESET_F1
 
-#define LPDDR4__DENALI_CTL_266_READ_MASK				             0x01010FFFU
-#define LPDDR4__DENALI_CTL_266_WRITE_MASK				            0x01010FFFU
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK				      0x00000FFFU
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH				             12U
+#define LPDDR4__DENALI_CTL_266_READ_MASK                             0x01010FFFU
+#define LPDDR4__DENALI_CTL_266_WRITE_MASK                            0x01010FFFU
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_MASK                      0x00000FFFU
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_266__ZQRESET_F2_WIDTH                             12U
 #define LPDDR4__ZQRESET_F2__REG DENALI_CTL_266
 #define LPDDR4__ZQRESET_F2__FLD LPDDR4__DENALI_CTL_266__ZQRESET_F2
 
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK				      0x00010000U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET				              0U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_266__NO_ZQ_INIT_WOSET                              0U
 #define LPDDR4__NO_ZQ_INIT__REG DENALI_CTL_266
 #define LPDDR4__NO_ZQ_INIT__FLD LPDDR4__DENALI_CTL_266__NO_ZQ_INIT
 
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET				             0U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_266__ZQCS_ROTATE_WOSET                             0U
 #define LPDDR4__ZQCS_ROTATE__REG DENALI_CTL_266
 #define LPDDR4__ZQCS_ROTATE__FLD LPDDR4__DENALI_CTL_266__ZQCS_ROTATE
 
-#define LPDDR4__DENALI_CTL_267_READ_MASK				             0x03030303U
-#define LPDDR4__DENALI_CTL_267_WRITE_MASK				            0x03030303U
+#define LPDDR4__DENALI_CTL_267_READ_MASK                             0x03030303U
+#define LPDDR4__DENALI_CTL_267_WRITE_MASK                            0x03030303U
 #define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_MASK              0x00000003U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH				      2U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0_WIDTH                      2U
 #define LPDDR4__ZQ_CAL_START_MAP_0__REG DENALI_CTL_267
 #define LPDDR4__ZQ_CAL_START_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_0
 
 #define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_MASK              0x00000300U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH				      2U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0_WIDTH                      2U
 #define LPDDR4__ZQ_CAL_LATCH_MAP_0__REG DENALI_CTL_267
 #define LPDDR4__ZQ_CAL_LATCH_MAP_0__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_0
 
 #define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_MASK              0x00030000U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH				      2U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1_WIDTH                      2U
 #define LPDDR4__ZQ_CAL_START_MAP_1__REG DENALI_CTL_267
 #define LPDDR4__ZQ_CAL_START_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_START_MAP_1
 
 #define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_MASK              0x03000000U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH				      2U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1_WIDTH                      2U
 #define LPDDR4__ZQ_CAL_LATCH_MAP_1__REG DENALI_CTL_267
 #define LPDDR4__ZQ_CAL_LATCH_MAP_1__FLD LPDDR4__DENALI_CTL_267__ZQ_CAL_LATCH_MAP_1
 
-#define LPDDR4__DENALI_CTL_268_READ_MASK				             0x07070303U
-#define LPDDR4__DENALI_CTL_268_WRITE_MASK				            0x07070303U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK				     0x00000003U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH				             2U
+#define LPDDR4__DENALI_CTL_268_READ_MASK                             0x07070303U
+#define LPDDR4__DENALI_CTL_268_WRITE_MASK                            0x07070303U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_MASK                     0x00000003U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_0_WIDTH                             2U
 #define LPDDR4__BANK_DIFF_0__REG DENALI_CTL_268
 #define LPDDR4__BANK_DIFF_0__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_0
 
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK				     0x00000300U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH				             2U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_MASK                     0x00000300U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_268__BANK_DIFF_1_WIDTH                             2U
 #define LPDDR4__BANK_DIFF_1__REG DENALI_CTL_268
 #define LPDDR4__BANK_DIFF_1__FLD LPDDR4__DENALI_CTL_268__BANK_DIFF_1
 
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK				      0x00070000U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH				              3U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_MASK                      0x00070000U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_0_WIDTH                              3U
 #define LPDDR4__ROW_DIFF_0__REG DENALI_CTL_268
 #define LPDDR4__ROW_DIFF_0__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_0
 
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK				      0x07000000U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH				              3U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_MASK                      0x07000000U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_268__ROW_DIFF_1_WIDTH                              3U
 #define LPDDR4__ROW_DIFF_1__REG DENALI_CTL_268
 #define LPDDR4__ROW_DIFF_1__FLD LPDDR4__DENALI_CTL_268__ROW_DIFF_1
 
-#define LPDDR4__DENALI_CTL_269_READ_MASK				             0xFFFF0F0FU
-#define LPDDR4__DENALI_CTL_269_WRITE_MASK				            0xFFFF0F0FU
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK				      0x0000000FU
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH				              4U
+#define LPDDR4__DENALI_CTL_269_READ_MASK                             0xFFFF0F0FU
+#define LPDDR4__DENALI_CTL_269_WRITE_MASK                            0xFFFF0F0FU
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_MASK                      0x0000000FU
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_0_WIDTH                              4U
 #define LPDDR4__COL_DIFF_0__REG DENALI_CTL_269
 #define LPDDR4__COL_DIFF_0__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_0
 
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK				      0x00000F00U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH				              4U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_MASK                      0x00000F00U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_269__COL_DIFF_1_WIDTH                              4U
 #define LPDDR4__COL_DIFF_1__REG DENALI_CTL_269
 #define LPDDR4__COL_DIFF_1__FLD LPDDR4__DENALI_CTL_269__COL_DIFF_1
 
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK				  0xFFFF0000U
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH				         16U
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0_WIDTH                         16U
 #define LPDDR4__CS_VAL_LOWER_0__REG DENALI_CTL_269
 #define LPDDR4__CS_VAL_LOWER_0__FLD LPDDR4__DENALI_CTL_269__CS_VAL_LOWER_0
 
-#define LPDDR4__DENALI_CTL_270_READ_MASK				             0x0007FFFFU
-#define LPDDR4__DENALI_CTL_270_WRITE_MASK				            0x0007FFFFU
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK				  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH				         16U
+#define LPDDR4__DENALI_CTL_270_READ_MASK                             0x0007FFFFU
+#define LPDDR4__DENALI_CTL_270_WRITE_MASK                            0x0007FFFFU
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0_WIDTH                         16U
 #define LPDDR4__CS_VAL_UPPER_0__REG DENALI_CTL_270
 #define LPDDR4__CS_VAL_UPPER_0__FLD LPDDR4__DENALI_CTL_270__CS_VAL_UPPER_0
 
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK				 0x00070000U
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH				         3U
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_MASK                 0x00070000U
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_270__ROW_START_VAL_0_WIDTH                         3U
 #define LPDDR4__ROW_START_VAL_0__REG DENALI_CTL_270
 #define LPDDR4__ROW_START_VAL_0__FLD LPDDR4__DENALI_CTL_270__ROW_START_VAL_0
 
-#define LPDDR4__DENALI_CTL_271_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_271_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK				  0x0000FFFFU
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH				         16U
+#define LPDDR4__DENALI_CTL_271_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_271_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_MASK                  0x0000FFFFU
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1_WIDTH                         16U
 #define LPDDR4__CS_VAL_LOWER_1__REG DENALI_CTL_271
 #define LPDDR4__CS_VAL_LOWER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_LOWER_1
 
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK				  0xFFFF0000U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH				         16U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_MASK                  0xFFFF0000U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1_WIDTH                         16U
 #define LPDDR4__CS_VAL_UPPER_1__REG DENALI_CTL_271
 #define LPDDR4__CS_VAL_UPPER_1__FLD LPDDR4__DENALI_CTL_271__CS_VAL_UPPER_1
 
-#define LPDDR4__DENALI_CTL_272_READ_MASK				             0xFFFF0307U
-#define LPDDR4__DENALI_CTL_272_WRITE_MASK				            0xFFFF0307U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK				 0x00000007U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH				         3U
+#define LPDDR4__DENALI_CTL_272_READ_MASK                             0xFFFF0307U
+#define LPDDR4__DENALI_CTL_272_WRITE_MASK                            0xFFFF0307U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_272__ROW_START_VAL_1_WIDTH                         3U
 #define LPDDR4__ROW_START_VAL_1__REG DENALI_CTL_272
 #define LPDDR4__ROW_START_VAL_1__FLD LPDDR4__DENALI_CTL_272__ROW_START_VAL_1
 
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK				 0x00000300U
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH				         2U
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_MASK                 0x00000300U
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2_WIDTH                         2U
 #define LPDDR4__CS_MAP_NON_POW2__REG DENALI_CTL_272
 #define LPDDR4__CS_MAP_NON_POW2__FLD LPDDR4__DENALI_CTL_272__CS_MAP_NON_POW2
 
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK				        0xFFFF0000U
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT				               16U
-#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH				               16U
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_MASK                        0xFFFF0000U
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_SHIFT                               16U
+#define LPDDR4__DENALI_CTL_272__CS_MSK_0_WIDTH                               16U
 #define LPDDR4__CS_MSK_0__REG DENALI_CTL_272
 #define LPDDR4__CS_MSK_0__FLD LPDDR4__DENALI_CTL_272__CS_MSK_0
 
-#define LPDDR4__DENALI_CTL_273_READ_MASK				             0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_273_WRITE_MASK				            0x1F01FFFFU
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK				        0x0000FFFFU
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT								0U
-#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH				               16U
+#define LPDDR4__DENALI_CTL_273_READ_MASK                             0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_273_WRITE_MASK                            0x1F01FFFFU
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_MASK                        0x0000FFFFU
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_273__CS_MSK_1_WIDTH                               16U
 #define LPDDR4__CS_MSK_1__REG DENALI_CTL_273
 #define LPDDR4__CS_MSK_1__FLD LPDDR4__DENALI_CTL_273__CS_MSK_1
 
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET				        0U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN_WOSET                        0U
 #define LPDDR4__CS_LOWER_ADDR_EN__REG DENALI_CTL_273
 #define LPDDR4__CS_LOWER_ADDR_EN__FLD LPDDR4__DENALI_CTL_273__CS_LOWER_ADDR_EN
 
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK				   0x1F000000U
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH				           5U
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_273__MC_RESERVED24_WIDTH                           5U
 #define LPDDR4__MC_RESERVED24__REG DENALI_CTL_273
 #define LPDDR4__MC_RESERVED24__FLD LPDDR4__DENALI_CTL_273__MC_RESERVED24
 
-#define LPDDR4__DENALI_CTL_274_READ_MASK				             0xFFFF1F01U
-#define LPDDR4__DENALI_CTL_274_WRITE_MASK				            0xFFFF1F01U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK				   0x00000001U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET				           0U
+#define LPDDR4__DENALI_CTL_274_READ_MASK                             0xFFFF1F01U
+#define LPDDR4__DENALI_CTL_274_WRITE_MASK                            0xFFFF1F01U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_274__MC_RESERVED25_WOSET                           0U
 #define LPDDR4__MC_RESERVED25__REG DENALI_CTL_274
 #define LPDDR4__MC_RESERVED25__FLD LPDDR4__DENALI_CTL_274__MC_RESERVED25
 
-#define LPDDR4__DENALI_CTL_274__APREBIT_MASK				         0x00001F00U
-#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT								 8U
-#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH								 5U
+#define LPDDR4__DENALI_CTL_274__APREBIT_MASK                         0x00001F00U
+#define LPDDR4__DENALI_CTL_274__APREBIT_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_274__APREBIT_WIDTH                                 5U
 #define LPDDR4__APREBIT__REG DENALI_CTL_274
 #define LPDDR4__APREBIT__FLD LPDDR4__DENALI_CTL_274__APREBIT
 
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK				       0x00FF0000U
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH				               8U
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_MASK                       0x00FF0000U
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_274__AGE_COUNT_WIDTH                               8U
 #define LPDDR4__AGE_COUNT__REG DENALI_CTL_274
 #define LPDDR4__AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__AGE_COUNT
 
 #define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_MASK               0xFF000000U
-#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH				       8U
+#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT_WIDTH                       8U
 #define LPDDR4__COMMAND_AGE_COUNT__REG DENALI_CTL_274
 #define LPDDR4__COMMAND_AGE_COUNT__FLD LPDDR4__DENALI_CTL_274__COMMAND_AGE_COUNT
 
-#define LPDDR4__DENALI_CTL_275_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_275_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK				     0x00000001U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET				             0U
+#define LPDDR4__DENALI_CTL_275_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_275_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_275__ADDR_CMP_EN_WOSET                             0U
 #define LPDDR4__ADDR_CMP_EN__REG DENALI_CTL_275
 #define LPDDR4__ADDR_CMP_EN__FLD LPDDR4__DENALI_CTL_275__ADDR_CMP_EN
 
 #define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_MASK          0x00000100U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH				  1U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR				  0U
-#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET				  0U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS_WOSET                  0U
 #define LPDDR4__ADDR_COLLISION_MPM_DIS__REG DENALI_CTL_275
 #define LPDDR4__ADDR_COLLISION_MPM_DIS__FLD LPDDR4__DENALI_CTL_275__ADDR_COLLISION_MPM_DIS
 
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK				   0x00010000U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET				           0U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN_WOSET                           0U
 #define LPDDR4__BANK_SPLIT_EN__REG DENALI_CTL_275
 #define LPDDR4__BANK_SPLIT_EN__FLD LPDDR4__DENALI_CTL_275__BANK_SPLIT_EN
 
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK				    0x01000000U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET				            0U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_MASK                    0x01000000U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_275__PLACEMENT_EN_WOSET                            0U
 #define LPDDR4__PLACEMENT_EN__REG DENALI_CTL_275
 #define LPDDR4__PLACEMENT_EN__FLD LPDDR4__DENALI_CTL_275__PLACEMENT_EN
 
-#define LPDDR4__DENALI_CTL_276_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_276_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK				     0x00000001U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET				             0U
+#define LPDDR4__DENALI_CTL_276_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_276_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_MASK                     0x00000001U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_276__PRIORITY_EN_WOSET                             0U
 #define LPDDR4__PRIORITY_EN__REG DENALI_CTL_276
 #define LPDDR4__PRIORITY_EN__FLD LPDDR4__DENALI_CTL_276__PRIORITY_EN
 
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK				      0x00000100U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT				              8U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET				              0U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_MASK                      0x00000100U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_SHIFT                              8U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_EN_WOSET                              0U
 #define LPDDR4__RW_SAME_EN__REG DENALI_CTL_276
 #define LPDDR4__RW_SAME_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_EN
 
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK				 0x00010000U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET				         0U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_MASK                 0x00010000U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN_WOSET                         0U
 #define LPDDR4__RW_SAME_PAGE_EN__REG DENALI_CTL_276
 #define LPDDR4__RW_SAME_PAGE_EN__FLD LPDDR4__DENALI_CTL_276__RW_SAME_PAGE_EN
 
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK				      0x01000000U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT				             24U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET				              0U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_MASK                      0x01000000U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_SHIFT                             24U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_276__CS_SAME_EN_WOSET                              0U
 #define LPDDR4__CS_SAME_EN__REG DENALI_CTL_276
 #define LPDDR4__CS_SAME_EN__FLD LPDDR4__DENALI_CTL_276__CS_SAME_EN
 
-#define LPDDR4__DENALI_CTL_277_READ_MASK				             0x011F0301U
-#define LPDDR4__DENALI_CTL_277_WRITE_MASK				            0x011F0301U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK				    0x00000001U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET				            0U
+#define LPDDR4__DENALI_CTL_277_READ_MASK                             0x011F0301U
+#define LPDDR4__DENALI_CTL_277_WRITE_MASK                            0x011F0301U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN_WOSET                            0U
 #define LPDDR4__W2R_SPLIT_EN__REG DENALI_CTL_277
 #define LPDDR4__W2R_SPLIT_EN__FLD LPDDR4__DENALI_CTL_277__W2R_SPLIT_EN
 
@@ -4818,62 +4818,62 @@
 #define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__REG DENALI_CTL_277
 #define LPDDR4__NUM_Q_ENTRIES_ACT_DISABLE__FLD LPDDR4__DENALI_CTL_277__NUM_Q_ENTRIES_ACT_DISABLE
 
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK				         0x01000000U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT								24U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH								 1U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR								 0U
-#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET								 0U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_MASK                         0x01000000U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_SHIFT                                24U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WIDTH                                 1U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOCLR                                 0U
+#define LPDDR4__DENALI_CTL_277__SWAP_EN_WOSET                                 0U
 #define LPDDR4__SWAP_EN__REG DENALI_CTL_277
 #define LPDDR4__SWAP_EN__FLD LPDDR4__DENALI_CTL_277__SWAP_EN
 
-#define LPDDR4__DENALI_CTL_278_READ_MASK				             0x01030301U
-#define LPDDR4__DENALI_CTL_278_WRITE_MASK				            0x01030301U
+#define LPDDR4__DENALI_CTL_278_READ_MASK                             0x01030301U
+#define LPDDR4__DENALI_CTL_278_WRITE_MASK                            0x01030301U
 #define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_MASK           0x00000001U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH				   1U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR				   0U
-#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET				   0U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WIDTH                   1U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOCLR                   0U
+#define LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE_WOSET                   0U
 #define LPDDR4__DISABLE_RD_INTERLEAVE__REG DENALI_CTL_278
 #define LPDDR4__DISABLE_RD_INTERLEAVE__FLD LPDDR4__DENALI_CTL_278__DISABLE_RD_INTERLEAVE
 
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK				0x00000300U
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH				        2U
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD_WIDTH                        2U
 #define LPDDR4__INHIBIT_DRAM_CMD__REG DENALI_CTL_278
 #define LPDDR4__INHIBIT_DRAM_CMD__FLD LPDDR4__DENALI_CTL_278__INHIBIT_DRAM_CMD
 
-#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK				          0x00030000U
-#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH								  2U
+#define LPDDR4__DENALI_CTL_278__CS_MAP_MASK                          0x00030000U
+#define LPDDR4__DENALI_CTL_278__CS_MAP_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_278__CS_MAP_WIDTH                                  2U
 #define LPDDR4__CS_MAP__REG DENALI_CTL_278
 #define LPDDR4__CS_MAP__FLD LPDDR4__DENALI_CTL_278__CS_MAP
 
-#define LPDDR4__DENALI_CTL_278__REDUC_MASK				           0x01000000U
-#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT								  24U
-#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH								   1U
-#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR								   0U
-#define LPDDR4__DENALI_CTL_278__REDUC_WOSET								   0U
+#define LPDDR4__DENALI_CTL_278__REDUC_MASK                           0x01000000U
+#define LPDDR4__DENALI_CTL_278__REDUC_SHIFT                                  24U
+#define LPDDR4__DENALI_CTL_278__REDUC_WIDTH                                   1U
+#define LPDDR4__DENALI_CTL_278__REDUC_WOCLR                                   0U
+#define LPDDR4__DENALI_CTL_278__REDUC_WOSET                                   0U
 #define LPDDR4__REDUC__REG DENALI_CTL_278
 #define LPDDR4__REDUC__FLD LPDDR4__DENALI_CTL_278__REDUC
 
-#define LPDDR4__DENALI_CTL_279_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_CTL_279_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_CTL_279_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_CTL_279_WRITE_MASK                            0x0003FFFFU
 #define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_MASK        0x0003FFFFU
-#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT				0U
+#define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_SHIFT                0U
 #define LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN_WIDTH               18U
 #define LPDDR4__FAULT_FIFO_PROTECTION_EN__REG DENALI_CTL_279
 #define LPDDR4__FAULT_FIFO_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_279__FAULT_FIFO_PROTECTION_EN
 
-#define LPDDR4__DENALI_CTL_280_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_CTL_280_WRITE_MASK				            0x0003FFFFU
+#define LPDDR4__DENALI_CTL_280_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_CTL_280_WRITE_MASK                            0x0003FFFFU
 #define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_MASK    0x0003FFFFU
 #define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_SHIFT            0U
 #define LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS_WIDTH           18U
 #define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__REG DENALI_CTL_280
 #define LPDDR4__FAULT_FIFO_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_280__FAULT_FIFO_PROTECTION_STATUS
 
-#define LPDDR4__DENALI_CTL_281_READ_MASK				             0x0103FFFFU
-#define LPDDR4__DENALI_CTL_281_WRITE_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_CTL_281_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_CTL_281_WRITE_MASK                            0x0103FFFFU
 #define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_MASK 0x0003FFFFU
 #define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_SHIFT      0U
 #define LPDDR4__DENALI_CTL_281__FAULT_FIFO_PROTECTION_INJECTION_EN_WIDTH     18U
@@ -4888,8 +4888,8 @@
 #define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_281
 #define LPDDR4__WRITE_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_281__WRITE_ADDR_CHAN_PARITY_EN
 
-#define LPDDR4__DENALI_CTL_282_READ_MASK				             0x01010103U
-#define LPDDR4__DENALI_CTL_282_WRITE_MASK				            0x01010103U
+#define LPDDR4__DENALI_CTL_282_READ_MASK                             0x01010103U
+#define LPDDR4__DENALI_CTL_282_WRITE_MASK                            0x01010103U
 #define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_MASK       0x00000003U
 #define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_SHIFT               0U
 #define LPDDR4__DENALI_CTL_282__WRITE_DATA_CHAN_PARITY_EN_WIDTH               2U
@@ -4906,35 +4906,35 @@
 
 #define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_MASK        0x00010000U
 #define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_SHIFT               16U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH				1U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR				0U
-#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET				0U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WIDTH                1U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOCLR                0U
+#define LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN_WOSET                0U
 #define LPDDR4__READ_ADDR_CHAN_PARITY_EN__REG DENALI_CTL_282
 #define LPDDR4__READ_ADDR_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_ADDR_CHAN_PARITY_EN
 
 #define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_MASK        0x01000000U
 #define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_SHIFT               24U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH				1U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR				0U
-#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET				0U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WIDTH                1U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOCLR                0U
+#define LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN_WOSET                0U
 #define LPDDR4__READ_DATA_CHAN_PARITY_EN__REG DENALI_CTL_282
 #define LPDDR4__READ_DATA_CHAN_PARITY_EN__FLD LPDDR4__DENALI_CTL_282__READ_DATA_CHAN_PARITY_EN
 
-#define LPDDR4__DENALI_CTL_283_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_283_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK				   0x00000001U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET				           0U
+#define LPDDR4__DENALI_CTL_283_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_283_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED26_WOSET                           0U
 #define LPDDR4__MC_RESERVED26__REG DENALI_CTL_283
 #define LPDDR4__MC_RESERVED26__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED26
 
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET				           0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_283__MC_RESERVED27_WOSET                           0U
 #define LPDDR4__MC_RESERVED27__REG DENALI_CTL_283
 #define LPDDR4__MC_RESERVED27__FLD LPDDR4__DENALI_CTL_283__MC_RESERVED27
 
@@ -4948,14 +4948,14 @@
 
 #define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_MASK        0x01000000U
 #define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_SHIFT               24U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH				1U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR				0U
-#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET				0U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WIDTH                1U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOCLR                0U
+#define LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN_WOSET                0U
 #define LPDDR4__READ_PARITY_ERR_RRESP_EN__REG DENALI_CTL_283
 #define LPDDR4__READ_PARITY_ERR_RRESP_EN__FLD LPDDR4__DENALI_CTL_283__READ_PARITY_ERR_RRESP_EN
 
-#define LPDDR4__DENALI_CTL_284_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_284_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_284_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_284_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_MASK 0x00000001U
 #define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_SHIFT       0U
 #define LPDDR4__DENALI_CTL_284__WRITE_ADDR_CHAN_TRIGGER_PARITY_EN_WIDTH       1U
@@ -4988,8 +4988,8 @@
 #define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__REG DENALI_CTL_284
 #define LPDDR4__READ_ADDR_CHAN_TRIGGER_PARITY_EN__FLD LPDDR4__DENALI_CTL_284__READ_ADDR_CHAN_TRIGGER_PARITY_EN
 
-#define LPDDR4__DENALI_CTL_285_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_285_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_285_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_285_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_MASK 0x00000001U
 #define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_SHIFT        0U
 #define LPDDR4__DENALI_CTL_285__READ_DATA_CHAN_CORRUPT_PARITY_EN_WIDTH        1U
@@ -5022,917 +5022,917 @@
 #define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__REG DENALI_CTL_285
 #define LPDDR4__ENHANCED_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_285__ENHANCED_PARITY_PROTECTION_EN
 
-#define LPDDR4__DENALI_CTL_286_READ_MASK				             0x0F0F0F07U
-#define LPDDR4__DENALI_CTL_286_WRITE_MASK				            0x0F0F0F07U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK				 0x00000007U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH				         3U
+#define LPDDR4__DENALI_CTL_286_READ_MASK                             0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_286_WRITE_MASK                            0x0F0F0F07U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0_WIDTH                         3U
 #define LPDDR4__MEMDATA_RATIO_0__REG DENALI_CTL_286
 #define LPDDR4__MEMDATA_RATIO_0__FLD LPDDR4__DENALI_CTL_286__MEMDATA_RATIO_0
 
 #define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_MASK               0x00000F00U
-#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0_WIDTH                       4U
 #define LPDDR4__DEVICE0_BYTE0_CS0__REG DENALI_CTL_286
 #define LPDDR4__DEVICE0_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE0_BYTE0_CS0
 
 #define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_MASK               0x000F0000U
-#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0_WIDTH                       4U
 #define LPDDR4__DEVICE1_BYTE0_CS0__REG DENALI_CTL_286
 #define LPDDR4__DEVICE1_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE1_BYTE0_CS0
 
 #define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_MASK               0x0F000000U
-#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0_WIDTH                       4U
 #define LPDDR4__DEVICE2_BYTE0_CS0__REG DENALI_CTL_286
 #define LPDDR4__DEVICE2_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_286__DEVICE2_BYTE0_CS0
 
-#define LPDDR4__DENALI_CTL_287_READ_MASK				             0x0F0F070FU
-#define LPDDR4__DENALI_CTL_287_WRITE_MASK				            0x0F0F070FU
+#define LPDDR4__DENALI_CTL_287_READ_MASK                             0x0F0F070FU
+#define LPDDR4__DENALI_CTL_287_WRITE_MASK                            0x0F0F070FU
 #define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_MASK               0x0000000FU
-#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0_WIDTH                       4U
 #define LPDDR4__DEVICE3_BYTE0_CS0__REG DENALI_CTL_287
 #define LPDDR4__DEVICE3_BYTE0_CS0__FLD LPDDR4__DENALI_CTL_287__DEVICE3_BYTE0_CS0
 
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK				 0x00000700U
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH				         3U
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_MASK                 0x00000700U
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1_WIDTH                         3U
 #define LPDDR4__MEMDATA_RATIO_1__REG DENALI_CTL_287
 #define LPDDR4__MEMDATA_RATIO_1__FLD LPDDR4__DENALI_CTL_287__MEMDATA_RATIO_1
 
 #define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_MASK               0x000F0000U
-#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1_WIDTH                       4U
 #define LPDDR4__DEVICE0_BYTE0_CS1__REG DENALI_CTL_287
 #define LPDDR4__DEVICE0_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE0_BYTE0_CS1
 
 #define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_MASK               0x0F000000U
-#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1_WIDTH                       4U
 #define LPDDR4__DEVICE1_BYTE0_CS1__REG DENALI_CTL_287
 #define LPDDR4__DEVICE1_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_287__DEVICE1_BYTE0_CS1
 
-#define LPDDR4__DENALI_CTL_288_READ_MASK				             0x011F0F0FU
-#define LPDDR4__DENALI_CTL_288_WRITE_MASK				            0x011F0F0FU
+#define LPDDR4__DENALI_CTL_288_READ_MASK                             0x011F0F0FU
+#define LPDDR4__DENALI_CTL_288_WRITE_MASK                            0x011F0F0FU
 #define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_MASK               0x0000000FU
-#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1_WIDTH                       4U
 #define LPDDR4__DEVICE2_BYTE0_CS1__REG DENALI_CTL_288
 #define LPDDR4__DEVICE2_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE2_BYTE0_CS1
 
 #define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_MASK               0x00000F00U
-#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1_WIDTH                       4U
 #define LPDDR4__DEVICE3_BYTE0_CS1__REG DENALI_CTL_288
 #define LPDDR4__DEVICE3_BYTE0_CS1__FLD LPDDR4__DENALI_CTL_288__DEVICE3_BYTE0_CS1
 
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK				      0x001F0000U
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH				              5U
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_MASK                      0x001F0000U
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_288__Q_FULLNESS_WIDTH                              5U
 #define LPDDR4__Q_FULLNESS__REG DENALI_CTL_288
 #define LPDDR4__Q_FULLNESS__FLD LPDDR4__DENALI_CTL_288__Q_FULLNESS
 
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK				 0x01000000U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET				         0U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_MASK                 0x01000000U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT_WOSET                         0U
 #define LPDDR4__IN_ORDER_ACCEPT__REG DENALI_CTL_288
 #define LPDDR4__IN_ORDER_ACCEPT__FLD LPDDR4__DENALI_CTL_288__IN_ORDER_ACCEPT
 
-#define LPDDR4__DENALI_CTL_289_READ_MASK				             0x01000103U
-#define LPDDR4__DENALI_CTL_289_WRITE_MASK				            0x01000103U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK				    0x00000003U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH				            2U
+#define LPDDR4__DENALI_CTL_289_READ_MASK                             0x01000103U
+#define LPDDR4__DENALI_CTL_289_WRITE_MASK                            0x01000103U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_MASK                    0x00000003U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_289__WR_ORDER_REQ_WIDTH                            2U
 #define LPDDR4__WR_ORDER_REQ__REG DENALI_CTL_289
 #define LPDDR4__WR_ORDER_REQ__FLD LPDDR4__DENALI_CTL_289__WR_ORDER_REQ
 
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK				 0x00000100U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET				         0U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_MASK                 0x00000100U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY_WOSET                         0U
 #define LPDDR4__CONTROLLER_BUSY__REG DENALI_CTL_289
 #define LPDDR4__CONTROLLER_BUSY__FLD LPDDR4__DENALI_CTL_289__CONTROLLER_BUSY
 
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK				     0x00010000U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET				             0U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_MASK                     0x00010000U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_WOSET                             0U
 #define LPDDR4__CTRLUPD_REQ__REG DENALI_CTL_289
 #define LPDDR4__CTRLUPD_REQ__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ
 
 #define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_MASK         0x01000000U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT				24U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET				 0U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_SHIFT                24U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN_WOSET                 0U
 #define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__REG DENALI_CTL_289
 #define LPDDR4__CTRLUPD_REQ_PER_AREF_EN__FLD LPDDR4__DENALI_CTL_289__CTRLUPD_REQ_PER_AREF_EN
 
-#define LPDDR4__DENALI_CTL_290_READ_MASK				             0x03030301U
-#define LPDDR4__DENALI_CTL_290_WRITE_MASK				            0x03030301U
+#define LPDDR4__DENALI_CTL_290_READ_MASK                             0x03030301U
+#define LPDDR4__DENALI_CTL_290_WRITE_MASK                            0x03030301U
 #define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_MASK          0x00000001U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH				  1U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR				  0U
-#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET				  0U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WIDTH                  1U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOCLR                  0U
+#define LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE_WOSET                  0U
 #define LPDDR4__CTRLUPD_AREF_HP_ENABLE__REG DENALI_CTL_290
 #define LPDDR4__CTRLUPD_AREF_HP_ENABLE__FLD LPDDR4__DENALI_CTL_290__CTRLUPD_AREF_HP_ENABLE
 
 #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_MASK             0x00000300U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH				     2U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0_WIDTH                     2U
 #define LPDDR4__PREAMBLE_SUPPORT_F0__REG DENALI_CTL_290
 #define LPDDR4__PREAMBLE_SUPPORT_F0__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F0
 
 #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_MASK             0x00030000U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH				     2U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1_WIDTH                     2U
 #define LPDDR4__PREAMBLE_SUPPORT_F1__REG DENALI_CTL_290
 #define LPDDR4__PREAMBLE_SUPPORT_F1__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F1
 
 #define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_MASK             0x03000000U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT				    24U
-#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH				     2U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2_WIDTH                     2U
 #define LPDDR4__PREAMBLE_SUPPORT_F2__REG DENALI_CTL_290
 #define LPDDR4__PREAMBLE_SUPPORT_F2__FLD LPDDR4__DENALI_CTL_290__PREAMBLE_SUPPORT_F2
 
-#define LPDDR4__DENALI_CTL_291_READ_MASK				             0x1F010101U
-#define LPDDR4__DENALI_CTL_291_WRITE_MASK				            0x1F010101U
+#define LPDDR4__DENALI_CTL_291_READ_MASK                             0x1F010101U
+#define LPDDR4__DENALI_CTL_291_WRITE_MASK                            0x1F010101U
 #define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_MASK         0x00000001U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET				 0U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN_WOSET                 0U
 #define LPDDR4__RD_PREAMBLE_TRAINING_EN__REG DENALI_CTL_291
 #define LPDDR4__RD_PREAMBLE_TRAINING_EN__FLD LPDDR4__DENALI_CTL_291__RD_PREAMBLE_TRAINING_EN
 
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK				       0x00000100U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET				               0U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_291__WR_DBI_EN_WOSET                               0U
 #define LPDDR4__WR_DBI_EN__REG DENALI_CTL_291
 #define LPDDR4__WR_DBI_EN__FLD LPDDR4__DENALI_CTL_291__WR_DBI_EN
 
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK				       0x00010000U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET				               0U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_291__RD_DBI_EN_WOSET                               0U
 #define LPDDR4__RD_DBI_EN__REG DENALI_CTL_291
 #define LPDDR4__RD_DBI_EN__FLD LPDDR4__DENALI_CTL_291__RD_DBI_EN
 
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK				       0x1F000000U
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH				               5U
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_MASK                       0x1F000000U
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_291__DFI_ERROR_WIDTH                               5U
 #define LPDDR4__DFI_ERROR__REG DENALI_CTL_291
 #define LPDDR4__DFI_ERROR__FLD LPDDR4__DENALI_CTL_291__DFI_ERROR
 
-#define LPDDR4__DENALI_CTL_292_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH				         20U
+#define LPDDR4__DENALI_CTL_292_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO_WIDTH                         20U
 #define LPDDR4__DFI_ERROR_INFO__REG DENALI_CTL_292
 #define LPDDR4__DFI_ERROR_INFO__FLD LPDDR4__DENALI_CTL_292__DFI_ERROR_INFO
 
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET				           0U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_292__MC_RESERVED28_WOSET                           0U
 #define LPDDR4__MC_RESERVED28__REG DENALI_CTL_292
 #define LPDDR4__MC_RESERVED28__FLD LPDDR4__DENALI_CTL_292__MC_RESERVED28
 
-#define LPDDR4__DENALI_CTL_293_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK				    0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH				           32U
+#define LPDDR4__DENALI_CTL_293_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_MASK                    0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_293__INT_STATUS_0_WIDTH                           32U
 #define LPDDR4__INT_STATUS_0__REG DENALI_CTL_293
 #define LPDDR4__INT_STATUS_0__FLD LPDDR4__DENALI_CTL_293__INT_STATUS_0
 
-#define LPDDR4__DENALI_CTL_294_READ_MASK				             0x00001FFFU
-#define LPDDR4__DENALI_CTL_294_WRITE_MASK				            0x00001FFFU
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK				    0x00001FFFU
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH				           13U
+#define LPDDR4__DENALI_CTL_294_READ_MASK                             0x00001FFFU
+#define LPDDR4__DENALI_CTL_294_WRITE_MASK                            0x00001FFFU
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_MASK                    0x00001FFFU
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_294__INT_STATUS_1_WIDTH                           13U
 #define LPDDR4__INT_STATUS_1__REG DENALI_CTL_294
 #define LPDDR4__INT_STATUS_1__FLD LPDDR4__DENALI_CTL_294__INT_STATUS_1
 
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK				       0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH				              32U
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_MASK                       0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_295__INT_ACK_0_WIDTH                              32U
 #define LPDDR4__INT_ACK_0__REG DENALI_CTL_295
 #define LPDDR4__INT_ACK_0__FLD LPDDR4__DENALI_CTL_295__INT_ACK_0
 
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK				       0x00000FFFU
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH				              12U
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_MASK                       0x00000FFFU
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_296__INT_ACK_1_WIDTH                              12U
 #define LPDDR4__INT_ACK_1__REG DENALI_CTL_296
 #define LPDDR4__INT_ACK_1__FLD LPDDR4__DENALI_CTL_296__INT_ACK_1
 
-#define LPDDR4__DENALI_CTL_297_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK				      0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH				             32U
+#define LPDDR4__DENALI_CTL_297_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_MASK                      0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_297__INT_MASK_0_WIDTH                             32U
 #define LPDDR4__INT_MASK_0__REG DENALI_CTL_297
 #define LPDDR4__INT_MASK_0__FLD LPDDR4__DENALI_CTL_297__INT_MASK_0
 
-#define LPDDR4__DENALI_CTL_298_READ_MASK				             0x00001FFFU
-#define LPDDR4__DENALI_CTL_298_WRITE_MASK				            0x00001FFFU
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK				      0x00001FFFU
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH				             13U
+#define LPDDR4__DENALI_CTL_298_READ_MASK                             0x00001FFFU
+#define LPDDR4__DENALI_CTL_298_WRITE_MASK                            0x00001FFFU
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_MASK                      0x00001FFFU
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_298__INT_MASK_1_WIDTH                             13U
 #define LPDDR4__INT_MASK_1__REG DENALI_CTL_298
 #define LPDDR4__INT_MASK_1__FLD LPDDR4__DENALI_CTL_298__INT_MASK_1
 
-#define LPDDR4__DENALI_CTL_299_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_299_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_299_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_MASK             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH				    32U
+#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0_WIDTH                    32U
 #define LPDDR4__OUT_OF_RANGE_ADDR_0__REG DENALI_CTL_299
 #define LPDDR4__OUT_OF_RANGE_ADDR_0__FLD LPDDR4__DENALI_CTL_299__OUT_OF_RANGE_ADDR_0
 
-#define LPDDR4__DENALI_CTL_300_READ_MASK				             0x7F0FFF07U
-#define LPDDR4__DENALI_CTL_300_WRITE_MASK				            0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_300_READ_MASK                             0x7F0FFF07U
+#define LPDDR4__DENALI_CTL_300_WRITE_MASK                            0x7F0FFF07U
 #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_MASK             0x00000007U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH				     3U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1_WIDTH                     3U
 #define LPDDR4__OUT_OF_RANGE_ADDR_1__REG DENALI_CTL_300
 #define LPDDR4__OUT_OF_RANGE_ADDR_1__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_ADDR_1
 
 #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_MASK             0x000FFF00U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT				     8U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH				    12U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_SHIFT                     8U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH_WIDTH                    12U
 #define LPDDR4__OUT_OF_RANGE_LENGTH__REG DENALI_CTL_300
 #define LPDDR4__OUT_OF_RANGE_LENGTH__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_LENGTH
 
 #define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_MASK               0x7F000000U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH				       7U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE_WIDTH                       7U
 #define LPDDR4__OUT_OF_RANGE_TYPE__REG DENALI_CTL_300
 #define LPDDR4__OUT_OF_RANGE_TYPE__FLD LPDDR4__DENALI_CTL_300__OUT_OF_RANGE_TYPE
 
-#define LPDDR4__DENALI_CTL_301_READ_MASK				             0x0000003FU
-#define LPDDR4__DENALI_CTL_301_WRITE_MASK				            0x0000003FU
+#define LPDDR4__DENALI_CTL_301_READ_MASK                             0x0000003FU
+#define LPDDR4__DENALI_CTL_301_WRITE_MASK                            0x0000003FU
 #define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_MASK          0x0000003FU
-#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH				  6U
+#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID_WIDTH                  6U
 #define LPDDR4__OUT_OF_RANGE_SOURCE_ID__REG DENALI_CTL_301
 #define LPDDR4__OUT_OF_RANGE_SOURCE_ID__FLD LPDDR4__DENALI_CTL_301__OUT_OF_RANGE_SOURCE_ID
 
-#define LPDDR4__DENALI_CTL_302_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_302_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0_WIDTH                        32U
 #define LPDDR4__BIST_EXP_DATA_0__REG DENALI_CTL_302
 #define LPDDR4__BIST_EXP_DATA_0__FLD LPDDR4__DENALI_CTL_302__BIST_EXP_DATA_0
 
-#define LPDDR4__DENALI_CTL_303_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_303_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1_WIDTH                        32U
 #define LPDDR4__BIST_EXP_DATA_1__REG DENALI_CTL_303
 #define LPDDR4__BIST_EXP_DATA_1__FLD LPDDR4__DENALI_CTL_303__BIST_EXP_DATA_1
 
-#define LPDDR4__DENALI_CTL_304_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_304_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2_WIDTH                        32U
 #define LPDDR4__BIST_EXP_DATA_2__REG DENALI_CTL_304
 #define LPDDR4__BIST_EXP_DATA_2__FLD LPDDR4__DENALI_CTL_304__BIST_EXP_DATA_2
 
-#define LPDDR4__DENALI_CTL_305_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_305_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3_WIDTH                        32U
 #define LPDDR4__BIST_EXP_DATA_3__REG DENALI_CTL_305
 #define LPDDR4__BIST_EXP_DATA_3__FLD LPDDR4__DENALI_CTL_305__BIST_EXP_DATA_3
 
-#define LPDDR4__DENALI_CTL_306_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH				       32U
+#define LPDDR4__DENALI_CTL_306_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0_WIDTH                       32U
 #define LPDDR4__BIST_FAIL_DATA_0__REG DENALI_CTL_306
 #define LPDDR4__BIST_FAIL_DATA_0__FLD LPDDR4__DENALI_CTL_306__BIST_FAIL_DATA_0
 
-#define LPDDR4__DENALI_CTL_307_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH				       32U
+#define LPDDR4__DENALI_CTL_307_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1_WIDTH                       32U
 #define LPDDR4__BIST_FAIL_DATA_1__REG DENALI_CTL_307
 #define LPDDR4__BIST_FAIL_DATA_1__FLD LPDDR4__DENALI_CTL_307__BIST_FAIL_DATA_1
 
-#define LPDDR4__DENALI_CTL_308_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH				       32U
+#define LPDDR4__DENALI_CTL_308_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2_WIDTH                       32U
 #define LPDDR4__BIST_FAIL_DATA_2__REG DENALI_CTL_308
 #define LPDDR4__BIST_FAIL_DATA_2__FLD LPDDR4__DENALI_CTL_308__BIST_FAIL_DATA_2
 
-#define LPDDR4__DENALI_CTL_309_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH				       32U
+#define LPDDR4__DENALI_CTL_309_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3_WIDTH                       32U
 #define LPDDR4__BIST_FAIL_DATA_3__REG DENALI_CTL_309
 #define LPDDR4__BIST_FAIL_DATA_3__FLD LPDDR4__DENALI_CTL_309__BIST_FAIL_DATA_3
 
-#define LPDDR4__DENALI_CTL_310_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK				0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH				       32U
+#define LPDDR4__DENALI_CTL_310_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_MASK                0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0_WIDTH                       32U
 #define LPDDR4__BIST_FAIL_ADDR_0__REG DENALI_CTL_310
 #define LPDDR4__BIST_FAIL_ADDR_0__FLD LPDDR4__DENALI_CTL_310__BIST_FAIL_ADDR_0
 
-#define LPDDR4__DENALI_CTL_311_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_311_WRITE_MASK				            0x00000007U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK				0x00000007U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH				        3U
+#define LPDDR4__DENALI_CTL_311_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_311_WRITE_MASK                            0x00000007U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_MASK                0x00000007U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1_WIDTH                        3U
 #define LPDDR4__BIST_FAIL_ADDR_1__REG DENALI_CTL_311
 #define LPDDR4__BIST_FAIL_ADDR_1__FLD LPDDR4__DENALI_CTL_311__BIST_FAIL_ADDR_1
 
-#define LPDDR4__DENALI_CTL_312_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_312_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_312_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_312_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_MASK           0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH				  32U
+#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0_WIDTH                  32U
 #define LPDDR4__PORT_CMD_ERROR_ADDR_0__REG DENALI_CTL_312
 #define LPDDR4__PORT_CMD_ERROR_ADDR_0__FLD LPDDR4__DENALI_CTL_312__PORT_CMD_ERROR_ADDR_0
 
-#define LPDDR4__DENALI_CTL_313_READ_MASK				             0x03033F07U
-#define LPDDR4__DENALI_CTL_313_WRITE_MASK				            0x03033F07U
+#define LPDDR4__DENALI_CTL_313_READ_MASK                             0x03033F07U
+#define LPDDR4__DENALI_CTL_313_WRITE_MASK                            0x03033F07U
 #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_MASK           0x00000007U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT				   0U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH				   3U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_SHIFT                   0U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1_WIDTH                   3U
 #define LPDDR4__PORT_CMD_ERROR_ADDR_1__REG DENALI_CTL_313
 #define LPDDR4__PORT_CMD_ERROR_ADDR_1__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ADDR_1
 
 #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_MASK               0x00003F00U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH				       6U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID_WIDTH                       6U
 #define LPDDR4__PORT_CMD_ERROR_ID__REG DENALI_CTL_313
 #define LPDDR4__PORT_CMD_ERROR_ID__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_ID
 
 #define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_MASK             0x00030000U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT				    16U
-#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH				     2U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_SHIFT                    16U
+#define LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE_WIDTH                     2U
 #define LPDDR4__PORT_CMD_ERROR_TYPE__REG DENALI_CTL_313
 #define LPDDR4__PORT_CMD_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_313__PORT_CMD_ERROR_TYPE
 
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK				  0x03000000U
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH				          2U
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_MASK                  0x03000000U
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0_WIDTH                          2U
 #define LPDDR4__ODT_RD_MAP_CS0__REG DENALI_CTL_313
 #define LPDDR4__ODT_RD_MAP_CS0__FLD LPDDR4__DENALI_CTL_313__ODT_RD_MAP_CS0
 
-#define LPDDR4__DENALI_CTL_314_READ_MASK				             0xFF030303U
-#define LPDDR4__DENALI_CTL_314_WRITE_MASK				            0xFF030303U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK				  0x00000003U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH				          2U
+#define LPDDR4__DENALI_CTL_314_READ_MASK                             0xFF030303U
+#define LPDDR4__DENALI_CTL_314_WRITE_MASK                            0xFF030303U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_MASK                  0x00000003U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0_WIDTH                          2U
 #define LPDDR4__ODT_WR_MAP_CS0__REG DENALI_CTL_314
 #define LPDDR4__ODT_WR_MAP_CS0__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS0
 
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK				  0x00000300U
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH				          2U
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_MASK                  0x00000300U
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1_WIDTH                          2U
 #define LPDDR4__ODT_RD_MAP_CS1__REG DENALI_CTL_314
 #define LPDDR4__ODT_RD_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_RD_MAP_CS1
 
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK				  0x00030000U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH				          2U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_MASK                  0x00030000U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1_WIDTH                          2U
 #define LPDDR4__ODT_WR_MAP_CS1__REG DENALI_CTL_314
 #define LPDDR4__ODT_WR_MAP_CS1__FLD LPDDR4__DENALI_CTL_314__ODT_WR_MAP_CS1
 
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0_WIDTH                           8U
 #define LPDDR4__TODTL_2CMD_F0__REG DENALI_CTL_314
 #define LPDDR4__TODTL_2CMD_F0__FLD LPDDR4__DENALI_CTL_314__TODTL_2CMD_F0
 
-#define LPDDR4__DENALI_CTL_315_READ_MASK				             0x0FFF0F0FU
-#define LPDDR4__DENALI_CTL_315_WRITE_MASK				            0x0FFF0F0FU
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK				     0x0000000FU
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH				             4U
+#define LPDDR4__DENALI_CTL_315_READ_MASK                             0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_315_WRITE_MASK                            0x0FFF0F0FU
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F0_WIDTH                             4U
 #define LPDDR4__TODTH_WR_F0__REG DENALI_CTL_315
 #define LPDDR4__TODTH_WR_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F0
 
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK				     0x00000F00U
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT				             8U
-#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH				             4U
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_MASK                     0x00000F00U
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_SHIFT                             8U
+#define LPDDR4__DENALI_CTL_315__TODTH_RD_F0_WIDTH                             4U
 #define LPDDR4__TODTH_RD_F0__REG DENALI_CTL_315
 #define LPDDR4__TODTH_RD_F0__FLD LPDDR4__DENALI_CTL_315__TODTH_RD_F0
 
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1_WIDTH                           8U
 #define LPDDR4__TODTL_2CMD_F1__REG DENALI_CTL_315
 #define LPDDR4__TODTL_2CMD_F1__FLD LPDDR4__DENALI_CTL_315__TODTL_2CMD_F1
 
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK				     0x0F000000U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH				             4U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_315__TODTH_WR_F1_WIDTH                             4U
 #define LPDDR4__TODTH_WR_F1__REG DENALI_CTL_315
 #define LPDDR4__TODTH_WR_F1__FLD LPDDR4__DENALI_CTL_315__TODTH_WR_F1
 
-#define LPDDR4__DENALI_CTL_316_READ_MASK				             0x0F0FFF0FU
-#define LPDDR4__DENALI_CTL_316_WRITE_MASK				            0x0F0FFF0FU
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK				     0x0000000FU
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH				             4U
+#define LPDDR4__DENALI_CTL_316_READ_MASK                             0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_316_WRITE_MASK                            0x0F0FFF0FU
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_MASK                     0x0000000FU
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F1_WIDTH                             4U
 #define LPDDR4__TODTH_RD_F1__REG DENALI_CTL_316
 #define LPDDR4__TODTH_RD_F1__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F1
 
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK				   0x0000FF00U
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_MASK                   0x0000FF00U
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2_WIDTH                           8U
 #define LPDDR4__TODTL_2CMD_F2__REG DENALI_CTL_316
 #define LPDDR4__TODTL_2CMD_F2__FLD LPDDR4__DENALI_CTL_316__TODTL_2CMD_F2
 
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK				     0x000F0000U
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT				            16U
-#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH				             4U
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_MASK                     0x000F0000U
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_SHIFT                            16U
+#define LPDDR4__DENALI_CTL_316__TODTH_WR_F2_WIDTH                             4U
 #define LPDDR4__TODTH_WR_F2__REG DENALI_CTL_316
 #define LPDDR4__TODTH_WR_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_WR_F2
 
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK				     0x0F000000U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH				             4U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_MASK                     0x0F000000U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_316__TODTH_RD_F2_WIDTH                             4U
 #define LPDDR4__TODTH_RD_F2__REG DENALI_CTL_316
 #define LPDDR4__TODTH_RD_F2__FLD LPDDR4__DENALI_CTL_316__TODTH_RD_F2
 
-#define LPDDR4__DENALI_CTL_317_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_317_WRITE_MASK				            0x01010101U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK				       0x00000001U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET				               0U
+#define LPDDR4__DENALI_CTL_317_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_317_WRITE_MASK                            0x01010101U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F0_WOSET                               0U
 #define LPDDR4__ODT_EN_F0__REG DENALI_CTL_317
 #define LPDDR4__ODT_EN_F0__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F0
 
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK				       0x00000100U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT				               8U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET				               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_MASK                       0x00000100U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_SHIFT                               8U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F1_WOSET                               0U
 #define LPDDR4__ODT_EN_F1__REG DENALI_CTL_317
 #define LPDDR4__ODT_EN_F1__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F1
 
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK				       0x00010000U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET				               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_317__ODT_EN_F2_WOSET                               0U
 #define LPDDR4__ODT_EN_F2__REG DENALI_CTL_317
 #define LPDDR4__ODT_EN_F2__FLD LPDDR4__DENALI_CTL_317__ODT_EN_F2
 
 #define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_MASK         0x01000000U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT				24U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET				 0U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_SHIFT                24U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD_WOSET                 0U
 #define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__REG DENALI_CTL_317
 #define LPDDR4__EN_ODT_ASSERT_EXCEPT_RD__FLD LPDDR4__DENALI_CTL_317__EN_ODT_ASSERT_EXCEPT_RD
 
-#define LPDDR4__DENALI_CTL_318_READ_MASK				             0x3F3F3F3FU
-#define LPDDR4__DENALI_CTL_318_WRITE_MASK				            0x3F3F3F3FU
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK				   0x0000003FU
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH				           6U
+#define LPDDR4__DENALI_CTL_318_READ_MASK                             0x3F3F3F3FU
+#define LPDDR4__DENALI_CTL_318_WRITE_MASK                            0x3F3F3F3FU
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0_WIDTH                           6U
 #define LPDDR4__WR_TO_ODTH_F0__REG DENALI_CTL_318
 #define LPDDR4__WR_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F0
 
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK				   0x00003F00U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH				           6U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1_WIDTH                           6U
 #define LPDDR4__WR_TO_ODTH_F1__REG DENALI_CTL_318
 #define LPDDR4__WR_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F1
 
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK				   0x003F0000U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH				           6U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_MASK                   0x003F0000U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2_WIDTH                           6U
 #define LPDDR4__WR_TO_ODTH_F2__REG DENALI_CTL_318
 #define LPDDR4__WR_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_318__WR_TO_ODTH_F2
 
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK				   0x3F000000U
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH				           6U
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_MASK                   0x3F000000U
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0_WIDTH                           6U
 #define LPDDR4__RD_TO_ODTH_F0__REG DENALI_CTL_318
 #define LPDDR4__RD_TO_ODTH_F0__FLD LPDDR4__DENALI_CTL_318__RD_TO_ODTH_F0
 
-#define LPDDR4__DENALI_CTL_319_READ_MASK				             0x1F1F3F3FU
-#define LPDDR4__DENALI_CTL_319_WRITE_MASK				            0x1F1F3F3FU
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK				   0x0000003FU
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH				           6U
+#define LPDDR4__DENALI_CTL_319_READ_MASK                             0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_319_WRITE_MASK                            0x1F1F3F3FU
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_MASK                   0x0000003FU
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1_WIDTH                           6U
 #define LPDDR4__RD_TO_ODTH_F1__REG DENALI_CTL_319
 #define LPDDR4__RD_TO_ODTH_F1__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F1
 
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK				   0x00003F00U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH				           6U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_MASK                   0x00003F00U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2_WIDTH                           6U
 #define LPDDR4__RD_TO_ODTH_F2__REG DENALI_CTL_319
 #define LPDDR4__RD_TO_ODTH_F2__FLD LPDDR4__DENALI_CTL_319__RD_TO_ODTH_F2
 
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK				   0x001F0000U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH				           5U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_MASK                   0x001F0000U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0_WIDTH                           5U
 #define LPDDR4__RW2MRW_DLY_F0__REG DENALI_CTL_319
 #define LPDDR4__RW2MRW_DLY_F0__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F0
 
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK				   0x1F000000U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH				           5U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_MASK                   0x1F000000U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1_WIDTH                           5U
 #define LPDDR4__RW2MRW_DLY_F1__REG DENALI_CTL_319
 #define LPDDR4__RW2MRW_DLY_F1__FLD LPDDR4__DENALI_CTL_319__RW2MRW_DLY_F1
 
-#define LPDDR4__DENALI_CTL_320_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_320_WRITE_MASK				            0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK				   0x0000001FU
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH				           5U
+#define LPDDR4__DENALI_CTL_320_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_320_WRITE_MASK                            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_MASK                   0x0000001FU
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2_WIDTH                           5U
 #define LPDDR4__RW2MRW_DLY_F2__REG DENALI_CTL_320
 #define LPDDR4__RW2MRW_DLY_F2__FLD LPDDR4__DENALI_CTL_320__RW2MRW_DLY_F2
 
 #define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_MASK               0x00001F00U
-#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0_WIDTH                       5U
 #define LPDDR4__R2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
 #define LPDDR4__R2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2R_DIFFCS_DLY_F0
 
 #define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_MASK               0x001F0000U
-#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0_WIDTH                       5U
 #define LPDDR4__R2W_DIFFCS_DLY_F0__REG DENALI_CTL_320
 #define LPDDR4__R2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__R2W_DIFFCS_DLY_F0
 
 #define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_MASK               0x1F000000U
-#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0_WIDTH                       5U
 #define LPDDR4__W2R_DIFFCS_DLY_F0__REG DENALI_CTL_320
 #define LPDDR4__W2R_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_320__W2R_DIFFCS_DLY_F0
 
-#define LPDDR4__DENALI_CTL_321_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_321_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_321_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_321_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_MASK               0x0000001FU
-#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0_WIDTH                       5U
 #define LPDDR4__W2W_DIFFCS_DLY_F0__REG DENALI_CTL_321
 #define LPDDR4__W2W_DIFFCS_DLY_F0__FLD LPDDR4__DENALI_CTL_321__W2W_DIFFCS_DLY_F0
 
 #define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_MASK               0x00001F00U
-#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1_WIDTH                       5U
 #define LPDDR4__R2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
 #define LPDDR4__R2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2R_DIFFCS_DLY_F1
 
 #define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_MASK               0x001F0000U
-#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1_WIDTH                       5U
 #define LPDDR4__R2W_DIFFCS_DLY_F1__REG DENALI_CTL_321
 #define LPDDR4__R2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__R2W_DIFFCS_DLY_F1
 
 #define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_MASK               0x1F000000U
-#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1_WIDTH                       5U
 #define LPDDR4__W2R_DIFFCS_DLY_F1__REG DENALI_CTL_321
 #define LPDDR4__W2R_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_321__W2R_DIFFCS_DLY_F1
 
-#define LPDDR4__DENALI_CTL_322_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_322_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_322_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_322_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_MASK               0x0000001FU
-#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1_WIDTH                       5U
 #define LPDDR4__W2W_DIFFCS_DLY_F1__REG DENALI_CTL_322
 #define LPDDR4__W2W_DIFFCS_DLY_F1__FLD LPDDR4__DENALI_CTL_322__W2W_DIFFCS_DLY_F1
 
 #define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_MASK               0x00001F00U
-#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2_WIDTH                       5U
 #define LPDDR4__R2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
 #define LPDDR4__R2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2R_DIFFCS_DLY_F2
 
 #define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_MASK               0x001F0000U
-#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2_WIDTH                       5U
 #define LPDDR4__R2W_DIFFCS_DLY_F2__REG DENALI_CTL_322
 #define LPDDR4__R2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__R2W_DIFFCS_DLY_F2
 
 #define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_MASK               0x1F000000U
-#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2_WIDTH                       5U
 #define LPDDR4__W2R_DIFFCS_DLY_F2__REG DENALI_CTL_322
 #define LPDDR4__W2R_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_322__W2R_DIFFCS_DLY_F2
 
-#define LPDDR4__DENALI_CTL_323_READ_MASK				             0x1F1F1F1FU
-#define LPDDR4__DENALI_CTL_323_WRITE_MASK				            0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_323_READ_MASK                             0x1F1F1F1FU
+#define LPDDR4__DENALI_CTL_323_WRITE_MASK                            0x1F1F1F1FU
 #define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_MASK               0x0000001FU
-#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2_WIDTH                       5U
 #define LPDDR4__W2W_DIFFCS_DLY_F2__REG DENALI_CTL_323
 #define LPDDR4__W2W_DIFFCS_DLY_F2__FLD LPDDR4__DENALI_CTL_323__W2W_DIFFCS_DLY_F2
 
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK				  0x00001F00U
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH				          5U
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_MASK                  0x00001F00U
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY_WIDTH                          5U
 #define LPDDR4__R2R_SAMECS_DLY__REG DENALI_CTL_323
 #define LPDDR4__R2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_323__R2R_SAMECS_DLY
 
 #define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_MASK               0x001F0000U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0_WIDTH                       5U
 #define LPDDR4__R2W_SAMECS_DLY_F0__REG DENALI_CTL_323
 #define LPDDR4__R2W_SAMECS_DLY_F0__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F0
 
 #define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_MASK               0x1F000000U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1_WIDTH                       5U
 #define LPDDR4__R2W_SAMECS_DLY_F1__REG DENALI_CTL_323
 #define LPDDR4__R2W_SAMECS_DLY_F1__FLD LPDDR4__DENALI_CTL_323__R2W_SAMECS_DLY_F1
 
-#define LPDDR4__DENALI_CTL_324_READ_MASK				             0x0F1F1F1FU
-#define LPDDR4__DENALI_CTL_324_WRITE_MASK				            0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_324_READ_MASK                             0x0F1F1F1FU
+#define LPDDR4__DENALI_CTL_324_WRITE_MASK                            0x0F1F1F1FU
 #define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_MASK               0x0000001FU
-#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH				       5U
+#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2_WIDTH                       5U
 #define LPDDR4__R2W_SAMECS_DLY_F2__REG DENALI_CTL_324
 #define LPDDR4__R2W_SAMECS_DLY_F2__FLD LPDDR4__DENALI_CTL_324__R2W_SAMECS_DLY_F2
 
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK				  0x00001F00U
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH				          5U
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_MASK                  0x00001F00U
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY_WIDTH                          5U
 #define LPDDR4__W2R_SAMECS_DLY__REG DENALI_CTL_324
 #define LPDDR4__W2R_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2R_SAMECS_DLY
 
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK				  0x001F0000U
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT				         16U
-#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH				          5U
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_MASK                  0x001F0000U
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_SHIFT                         16U
+#define LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY_WIDTH                          5U
 #define LPDDR4__W2W_SAMECS_DLY__REG DENALI_CTL_324
 #define LPDDR4__W2W_SAMECS_DLY__FLD LPDDR4__DENALI_CTL_324__W2W_SAMECS_DLY
 
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0_WIDTH                           4U
 #define LPDDR4__TDQSCK_MAX_F0__REG DENALI_CTL_324
 #define LPDDR4__TDQSCK_MAX_F0__FLD LPDDR4__DENALI_CTL_324__TDQSCK_MAX_F0
 
-#define LPDDR4__DENALI_CTL_325_READ_MASK				             0x0F070F07U
-#define LPDDR4__DENALI_CTL_325_WRITE_MASK				            0x0F070F07U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK				   0x00000007U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_325_READ_MASK                             0x0F070F07U
+#define LPDDR4__DENALI_CTL_325_WRITE_MASK                            0x0F070F07U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0_WIDTH                           3U
 #define LPDDR4__TDQSCK_MIN_F0__REG DENALI_CTL_325
 #define LPDDR4__TDQSCK_MIN_F0__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F0
 
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1_WIDTH                           4U
 #define LPDDR4__TDQSCK_MAX_F1__REG DENALI_CTL_325
 #define LPDDR4__TDQSCK_MAX_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F1
 
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK				   0x00070000U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1_WIDTH                           3U
 #define LPDDR4__TDQSCK_MIN_F1__REG DENALI_CTL_325
 #define LPDDR4__TDQSCK_MIN_F1__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MIN_F1
 
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2_WIDTH                           4U
 #define LPDDR4__TDQSCK_MAX_F2__REG DENALI_CTL_325
 #define LPDDR4__TDQSCK_MAX_F2__FLD LPDDR4__DENALI_CTL_325__TDQSCK_MAX_F2
 
-#define LPDDR4__DENALI_CTL_326_READ_MASK				             0x00000707U
-#define LPDDR4__DENALI_CTL_326_WRITE_MASK				            0x00000707U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK				   0x00000007U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_326_READ_MASK                             0x00000707U
+#define LPDDR4__DENALI_CTL_326_WRITE_MASK                            0x00000707U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2_WIDTH                           3U
 #define LPDDR4__TDQSCK_MIN_F2__REG DENALI_CTL_326
 #define LPDDR4__TDQSCK_MIN_F2__FLD LPDDR4__DENALI_CTL_326__TDQSCK_MIN_F2
 
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK				0x00000700U
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH				        3U
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_MASK                0x00000700U
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE_WIDTH                        3U
 #define LPDDR4__SW_LEVELING_MODE__REG DENALI_CTL_326
 #define LPDDR4__SW_LEVELING_MODE__FLD LPDDR4__DENALI_CTL_326__SW_LEVELING_MODE
 
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK				      0x00010000U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET				              0U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_MASK                      0x00010000U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_326__SWLVL_LOAD_WOSET                              0U
 #define LPDDR4__SWLVL_LOAD__REG DENALI_CTL_326
 #define LPDDR4__SWLVL_LOAD__FLD LPDDR4__DENALI_CTL_326__SWLVL_LOAD
 
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK				     0x01000000U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT				            24U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH				             1U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR				             0U
-#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET				             0U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_MASK                     0x01000000U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_SHIFT                            24U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WIDTH                             1U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOCLR                             0U
+#define LPDDR4__DENALI_CTL_326__SWLVL_START_WOSET                             0U
 #define LPDDR4__SWLVL_START__REG DENALI_CTL_326
 #define LPDDR4__SWLVL_START__FLD LPDDR4__DENALI_CTL_326__SWLVL_START
 
-#define LPDDR4__DENALI_CTL_327_READ_MASK				             0x01010100U
-#define LPDDR4__DENALI_CTL_327_WRITE_MASK				            0x01010100U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK				      0x00000001U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT				              0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH				              1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR				              0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET				              0U
+#define LPDDR4__DENALI_CTL_327_READ_MASK                             0x01010100U
+#define LPDDR4__DENALI_CTL_327_WRITE_MASK                            0x01010100U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_MASK                      0x00000001U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_SHIFT                              0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WIDTH                              1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOCLR                              0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_EXIT_WOSET                              0U
 #define LPDDR4__SWLVL_EXIT__REG DENALI_CTL_327
 #define LPDDR4__SWLVL_EXIT__FLD LPDDR4__DENALI_CTL_327__SWLVL_EXIT
 
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET				           0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE_WOSET                           0U
 #define LPDDR4__SWLVL_OP_DONE__REG DENALI_CTL_327
 #define LPDDR4__SWLVL_OP_DONE__FLD LPDDR4__DENALI_CTL_327__SWLVL_OP_DONE
 
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK				    0x00010000U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET				            0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_0_WOSET                            0U
 #define LPDDR4__SWLVL_RESP_0__REG DENALI_CTL_327
 #define LPDDR4__SWLVL_RESP_0__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_0
 
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK				    0x01000000U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET				            0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_MASK                    0x01000000U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_327__SWLVL_RESP_1_WOSET                            0U
 #define LPDDR4__SWLVL_RESP_1__REG DENALI_CTL_327
 #define LPDDR4__SWLVL_RESP_1__FLD LPDDR4__DENALI_CTL_327__SWLVL_RESP_1
 
-#define LPDDR4__DENALI_CTL_328_READ_MASK				             0x00010101U
-#define LPDDR4__DENALI_CTL_328_WRITE_MASK				            0x00010101U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK				    0x00000001U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET				            0U
+#define LPDDR4__DENALI_CTL_328_READ_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_328_WRITE_MASK                            0x00010101U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_2_WOSET                            0U
 #define LPDDR4__SWLVL_RESP_2__REG DENALI_CTL_328
 #define LPDDR4__SWLVL_RESP_2__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_2
 
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK				    0x00000100U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET				            0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_328__SWLVL_RESP_3_WOSET                            0U
 #define LPDDR4__SWLVL_RESP_3__REG DENALI_CTL_328
 #define LPDDR4__SWLVL_RESP_3__FLD LPDDR4__DENALI_CTL_328__SWLVL_RESP_3
 
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK				0x00010000U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET				        0U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_MASK                0x00010000U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN_WOSET                        0U
 #define LPDDR4__PHYUPD_APPEND_EN__REG DENALI_CTL_328
 #define LPDDR4__PHYUPD_APPEND_EN__FLD LPDDR4__DENALI_CTL_328__PHYUPD_APPEND_EN
 
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK				       0x01000000U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT				              24U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET				               0U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_MASK                       0x01000000U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_SHIFT                              24U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_328__WRLVL_REQ_WOSET                               0U
 #define LPDDR4__WRLVL_REQ__REG DENALI_CTL_328
 #define LPDDR4__WRLVL_REQ__FLD LPDDR4__DENALI_CTL_328__WRLVL_REQ
 
-#define LPDDR4__DENALI_CTL_329_READ_MASK				             0x013F3F01U
-#define LPDDR4__DENALI_CTL_329_WRITE_MASK				            0x013F3F01U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK				        0x00000001U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT								0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH								1U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR								0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET								0U
+#define LPDDR4__DENALI_CTL_329_READ_MASK                             0x013F3F01U
+#define LPDDR4__DENALI_CTL_329_WRITE_MASK                            0x013F3F01U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_MASK                        0x00000001U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_CS_WOSET                                0U
 #define LPDDR4__WRLVL_CS__REG DENALI_CTL_329
 #define LPDDR4__WRLVL_CS__FLD LPDDR4__DENALI_CTL_329__WRLVL_CS
 
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK				         0x00003F00U
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT								 8U
-#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH								 6U
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_MASK                         0x00003F00U
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_SHIFT                                 8U
+#define LPDDR4__DENALI_CTL_329__WLDQSEN_WIDTH                                 6U
 #define LPDDR4__WLDQSEN__REG DENALI_CTL_329
 #define LPDDR4__WLDQSEN__FLD LPDDR4__DENALI_CTL_329__WLDQSEN
 
-#define LPDDR4__DENALI_CTL_329__WLMRD_MASK				           0x003F0000U
-#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT								  16U
-#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH								   6U
+#define LPDDR4__DENALI_CTL_329__WLMRD_MASK                           0x003F0000U
+#define LPDDR4__DENALI_CTL_329__WLMRD_SHIFT                                  16U
+#define LPDDR4__DENALI_CTL_329__WLMRD_WIDTH                                   6U
 #define LPDDR4__WLMRD__REG DENALI_CTL_329
 #define LPDDR4__WLMRD__FLD LPDDR4__DENALI_CTL_329__WLMRD
 
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK				        0x01000000U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT				               24U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH								1U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR								0U
-#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET								0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_MASK                        0x01000000U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_SHIFT                               24U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_329__WRLVL_EN_WOSET                                0U
 #define LPDDR4__WRLVL_EN__REG DENALI_CTL_329
 #define LPDDR4__WRLVL_EN__FLD LPDDR4__DENALI_CTL_329__WRLVL_EN
 
-#define LPDDR4__DENALI_CTL_330_READ_MASK				             0x0F010101U
-#define LPDDR4__DENALI_CTL_330_WRITE_MASK				            0x0F010101U
+#define LPDDR4__DENALI_CTL_330_READ_MASK                             0x0F010101U
+#define LPDDR4__DENALI_CTL_330_WRITE_MASK                            0x0F010101U
 #define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_MASK              0x00000001U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET				      0U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE_WOSET                      0U
 #define LPDDR4__DFI_PHY_WRLVL_MODE__REG DENALI_CTL_330
 #define LPDDR4__DFI_PHY_WRLVL_MODE__FLD LPDDR4__DENALI_CTL_330__DFI_PHY_WRLVL_MODE
 
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET				          0U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC_WOSET                          0U
 #define LPDDR4__WRLVL_PERIODIC__REG DENALI_CTL_330
 #define LPDDR4__WRLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_330__WRLVL_PERIODIC
 
 #define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET				      0U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT_WOSET                      0U
 #define LPDDR4__WRLVL_ON_SREF_EXIT__REG DENALI_CTL_330
 #define LPDDR4__WRLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_330__WRLVL_ON_SREF_EXIT
 
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK				 0x0F000000U
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH				         4U
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_MASK                 0x0F000000U
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK_WIDTH                         4U
 #define LPDDR4__WRLVL_RESP_MASK__REG DENALI_CTL_330
 #define LPDDR4__WRLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_330__WRLVL_RESP_MASK
 
-#define LPDDR4__DENALI_CTL_331_READ_MASK				             0x07030101U
-#define LPDDR4__DENALI_CTL_331_WRITE_MASK				            0x07030101U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK				   0x00000001U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET				           0U
+#define LPDDR4__DENALI_CTL_331_READ_MASK                             0x07030101U
+#define LPDDR4__DENALI_CTL_331_WRITE_MASK                            0x07030101U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN_WOSET                           0U
 #define LPDDR4__WRLVL_AREF_EN__REG DENALI_CTL_331
 #define LPDDR4__WRLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_331__WRLVL_AREF_EN
 
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK				    0x00000100U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET				            0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ROTATE_WOSET                            0U
 #define LPDDR4__WRLVL_ROTATE__REG DENALI_CTL_331
 #define LPDDR4__WRLVL_ROTATE__FLD LPDDR4__DENALI_CTL_331__WRLVL_ROTATE
 
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK				    0x00030000U
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH				            2U
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_MASK                    0x00030000U
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP_WIDTH                            2U
 #define LPDDR4__WRLVL_CS_MAP__REG DENALI_CTL_331
 #define LPDDR4__WRLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_331__WRLVL_CS_MAP
 
 #define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_MASK              0x07000000U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH				      3U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS_WIDTH                      3U
 #define LPDDR4__WRLVL_ERROR_STATUS__REG DENALI_CTL_331
 #define LPDDR4__WRLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_331__WRLVL_ERROR_STATUS
 
-#define LPDDR4__DENALI_CTL_332_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_332_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_332_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_332_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__WRLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_332
 #define LPDDR4__WRLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_NORM_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_332
 #define LPDDR4__WRLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_332__WRLVL_HIGH_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_333_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_333_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_333_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_333_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0_WIDTH                       16U
 #define LPDDR4__WRLVL_TIMEOUT_F0__REG DENALI_CTL_333
 #define LPDDR4__WRLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_TIMEOUT_F0
 
@@ -5942,8 +5942,8 @@
 #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_333
 #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_333__WRLVL_SW_PROMOTE_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_334_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_334_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_334_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
 #define LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
@@ -5951,27 +5951,27 @@
 #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_334__WRLVL_DFI_PROMOTE_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__WRLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_334
 #define LPDDR4__WRLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_334__WRLVL_NORM_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_335_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_335_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_335_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_335
 #define LPDDR4__WRLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_HIGH_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1_WIDTH                       16U
 #define LPDDR4__WRLVL_TIMEOUT_F1__REG DENALI_CTL_335
 #define LPDDR4__WRLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_335__WRLVL_TIMEOUT_F1
 
-#define LPDDR4__DENALI_CTL_336_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_336_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_336_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_SHIFT           0U
 #define LPDDR4__DENALI_CTL_336__WRLVL_SW_PROMOTE_THRESHOLD_F1_WIDTH          16U
@@ -5984,25 +5984,25 @@
 #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_336
 #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_336__WRLVL_DFI_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_337_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_337_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_337_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__WRLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_337
 #define LPDDR4__WRLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_NORM_THRESHOLD_F2
 
 #define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_337
 #define LPDDR4__WRLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_337__WRLVL_HIGH_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_338_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_338_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_338_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2_WIDTH                       16U
 #define LPDDR4__WRLVL_TIMEOUT_F2__REG DENALI_CTL_338
 #define LPDDR4__WRLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_TIMEOUT_F2
 
@@ -6012,177 +6012,177 @@
 #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_338
 #define LPDDR4__WRLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_338__WRLVL_SW_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_339_READ_MASK				             0x0000FFFFU
-#define LPDDR4__DENALI_CTL_339_WRITE_MASK				            0x0000FFFFU
+#define LPDDR4__DENALI_CTL_339_READ_MASK                             0x0000FFFFU
+#define LPDDR4__DENALI_CTL_339_WRITE_MASK                            0x0000FFFFU
 #define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
 #define LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
 #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_339
 #define LPDDR4__WRLVL_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_339__WRLVL_DFI_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK				       0x00010000U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT				              16U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET				               0U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_MASK                       0x00010000U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_SHIFT                              16U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_339__RDLVL_REQ_WOSET                               0U
 #define LPDDR4__RDLVL_REQ__REG DENALI_CTL_339
 #define LPDDR4__RDLVL_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_REQ
 
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET				          0U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ_WOSET                          0U
 #define LPDDR4__RDLVL_GATE_REQ__REG DENALI_CTL_339
 #define LPDDR4__RDLVL_GATE_REQ__FLD LPDDR4__DENALI_CTL_339__RDLVL_GATE_REQ
 
-#define LPDDR4__DENALI_CTL_340_READ_MASK				             0x010F0F01U
-#define LPDDR4__DENALI_CTL_340_WRITE_MASK				            0x010F0F01U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK				        0x00000001U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT								0U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH								1U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR								0U
-#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET								0U
+#define LPDDR4__DENALI_CTL_340_READ_MASK                             0x010F0F01U
+#define LPDDR4__DENALI_CTL_340_WRITE_MASK                            0x010F0F01U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_MASK                        0x00000001U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_SHIFT                                0U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_340__RDLVL_CS_WOSET                                0U
 #define LPDDR4__RDLVL_CS__REG DENALI_CTL_340
 #define LPDDR4__RDLVL_CS__FLD LPDDR4__DENALI_CTL_340__RDLVL_CS
 
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK				    0x00000F00U
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH				            4U
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_MASK                    0x00000F00U
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN_WIDTH                            4U
 #define LPDDR4__RDLVL_SEQ_EN__REG DENALI_CTL_340
 #define LPDDR4__RDLVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_SEQ_EN
 
 #define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_MASK               0x000F0000U
-#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH				       4U
+#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN_WIDTH                       4U
 #define LPDDR4__RDLVL_GATE_SEQ_EN__REG DENALI_CTL_340
 #define LPDDR4__RDLVL_GATE_SEQ_EN__FLD LPDDR4__DENALI_CTL_340__RDLVL_GATE_SEQ_EN
 
 #define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_MASK              0x01000000U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET				      0U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE_WOSET                      0U
 #define LPDDR4__DFI_PHY_RDLVL_MODE__REG DENALI_CTL_340
 #define LPDDR4__DFI_PHY_RDLVL_MODE__FLD LPDDR4__DENALI_CTL_340__DFI_PHY_RDLVL_MODE
 
-#define LPDDR4__DENALI_CTL_341_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_341_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_341_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_341_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_MASK         0x00000001U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET				 0U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE_WOSET                 0U
 #define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__REG DENALI_CTL_341
 #define LPDDR4__DFI_PHY_RDLVL_GATE_MODE__FLD LPDDR4__DENALI_CTL_341__DFI_PHY_RDLVL_GATE_MODE
 
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK				  0x00000100U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT				          8U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET				          0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_MASK                  0x00000100U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_SHIFT                          8U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC_WOSET                          0U
 #define LPDDR4__RDLVL_PERIODIC__REG DENALI_CTL_341
 #define LPDDR4__RDLVL_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_PERIODIC
 
 #define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET				      0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT_WOSET                      0U
 #define LPDDR4__RDLVL_ON_SREF_EXIT__REG DENALI_CTL_341
 #define LPDDR4__RDLVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_341__RDLVL_ON_SREF_EXIT
 
 #define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_MASK             0x01000000U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT				    24U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH				     1U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR				     0U
-#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET				     0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_SHIFT                    24U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WIDTH                     1U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOCLR                     0U
+#define LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC_WOSET                     0U
 #define LPDDR4__RDLVL_GATE_PERIODIC__REG DENALI_CTL_341
 #define LPDDR4__RDLVL_GATE_PERIODIC__FLD LPDDR4__DENALI_CTL_341__RDLVL_GATE_PERIODIC
 
-#define LPDDR4__DENALI_CTL_342_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_342_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_342_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_342_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_MASK         0x00000001U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH				 1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR				 0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET				 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WIDTH                 1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOCLR                 0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT_WOSET                 0U
 #define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__REG DENALI_CTL_342
 #define LPDDR4__RDLVL_GATE_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_ON_SREF_EXIT
 
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET				           0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN_WOSET                           0U
 #define LPDDR4__RDLVL_AREF_EN__REG DENALI_CTL_342
 #define LPDDR4__RDLVL_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_AREF_EN
 
 #define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET				      0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN_WOSET                      0U
 #define LPDDR4__RDLVL_GATE_AREF_EN__REG DENALI_CTL_342
 #define LPDDR4__RDLVL_GATE_AREF_EN__FLD LPDDR4__DENALI_CTL_342__RDLVL_GATE_AREF_EN
 
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET				           0U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_342__MC_RESERVED29_WOSET                           0U
 #define LPDDR4__MC_RESERVED29__REG DENALI_CTL_342
 #define LPDDR4__MC_RESERVED29__FLD LPDDR4__DENALI_CTL_342__MC_RESERVED29
 
-#define LPDDR4__DENALI_CTL_343_READ_MASK				             0x03030101U
-#define LPDDR4__DENALI_CTL_343_WRITE_MASK				            0x03030101U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK				    0x00000001U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET				            0U
+#define LPDDR4__DENALI_CTL_343_READ_MASK                             0x03030101U
+#define LPDDR4__DENALI_CTL_343_WRITE_MASK                            0x03030101U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_MASK                    0x00000001U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_ROTATE_WOSET                            0U
 #define LPDDR4__RDLVL_ROTATE__REG DENALI_CTL_343
 #define LPDDR4__RDLVL_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_ROTATE
 
 #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_MASK               0x00000100U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH				       1U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR				       0U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET				       0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WIDTH                       1U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOCLR                       0U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE_WOSET                       0U
 #define LPDDR4__RDLVL_GATE_ROTATE__REG DENALI_CTL_343
 #define LPDDR4__RDLVL_GATE_ROTATE__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_ROTATE
 
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK				    0x00030000U
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH				            2U
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_MASK                    0x00030000U
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP_WIDTH                            2U
 #define LPDDR4__RDLVL_CS_MAP__REG DENALI_CTL_343
 #define LPDDR4__RDLVL_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_CS_MAP
 
 #define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_MASK               0x03000000U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH				       2U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP_WIDTH                       2U
 #define LPDDR4__RDLVL_GATE_CS_MAP__REG DENALI_CTL_343
 #define LPDDR4__RDLVL_GATE_CS_MAP__FLD LPDDR4__DENALI_CTL_343__RDLVL_GATE_CS_MAP
 
-#define LPDDR4__DENALI_CTL_344_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_344_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_344_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__RDLVL_NORM_THRESHOLD_F0__REG DENALI_CTL_344
 #define LPDDR4__RDLVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_NORM_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_344
 #define LPDDR4__RDLVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_344__RDLVL_HIGH_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_345_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_345_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_345_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0_WIDTH                       16U
 #define LPDDR4__RDLVL_TIMEOUT_F0__REG DENALI_CTL_345
 #define LPDDR4__RDLVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_TIMEOUT_F0
 
@@ -6192,8 +6192,8 @@
 #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_345
 #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_345__RDLVL_SW_PROMOTE_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_346_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_346_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_346_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
 #define LPDDR4__DENALI_CTL_346__RDLVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
@@ -6206,8 +6206,8 @@
 #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__REG DENALI_CTL_346
 #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_346__RDLVL_GATE_NORM_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_347_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_347_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_347_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_MASK    0x0000FFFFU
 #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_SHIFT            0U
 #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0_WIDTH           16U
@@ -6215,13 +6215,13 @@
 #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_HIGH_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH				  16U
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0_WIDTH                  16U
 #define LPDDR4__RDLVL_GATE_TIMEOUT_F0__REG DENALI_CTL_347
 #define LPDDR4__RDLVL_GATE_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_347__RDLVL_GATE_TIMEOUT_F0
 
-#define LPDDR4__DENALI_CTL_348_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_348_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_348_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_SHIFT      0U
 #define LPDDR4__DENALI_CTL_348__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F0_WIDTH     16U
@@ -6234,25 +6234,25 @@
 #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_348
 #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_348__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_349_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_349_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_349_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__RDLVL_NORM_THRESHOLD_F1__REG DENALI_CTL_349
 #define LPDDR4__RDLVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_NORM_THRESHOLD_F1
 
 #define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_349
 #define LPDDR4__RDLVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_349__RDLVL_HIGH_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_350_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_350_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_350_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1_WIDTH                       16U
 #define LPDDR4__RDLVL_TIMEOUT_F1__REG DENALI_CTL_350
 #define LPDDR4__RDLVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_TIMEOUT_F1
 
@@ -6262,8 +6262,8 @@
 #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_350
 #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_350__RDLVL_SW_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_351_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_351_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_351_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_351_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_SHIFT          0U
 #define LPDDR4__DENALI_CTL_351__RDLVL_DFI_PROMOTE_THRESHOLD_F1_WIDTH         16U
@@ -6276,8 +6276,8 @@
 #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__REG DENALI_CTL_351
 #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_351__RDLVL_GATE_NORM_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_352_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_352_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_352_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_MASK    0x0000FFFFU
 #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_SHIFT            0U
 #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1_WIDTH           16U
@@ -6285,13 +6285,13 @@
 #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_HIGH_THRESHOLD_F1
 
 #define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH				  16U
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1_WIDTH                  16U
 #define LPDDR4__RDLVL_GATE_TIMEOUT_F1__REG DENALI_CTL_352
 #define LPDDR4__RDLVL_GATE_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_352__RDLVL_GATE_TIMEOUT_F1
 
-#define LPDDR4__DENALI_CTL_353_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_353_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_353_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_SHIFT      0U
 #define LPDDR4__DENALI_CTL_353__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F1_WIDTH     16U
@@ -6304,25 +6304,25 @@
 #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_353
 #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_353__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_354_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_354_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_354_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__RDLVL_NORM_THRESHOLD_F2__REG DENALI_CTL_354
 #define LPDDR4__RDLVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_NORM_THRESHOLD_F2
 
 #define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_354
 #define LPDDR4__RDLVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_354__RDLVL_HIGH_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_355_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_355_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_355_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2_WIDTH                       16U
 #define LPDDR4__RDLVL_TIMEOUT_F2__REG DENALI_CTL_355
 #define LPDDR4__RDLVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_TIMEOUT_F2
 
@@ -6332,8 +6332,8 @@
 #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_355
 #define LPDDR4__RDLVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_355__RDLVL_SW_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_356_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_356_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_356_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
 #define LPDDR4__DENALI_CTL_356__RDLVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
@@ -6346,8 +6346,8 @@
 #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__REG DENALI_CTL_356
 #define LPDDR4__RDLVL_GATE_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_356__RDLVL_GATE_NORM_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_357_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_357_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_357_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_MASK    0x0000FFFFU
 #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_SHIFT            0U
 #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2_WIDTH           16U
@@ -6355,13 +6355,13 @@
 #define LPDDR4__RDLVL_GATE_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_HIGH_THRESHOLD_F2
 
 #define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_MASK           0xFFFF0000U
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH				  16U
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2_WIDTH                  16U
 #define LPDDR4__RDLVL_GATE_TIMEOUT_F2__REG DENALI_CTL_357
 #define LPDDR4__RDLVL_GATE_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_357__RDLVL_GATE_TIMEOUT_F2
 
-#define LPDDR4__DENALI_CTL_358_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_358_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_358_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_SHIFT      0U
 #define LPDDR4__DENALI_CTL_358__RDLVL_GATE_SW_PROMOTE_THRESHOLD_F2_WIDTH     16U
@@ -6374,177 +6374,177 @@
 #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_358
 #define LPDDR4__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_358__RDLVL_GATE_DFI_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_359_READ_MASK				             0x00000100U
-#define LPDDR4__DENALI_CTL_359_WRITE_MASK				            0x00000100U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK				       0x00000001U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT				               0U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH				               1U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR				               0U
-#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET				               0U
+#define LPDDR4__DENALI_CTL_359_READ_MASK                             0x00000100U
+#define LPDDR4__DENALI_CTL_359_WRITE_MASK                            0x00000100U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_MASK                       0x00000001U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_SHIFT                               0U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WIDTH                               1U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOCLR                               0U
+#define LPDDR4__DENALI_CTL_359__CALVL_REQ_WOSET                               0U
 #define LPDDR4__CALVL_REQ__REG DENALI_CTL_359
 #define LPDDR4__CALVL_REQ__FLD LPDDR4__DENALI_CTL_359__CALVL_REQ
 
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK				        0x00000100U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT								8U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH								1U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR								0U
-#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET								0U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_MASK                        0x00000100U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_359__CALVL_CS_WOSET                                0U
 #define LPDDR4__CALVL_CS__REG DENALI_CTL_359
 #define LPDDR4__CALVL_CS__FLD LPDDR4__DENALI_CTL_359__CALVL_CS
 
-#define LPDDR4__DENALI_CTL_360_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK				     0x000FFFFFU
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH				            20U
+#define LPDDR4__DENALI_CTL_360_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_MASK                     0x000FFFFFU
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_360__CALVL_PAT_0_WIDTH                            20U
 #define LPDDR4__CALVL_PAT_0__REG DENALI_CTL_360
 #define LPDDR4__CALVL_PAT_0__FLD LPDDR4__DENALI_CTL_360__CALVL_PAT_0
 
-#define LPDDR4__DENALI_CTL_361_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH				         20U
+#define LPDDR4__DENALI_CTL_361_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0_WIDTH                         20U
 #define LPDDR4__CALVL_BG_PAT_0__REG DENALI_CTL_361
 #define LPDDR4__CALVL_BG_PAT_0__FLD LPDDR4__DENALI_CTL_361__CALVL_BG_PAT_0
 
-#define LPDDR4__DENALI_CTL_362_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK				     0x000FFFFFU
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH				            20U
+#define LPDDR4__DENALI_CTL_362_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_MASK                     0x000FFFFFU
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_362__CALVL_PAT_1_WIDTH                            20U
 #define LPDDR4__CALVL_PAT_1__REG DENALI_CTL_362
 #define LPDDR4__CALVL_PAT_1__FLD LPDDR4__DENALI_CTL_362__CALVL_PAT_1
 
-#define LPDDR4__DENALI_CTL_363_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH				         20U
+#define LPDDR4__DENALI_CTL_363_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1_WIDTH                         20U
 #define LPDDR4__CALVL_BG_PAT_1__REG DENALI_CTL_363
 #define LPDDR4__CALVL_BG_PAT_1__FLD LPDDR4__DENALI_CTL_363__CALVL_BG_PAT_1
 
-#define LPDDR4__DENALI_CTL_364_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK				     0x000FFFFFU
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH				            20U
+#define LPDDR4__DENALI_CTL_364_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_MASK                     0x000FFFFFU
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_364__CALVL_PAT_2_WIDTH                            20U
 #define LPDDR4__CALVL_PAT_2__REG DENALI_CTL_364
 #define LPDDR4__CALVL_PAT_2__FLD LPDDR4__DENALI_CTL_364__CALVL_PAT_2
 
-#define LPDDR4__DENALI_CTL_365_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH				         20U
+#define LPDDR4__DENALI_CTL_365_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2_WIDTH                         20U
 #define LPDDR4__CALVL_BG_PAT_2__REG DENALI_CTL_365
 #define LPDDR4__CALVL_BG_PAT_2__FLD LPDDR4__DENALI_CTL_365__CALVL_BG_PAT_2
 
-#define LPDDR4__DENALI_CTL_366_READ_MASK				             0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366_WRITE_MASK				            0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK				     0x000FFFFFU
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT				             0U
-#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH				            20U
+#define LPDDR4__DENALI_CTL_366_READ_MASK                             0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366_WRITE_MASK                            0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_MASK                     0x000FFFFFU
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_SHIFT                             0U
+#define LPDDR4__DENALI_CTL_366__CALVL_PAT_3_WIDTH                            20U
 #define LPDDR4__CALVL_PAT_3__REG DENALI_CTL_366
 #define LPDDR4__CALVL_PAT_3__FLD LPDDR4__DENALI_CTL_366__CALVL_PAT_3
 
-#define LPDDR4__DENALI_CTL_367_READ_MASK				             0x010FFFFFU
-#define LPDDR4__DENALI_CTL_367_WRITE_MASK				            0x010FFFFFU
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK				  0x000FFFFFU
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH				         20U
+#define LPDDR4__DENALI_CTL_367_READ_MASK                             0x010FFFFFU
+#define LPDDR4__DENALI_CTL_367_WRITE_MASK                            0x010FFFFFU
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_MASK                  0x000FFFFFU
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3_WIDTH                         20U
 #define LPDDR4__CALVL_BG_PAT_3__REG DENALI_CTL_367
 #define LPDDR4__CALVL_BG_PAT_3__FLD LPDDR4__DENALI_CTL_367__CALVL_BG_PAT_3
 
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET				           0U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_367__MC_RESERVED30_WOSET                           0U
 #define LPDDR4__MC_RESERVED30__REG DENALI_CTL_367
 #define LPDDR4__MC_RESERVED30__FLD LPDDR4__DENALI_CTL_367__MC_RESERVED30
 
-#define LPDDR4__DENALI_CTL_368_READ_MASK				             0x0101030FU
-#define LPDDR4__DENALI_CTL_368_WRITE_MASK				            0x0101030FU
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_368_READ_MASK                             0x0101030FU
+#define LPDDR4__DENALI_CTL_368_WRITE_MASK                            0x0101030FU
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_368__MC_RESERVED31_WIDTH                           4U
 #define LPDDR4__MC_RESERVED31__REG DENALI_CTL_368
 #define LPDDR4__MC_RESERVED31__FLD LPDDR4__DENALI_CTL_368__MC_RESERVED31
 
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK				    0x00000300U
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH				            2U
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_MASK                    0x00000300U
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN_WIDTH                            2U
 #define LPDDR4__CALVL_SEQ_EN__REG DENALI_CTL_368
 #define LPDDR4__CALVL_SEQ_EN__FLD LPDDR4__DENALI_CTL_368__CALVL_SEQ_EN
 
 #define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_MASK              0x00010000U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET				      0U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE_WOSET                      0U
 #define LPDDR4__DFI_PHY_CALVL_MODE__REG DENALI_CTL_368
 #define LPDDR4__DFI_PHY_CALVL_MODE__FLD LPDDR4__DENALI_CTL_368__DFI_PHY_CALVL_MODE
 
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK				  0x01000000U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH				          1U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR				          0U
-#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET				          0U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_MASK                  0x01000000U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WIDTH                          1U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOCLR                          0U
+#define LPDDR4__DENALI_CTL_368__CALVL_PERIODIC_WOSET                          0U
 #define LPDDR4__CALVL_PERIODIC__REG DENALI_CTL_368
 #define LPDDR4__CALVL_PERIODIC__FLD LPDDR4__DENALI_CTL_368__CALVL_PERIODIC
 
-#define LPDDR4__DENALI_CTL_369_READ_MASK				             0x03010101U
-#define LPDDR4__DENALI_CTL_369_WRITE_MASK				            0x03010101U
+#define LPDDR4__DENALI_CTL_369_READ_MASK                             0x03010101U
+#define LPDDR4__DENALI_CTL_369_WRITE_MASK                            0x03010101U
 #define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_MASK              0x00000001U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH				      1U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR				      0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET				      0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WIDTH                      1U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOCLR                      0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT_WOSET                      0U
 #define LPDDR4__CALVL_ON_SREF_EXIT__REG DENALI_CTL_369
 #define LPDDR4__CALVL_ON_SREF_EXIT__FLD LPDDR4__DENALI_CTL_369__CALVL_ON_SREF_EXIT
 
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET				           0U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_369__CALVL_AREF_EN_WOSET                           0U
 #define LPDDR4__CALVL_AREF_EN__REG DENALI_CTL_369
 #define LPDDR4__CALVL_AREF_EN__FLD LPDDR4__DENALI_CTL_369__CALVL_AREF_EN
 
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK				    0x00010000U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT				           16U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET				            0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_MASK                    0x00010000U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_SHIFT                           16U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_369__CALVL_ROTATE_WOSET                            0U
 #define LPDDR4__CALVL_ROTATE__REG DENALI_CTL_369
 #define LPDDR4__CALVL_ROTATE__FLD LPDDR4__DENALI_CTL_369__CALVL_ROTATE
 
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK				    0x03000000U
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT				           24U
-#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH				            2U
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_MASK                    0x03000000U
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_SHIFT                           24U
+#define LPDDR4__DENALI_CTL_369__CALVL_CS_MAP_WIDTH                            2U
 #define LPDDR4__CALVL_CS_MAP__REG DENALI_CTL_369
 #define LPDDR4__CALVL_CS_MAP__FLD LPDDR4__DENALI_CTL_369__CALVL_CS_MAP
 
-#define LPDDR4__DENALI_CTL_370_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_370_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_370_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_370_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__CALVL_NORM_THRESHOLD_F0__REG DENALI_CTL_370
 #define LPDDR4__CALVL_NORM_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_NORM_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT				16U
-#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH				16U
+#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_SHIFT                16U
+#define LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0_WIDTH                16U
 #define LPDDR4__CALVL_HIGH_THRESHOLD_F0__REG DENALI_CTL_370
 #define LPDDR4__CALVL_HIGH_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_370__CALVL_HIGH_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_371_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_371_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_371_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0_WIDTH                       16U
 #define LPDDR4__CALVL_TIMEOUT_F0__REG DENALI_CTL_371
 #define LPDDR4__CALVL_TIMEOUT_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_TIMEOUT_F0
 
@@ -6554,8 +6554,8 @@
 #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__REG DENALI_CTL_371
 #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_371__CALVL_SW_PROMOTE_THRESHOLD_F0
 
-#define LPDDR4__DENALI_CTL_372_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_372_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_372_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_SHIFT          0U
 #define LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0_WIDTH         16U
@@ -6563,27 +6563,27 @@
 #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F0__FLD LPDDR4__DENALI_CTL_372__CALVL_DFI_PROMOTE_THRESHOLD_F0
 
 #define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT				16U
-#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_SHIFT                16U
+#define LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__CALVL_NORM_THRESHOLD_F1__REG DENALI_CTL_372
 #define LPDDR4__CALVL_NORM_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_372__CALVL_NORM_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_373_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_373_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_373_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH				16U
+#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1_WIDTH                16U
 #define LPDDR4__CALVL_HIGH_THRESHOLD_F1__REG DENALI_CTL_373
 #define LPDDR4__CALVL_HIGH_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_HIGH_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK				0xFFFF0000U
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_MASK                0xFFFF0000U
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1_WIDTH                       16U
 #define LPDDR4__CALVL_TIMEOUT_F1__REG DENALI_CTL_373
 #define LPDDR4__CALVL_TIMEOUT_F1__FLD LPDDR4__DENALI_CTL_373__CALVL_TIMEOUT_F1
 
-#define LPDDR4__DENALI_CTL_374_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_374_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_374_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_MASK   0x0000FFFFU
 #define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_SHIFT           0U
 #define LPDDR4__DENALI_CTL_374__CALVL_SW_PROMOTE_THRESHOLD_F1_WIDTH          16U
@@ -6596,25 +6596,25 @@
 #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__REG DENALI_CTL_374
 #define LPDDR4__CALVL_DFI_PROMOTE_THRESHOLD_F1__FLD LPDDR4__DENALI_CTL_374__CALVL_DFI_PROMOTE_THRESHOLD_F1
 
-#define LPDDR4__DENALI_CTL_375_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_375_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_375_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_MASK         0x0000FFFFU
-#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT				 0U
-#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_SHIFT                 0U
+#define LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__CALVL_NORM_THRESHOLD_F2__REG DENALI_CTL_375
 #define LPDDR4__CALVL_NORM_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_NORM_THRESHOLD_F2
 
 #define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_MASK         0xFFFF0000U
-#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT				16U
-#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH				16U
+#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_SHIFT                16U
+#define LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2_WIDTH                16U
 #define LPDDR4__CALVL_HIGH_THRESHOLD_F2__REG DENALI_CTL_375
 #define LPDDR4__CALVL_HIGH_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_375__CALVL_HIGH_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_376_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_376_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK				0x0000FFFFU
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH				       16U
+#define LPDDR4__DENALI_CTL_376_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_MASK                0x0000FFFFU
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2_WIDTH                       16U
 #define LPDDR4__CALVL_TIMEOUT_F2__REG DENALI_CTL_376
 #define LPDDR4__CALVL_TIMEOUT_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_TIMEOUT_F2
 
@@ -6624,8 +6624,8 @@
 #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__REG DENALI_CTL_376
 #define LPDDR4__CALVL_SW_PROMOTE_THRESHOLD_F2__FLD LPDDR4__DENALI_CTL_376__CALVL_SW_PROMOTE_THRESHOLD_F2
 
-#define LPDDR4__DENALI_CTL_377_READ_MASK				             0x0101FFFFU
-#define LPDDR4__DENALI_CTL_377_WRITE_MASK				            0x0101FFFFU
+#define LPDDR4__DENALI_CTL_377_READ_MASK                             0x0101FFFFU
+#define LPDDR4__DENALI_CTL_377_WRITE_MASK                            0x0101FFFFU
 #define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_MASK  0x0000FFFFU
 #define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_SHIFT          0U
 #define LPDDR4__DENALI_CTL_377__CALVL_DFI_PROMOTE_THRESHOLD_F2_WIDTH         16U
@@ -6648,39 +6648,39 @@
 #define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__REG DENALI_CTL_377
 #define LPDDR4__AXI0_FIXED_PORT_PRIORITY_ENABLE__FLD LPDDR4__DENALI_CTL_377__AXI0_FIXED_PORT_PRIORITY_ENABLE
 
-#define LPDDR4__DENALI_CTL_378_READ_MASK				             0x00000707U
-#define LPDDR4__DENALI_CTL_378_WRITE_MASK				            0x00000707U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK				 0x00000007U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH				         3U
+#define LPDDR4__DENALI_CTL_378_READ_MASK                             0x00000707U
+#define LPDDR4__DENALI_CTL_378_WRITE_MASK                            0x00000707U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY_WIDTH                         3U
 #define LPDDR4__AXI0_R_PRIORITY__REG DENALI_CTL_378
 #define LPDDR4__AXI0_R_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_R_PRIORITY
 
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK				 0x00000700U
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH				         3U
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_MASK                 0x00000700U
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY_WIDTH                         3U
 #define LPDDR4__AXI0_W_PRIORITY__REG DENALI_CTL_378
 #define LPDDR4__AXI0_W_PRIORITY__FLD LPDDR4__DENALI_CTL_378__AXI0_W_PRIORITY
 
-#define LPDDR4__DENALI_CTL_379_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_379_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_379_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_MASK          0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH				 32U
+#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0_WIDTH                 32U
 #define LPDDR4__PARITY_ERROR_ADDRESS_0__REG DENALI_CTL_379
 #define LPDDR4__PARITY_ERROR_ADDRESS_0__FLD LPDDR4__DENALI_CTL_379__PARITY_ERROR_ADDRESS_0
 
-#define LPDDR4__DENALI_CTL_380_READ_MASK				             0x1FFF3F07U
-#define LPDDR4__DENALI_CTL_380_WRITE_MASK				            0x1FFF3F07U
+#define LPDDR4__DENALI_CTL_380_READ_MASK                             0x1FFF3F07U
+#define LPDDR4__DENALI_CTL_380_WRITE_MASK                            0x1FFF3F07U
 #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_MASK          0x00000007U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT				  0U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH				  3U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_SHIFT                  0U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1_WIDTH                  3U
 #define LPDDR4__PARITY_ERROR_ADDRESS_1__REG DENALI_CTL_380
 #define LPDDR4__PARITY_ERROR_ADDRESS_1__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_ADDRESS_1
 
 #define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_MASK          0x00003F00U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT				  8U
-#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH				  6U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_SHIFT                  8U
+#define LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID_WIDTH                  6U
 #define LPDDR4__PARITY_ERROR_MASTER_ID__REG DENALI_CTL_380
 #define LPDDR4__PARITY_ERROR_MASTER_ID__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_MASTER_ID
 
@@ -6690,625 +6690,625 @@
 #define LPDDR4__PARITY_ERROR_BUS_CHANNEL__REG DENALI_CTL_380
 #define LPDDR4__PARITY_ERROR_BUS_CHANNEL__FLD LPDDR4__DENALI_CTL_380__PARITY_ERROR_BUS_CHANNEL
 
-#define LPDDR4__DENALI_CTL_381_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_381_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_381_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_SHIFT               0U
 #define LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0_WIDTH              32U
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_0__REG DENALI_CTL_381
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_0__FLD LPDDR4__DENALI_CTL_381__PARITY_ERROR_WRITE_DATA_0
 
-#define LPDDR4__DENALI_CTL_382_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_382_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_382_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_382_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_SHIFT               0U
 #define LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1_WIDTH              32U
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_1__REG DENALI_CTL_382
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_1__FLD LPDDR4__DENALI_CTL_382__PARITY_ERROR_WRITE_DATA_1
 
-#define LPDDR4__DENALI_CTL_383_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_383_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_383_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_383_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_SHIFT               0U
 #define LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2_WIDTH              32U
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_2__REG DENALI_CTL_383
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_2__FLD LPDDR4__DENALI_CTL_383__PARITY_ERROR_WRITE_DATA_2
 
-#define LPDDR4__DENALI_CTL_384_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_384_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_384_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_384_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_MASK       0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_SHIFT               0U
 #define LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3_WIDTH              32U
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_3__REG DENALI_CTL_384
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_3__FLD LPDDR4__DENALI_CTL_384__PARITY_ERROR_WRITE_DATA_3
 
-#define LPDDR4__DENALI_CTL_385_READ_MASK				             0x0103FFFFU
-#define LPDDR4__DENALI_CTL_385_WRITE_MASK				            0x0103FFFFU
+#define LPDDR4__DENALI_CTL_385_READ_MASK                             0x0103FFFFU
+#define LPDDR4__DENALI_CTL_385_WRITE_MASK                            0x0103FFFFU
 #define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_MASK 0x0000FFFFU
 #define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_SHIFT   0U
 #define LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR_WIDTH  16U
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__REG DENALI_CTL_385
 #define LPDDR4__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR__FLD LPDDR4__DENALI_CTL_385__PARITY_ERROR_WRITE_DATA_PARITY_VECTOR
 
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK				      0x00030000U
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT				             16U
-#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH				              2U
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_MASK                      0x00030000U
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_SHIFT                             16U
+#define LPDDR4__DENALI_CTL_385__CKE_STATUS_WIDTH                              2U
 #define LPDDR4__CKE_STATUS__REG DENALI_CTL_385
 #define LPDDR4__CKE_STATUS__FLD LPDDR4__DENALI_CTL_385__CKE_STATUS
 
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK				   0x01000000U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET				           0U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_MASK                   0x01000000U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_385__MEM_RST_VALID_WOSET                           0U
 #define LPDDR4__MEM_RST_VALID__REG DENALI_CTL_385
 #define LPDDR4__MEM_RST_VALID__FLD LPDDR4__DENALI_CTL_385__MEM_RST_VALID
 
-#define LPDDR4__DENALI_CTL_386_READ_MASK				             0x7FFFFFFFU
-#define LPDDR4__DENALI_CTL_386_WRITE_MASK				            0x7FFFFFFFU
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK				   0x0000FFFFU
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH				          16U
+#define LPDDR4__DENALI_CTL_386_READ_MASK                             0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_386_WRITE_MASK                            0x7FFFFFFFU
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_MASK                   0x0000FFFFU
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_DELAY_WIDTH                          16U
 #define LPDDR4__DLL_RST_DELAY__REG DENALI_CTL_386
 #define LPDDR4__DLL_RST_DELAY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_DELAY
 
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK				 0x00FF0000U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH				         8U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_MASK                 0x00FF0000U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY_WIDTH                         8U
 #define LPDDR4__DLL_RST_ADJ_DLY__REG DENALI_CTL_386
 #define LPDDR4__DLL_RST_ADJ_DLY__FLD LPDDR4__DENALI_CTL_386__DLL_RST_ADJ_DLY
 
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK				  0x7F000000U
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT				         24U
-#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH				          7U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_MASK                  0x7F000000U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_SHIFT                         24U
+#define LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT_WIDTH                          7U
 #define LPDDR4__TDFI_PHY_WRLAT__REG DENALI_CTL_386
 #define LPDDR4__TDFI_PHY_WRLAT__FLD LPDDR4__DENALI_CTL_386__TDFI_PHY_WRLAT
 
-#define LPDDR4__DENALI_CTL_387_READ_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_387_WRITE_MASK				            0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_387_READ_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_387_WRITE_MASK                            0x7F7F7F7FU
 #define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_MASK             0x0000007FU
-#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH				     7U
+#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS_WIDTH                     7U
 #define LPDDR4__UPDATE_ERROR_STATUS__REG DENALI_CTL_387
 #define LPDDR4__UPDATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_387__UPDATE_ERROR_STATUS
 
 #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_MASK               0x00007F00U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT				       8U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH				       7U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_SHIFT                       8U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0_WIDTH                       7U
 #define LPDDR4__TDFI_PHY_RDLAT_F0__REG DENALI_CTL_387
 #define LPDDR4__TDFI_PHY_RDLAT_F0__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F0
 
 #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_MASK               0x007F0000U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT				      16U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH				       7U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_SHIFT                      16U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1_WIDTH                       7U
 #define LPDDR4__TDFI_PHY_RDLAT_F1__REG DENALI_CTL_387
 #define LPDDR4__TDFI_PHY_RDLAT_F1__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F1
 
 #define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_MASK               0x7F000000U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH				       7U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2_WIDTH                       7U
 #define LPDDR4__TDFI_PHY_RDLAT_F2__REG DENALI_CTL_387
 #define LPDDR4__TDFI_PHY_RDLAT_F2__FLD LPDDR4__DENALI_CTL_387__TDFI_PHY_RDLAT_F2
 
-#define LPDDR4__DENALI_CTL_388_READ_MASK				             0x00FF037FU
-#define LPDDR4__DENALI_CTL_388_WRITE_MASK				            0x00FF037FU
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK				  0x0000007FU
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH				          7U
+#define LPDDR4__DENALI_CTL_388_READ_MASK                             0x00FF037FU
+#define LPDDR4__DENALI_CTL_388_WRITE_MASK                            0x00FF037FU
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_MASK                  0x0000007FU
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN_WIDTH                          7U
 #define LPDDR4__TDFI_RDDATA_EN__REG DENALI_CTL_388
 #define LPDDR4__TDFI_RDDATA_EN__FLD LPDDR4__DENALI_CTL_388__TDFI_RDDATA_EN
 
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK				0x00000300U
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT				        8U
-#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH				        2U
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_MASK                0x00000300U
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_SHIFT                        8U
+#define LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE_WIDTH                        2U
 #define LPDDR4__DRAM_CLK_DISABLE__REG DENALI_CTL_388
 #define LPDDR4__DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_388__DRAM_CLK_DISABLE
 
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK				0x00FF0000U
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT				       16U
-#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH				        8U
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_MASK                0x00FF0000U
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_SHIFT                       16U
+#define LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN_WIDTH                        8U
 #define LPDDR4__TDFI_CTRLUPD_MIN__REG DENALI_CTL_388
 #define LPDDR4__TDFI_CTRLUPD_MIN__FLD LPDDR4__DENALI_CTL_388__TDFI_CTRLUPD_MIN
 
-#define LPDDR4__DENALI_CTL_389_READ_MASK				             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_389_WRITE_MASK				            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_389_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_389_WRITE_MASK                            0x001FFFFFU
 #define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_MASK             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH				    21U
+#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0_WIDTH                    21U
 #define LPDDR4__TDFI_CTRLUPD_MAX_F0__REG DENALI_CTL_389
 #define LPDDR4__TDFI_CTRLUPD_MAX_F0__FLD LPDDR4__DENALI_CTL_389__TDFI_CTRLUPD_MAX_F0
 
-#define LPDDR4__DENALI_CTL_390_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_390_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_390_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_390_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE0_F0__REG DENALI_CTL_390
 #define LPDDR4__TDFI_PHYUPD_TYPE0_F0__FLD LPDDR4__DENALI_CTL_390__TDFI_PHYUPD_TYPE0_F0
 
-#define LPDDR4__DENALI_CTL_391_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_391_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_391_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE1_F0__REG DENALI_CTL_391
 #define LPDDR4__TDFI_PHYUPD_TYPE1_F0__FLD LPDDR4__DENALI_CTL_391__TDFI_PHYUPD_TYPE1_F0
 
-#define LPDDR4__DENALI_CTL_392_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_392_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_392_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_392_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE2_F0__REG DENALI_CTL_392
 #define LPDDR4__TDFI_PHYUPD_TYPE2_F0__FLD LPDDR4__DENALI_CTL_392__TDFI_PHYUPD_TYPE2_F0
 
-#define LPDDR4__DENALI_CTL_393_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_393_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_393_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_393_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE3_F0__REG DENALI_CTL_393
 #define LPDDR4__TDFI_PHYUPD_TYPE3_F0__FLD LPDDR4__DENALI_CTL_393__TDFI_PHYUPD_TYPE3_F0
 
-#define LPDDR4__DENALI_CTL_394_READ_MASK				             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_394_WRITE_MASK				            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_394_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_394_WRITE_MASK                            0x007FFFFFU
 #define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_MASK             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH				    23U
+#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0_WIDTH                    23U
 #define LPDDR4__TDFI_PHYUPD_RESP_F0__REG DENALI_CTL_394
 #define LPDDR4__TDFI_PHYUPD_RESP_F0__FLD LPDDR4__DENALI_CTL_394__TDFI_PHYUPD_RESP_F0
 
-#define LPDDR4__DENALI_CTL_395_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_395_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_395_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT				0U
+#define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_SHIFT                0U
 #define LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0_WIDTH               32U
 #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__REG DENALI_CTL_395
 #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F0__FLD LPDDR4__DENALI_CTL_395__TDFI_CTRLUPD_INTERVAL_F0
 
-#define LPDDR4__DENALI_CTL_396_READ_MASK				             0x00007F7FU
-#define LPDDR4__DENALI_CTL_396_WRITE_MASK				            0x00007F7FU
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_396_READ_MASK                             0x00007F7FU
+#define LPDDR4__DENALI_CTL_396_WRITE_MASK                            0x00007F7FU
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0_WIDTH                            7U
 #define LPDDR4__RDLAT_ADJ_F0__REG DENALI_CTL_396
 #define LPDDR4__RDLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__RDLAT_ADJ_F0
 
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK				    0x00007F00U
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_MASK                    0x00007F00U
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0_WIDTH                            7U
 #define LPDDR4__WRLAT_ADJ_F0__REG DENALI_CTL_396
 #define LPDDR4__WRLAT_ADJ_F0__FLD LPDDR4__DENALI_CTL_396__WRLAT_ADJ_F0
 
-#define LPDDR4__DENALI_CTL_397_READ_MASK				             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_397_WRITE_MASK				            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_397_WRITE_MASK                            0x001FFFFFU
 #define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_MASK             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH				    21U
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1_WIDTH                    21U
 #define LPDDR4__TDFI_CTRLUPD_MAX_F1__REG DENALI_CTL_397
 #define LPDDR4__TDFI_CTRLUPD_MAX_F1__FLD LPDDR4__DENALI_CTL_397__TDFI_CTRLUPD_MAX_F1
 
-#define LPDDR4__DENALI_CTL_398_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_398_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_398_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE0_F1__REG DENALI_CTL_398
 #define LPDDR4__TDFI_PHYUPD_TYPE0_F1__FLD LPDDR4__DENALI_CTL_398__TDFI_PHYUPD_TYPE0_F1
 
-#define LPDDR4__DENALI_CTL_399_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_399_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_399_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE1_F1__REG DENALI_CTL_399
 #define LPDDR4__TDFI_PHYUPD_TYPE1_F1__FLD LPDDR4__DENALI_CTL_399__TDFI_PHYUPD_TYPE1_F1
 
-#define LPDDR4__DENALI_CTL_400_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_400_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_400_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE2_F1__REG DENALI_CTL_400
 #define LPDDR4__TDFI_PHYUPD_TYPE2_F1__FLD LPDDR4__DENALI_CTL_400__TDFI_PHYUPD_TYPE2_F1
 
-#define LPDDR4__DENALI_CTL_401_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_401_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_401_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE3_F1__REG DENALI_CTL_401
 #define LPDDR4__TDFI_PHYUPD_TYPE3_F1__FLD LPDDR4__DENALI_CTL_401__TDFI_PHYUPD_TYPE3_F1
 
-#define LPDDR4__DENALI_CTL_402_READ_MASK				             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_402_WRITE_MASK				            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_402_WRITE_MASK                            0x007FFFFFU
 #define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_MASK             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH				    23U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1_WIDTH                    23U
 #define LPDDR4__TDFI_PHYUPD_RESP_F1__REG DENALI_CTL_402
 #define LPDDR4__TDFI_PHYUPD_RESP_F1__FLD LPDDR4__DENALI_CTL_402__TDFI_PHYUPD_RESP_F1
 
-#define LPDDR4__DENALI_CTL_403_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_403_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_403_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT				0U
+#define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_SHIFT                0U
 #define LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1_WIDTH               32U
 #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__REG DENALI_CTL_403
 #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F1__FLD LPDDR4__DENALI_CTL_403__TDFI_CTRLUPD_INTERVAL_F1
 
-#define LPDDR4__DENALI_CTL_404_READ_MASK				             0x00007F7FU
-#define LPDDR4__DENALI_CTL_404_WRITE_MASK				            0x00007F7FU
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_404_READ_MASK                             0x00007F7FU
+#define LPDDR4__DENALI_CTL_404_WRITE_MASK                            0x00007F7FU
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1_WIDTH                            7U
 #define LPDDR4__RDLAT_ADJ_F1__REG DENALI_CTL_404
 #define LPDDR4__RDLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__RDLAT_ADJ_F1
 
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK				    0x00007F00U
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_MASK                    0x00007F00U
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1_WIDTH                            7U
 #define LPDDR4__WRLAT_ADJ_F1__REG DENALI_CTL_404
 #define LPDDR4__WRLAT_ADJ_F1__FLD LPDDR4__DENALI_CTL_404__WRLAT_ADJ_F1
 
-#define LPDDR4__DENALI_CTL_405_READ_MASK				             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_405_WRITE_MASK				            0x001FFFFFU
+#define LPDDR4__DENALI_CTL_405_READ_MASK                             0x001FFFFFU
+#define LPDDR4__DENALI_CTL_405_WRITE_MASK                            0x001FFFFFU
 #define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_MASK             0x001FFFFFU
-#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH				    21U
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2_WIDTH                    21U
 #define LPDDR4__TDFI_CTRLUPD_MAX_F2__REG DENALI_CTL_405
 #define LPDDR4__TDFI_CTRLUPD_MAX_F2__FLD LPDDR4__DENALI_CTL_405__TDFI_CTRLUPD_MAX_F2
 
-#define LPDDR4__DENALI_CTL_406_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_406_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_406_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE0_F2__REG DENALI_CTL_406
 #define LPDDR4__TDFI_PHYUPD_TYPE0_F2__FLD LPDDR4__DENALI_CTL_406__TDFI_PHYUPD_TYPE0_F2
 
-#define LPDDR4__DENALI_CTL_407_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_407_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_407_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE1_F2__REG DENALI_CTL_407
 #define LPDDR4__TDFI_PHYUPD_TYPE1_F2__FLD LPDDR4__DENALI_CTL_407__TDFI_PHYUPD_TYPE1_F2
 
-#define LPDDR4__DENALI_CTL_408_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_408_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_408_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE2_F2__REG DENALI_CTL_408
 #define LPDDR4__TDFI_PHYUPD_TYPE2_F2__FLD LPDDR4__DENALI_CTL_408__TDFI_PHYUPD_TYPE2_F2
 
-#define LPDDR4__DENALI_CTL_409_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_409_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_409_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_MASK            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH				   32U
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2_WIDTH                   32U
 #define LPDDR4__TDFI_PHYUPD_TYPE3_F2__REG DENALI_CTL_409
 #define LPDDR4__TDFI_PHYUPD_TYPE3_F2__FLD LPDDR4__DENALI_CTL_409__TDFI_PHYUPD_TYPE3_F2
 
-#define LPDDR4__DENALI_CTL_410_READ_MASK				             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_410_WRITE_MASK				            0x007FFFFFU
+#define LPDDR4__DENALI_CTL_410_READ_MASK                             0x007FFFFFU
+#define LPDDR4__DENALI_CTL_410_WRITE_MASK                            0x007FFFFFU
 #define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_MASK             0x007FFFFFU
-#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT				     0U
-#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH				    23U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_SHIFT                     0U
+#define LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2_WIDTH                    23U
 #define LPDDR4__TDFI_PHYUPD_RESP_F2__REG DENALI_CTL_410
 #define LPDDR4__TDFI_PHYUPD_RESP_F2__FLD LPDDR4__DENALI_CTL_410__TDFI_PHYUPD_RESP_F2
 
-#define LPDDR4__DENALI_CTL_411_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_411_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_411_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_MASK        0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT				0U
+#define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_SHIFT                0U
 #define LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2_WIDTH               32U
 #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__REG DENALI_CTL_411
 #define LPDDR4__TDFI_CTRLUPD_INTERVAL_F2__FLD LPDDR4__DENALI_CTL_411__TDFI_CTRLUPD_INTERVAL_F2
 
-#define LPDDR4__DENALI_CTL_412_READ_MASK				             0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_412_WRITE_MASK				            0x0F0F7F7FU
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK				    0x0000007FU
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT				            0U
-#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_412_READ_MASK                             0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_412_WRITE_MASK                            0x0F0F7F7FU
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_MASK                    0x0000007FU
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_SHIFT                            0U
+#define LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2_WIDTH                            7U
 #define LPDDR4__RDLAT_ADJ_F2__REG DENALI_CTL_412
 #define LPDDR4__RDLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__RDLAT_ADJ_F2
 
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK				    0x00007F00U
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH				            7U
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_MASK                    0x00007F00U
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2_WIDTH                            7U
 #define LPDDR4__WRLAT_ADJ_F2__REG DENALI_CTL_412
 #define LPDDR4__WRLAT_ADJ_F2__FLD LPDDR4__DENALI_CTL_412__WRLAT_ADJ_F2
 
 #define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_MASK              0x000F0000U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH				      4U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0_WIDTH                      4U
 #define LPDDR4__TDFI_CTRL_DELAY_F0__REG DENALI_CTL_412
 #define LPDDR4__TDFI_CTRL_DELAY_F0__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F0
 
 #define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_MASK              0x0F000000U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH				      4U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1_WIDTH                      4U
 #define LPDDR4__TDFI_CTRL_DELAY_F1__REG DENALI_CTL_412
 #define LPDDR4__TDFI_CTRL_DELAY_F1__FLD LPDDR4__DENALI_CTL_412__TDFI_CTRL_DELAY_F1
 
-#define LPDDR4__DENALI_CTL_413_READ_MASK				             0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_413_WRITE_MASK				            0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_413_READ_MASK                             0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_413_WRITE_MASK                            0xFF0F0F0FU
 #define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_MASK              0x0000000FU
-#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH				      4U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2_WIDTH                      4U
 #define LPDDR4__TDFI_CTRL_DELAY_F2__REG DENALI_CTL_413
 #define LPDDR4__TDFI_CTRL_DELAY_F2__FLD LPDDR4__DENALI_CTL_413__TDFI_CTRL_DELAY_F2
 
 #define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_MASK           0x00000F00U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT				   8U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH				   4U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_SHIFT                   8U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE_WIDTH                   4U
 #define LPDDR4__TDFI_DRAM_CLK_DISABLE__REG DENALI_CTL_413
 #define LPDDR4__TDFI_DRAM_CLK_DISABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_DISABLE
 
 #define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_MASK            0x000F0000U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT				   16U
-#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH				    4U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_SHIFT                   16U
+#define LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE_WIDTH                    4U
 #define LPDDR4__TDFI_DRAM_CLK_ENABLE__REG DENALI_CTL_413
 #define LPDDR4__TDFI_DRAM_CLK_ENABLE__FLD LPDDR4__DENALI_CTL_413__TDFI_DRAM_CLK_ENABLE
 
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK				   0xFF000000U
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_MASK                   0xFF000000U
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN_WIDTH                           8U
 #define LPDDR4__TDFI_WRLVL_EN__REG DENALI_CTL_413
 #define LPDDR4__TDFI_WRLVL_EN__FLD LPDDR4__DENALI_CTL_413__TDFI_WRLVL_EN
 
-#define LPDDR4__DENALI_CTL_414_READ_MASK				             0x000003FFU
-#define LPDDR4__DENALI_CTL_414_WRITE_MASK				            0x000003FFU
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK				   0x000003FFU
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH				          10U
+#define LPDDR4__DENALI_CTL_414_READ_MASK                             0x000003FFU
+#define LPDDR4__DENALI_CTL_414_WRITE_MASK                            0x000003FFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_MASK                   0x000003FFU
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW_WIDTH                          10U
 #define LPDDR4__TDFI_WRLVL_WW__REG DENALI_CTL_414
 #define LPDDR4__TDFI_WRLVL_WW__FLD LPDDR4__DENALI_CTL_414__TDFI_WRLVL_WW
 
-#define LPDDR4__DENALI_CTL_415_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_415_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP_WIDTH                        32U
 #define LPDDR4__TDFI_WRLVL_RESP__REG DENALI_CTL_415
 #define LPDDR4__TDFI_WRLVL_RESP__FLD LPDDR4__DENALI_CTL_415__TDFI_WRLVL_RESP
 
-#define LPDDR4__DENALI_CTL_416_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK				  0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH				         32U
+#define LPDDR4__DENALI_CTL_416_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX_WIDTH                         32U
 #define LPDDR4__TDFI_WRLVL_MAX__REG DENALI_CTL_416
 #define LPDDR4__TDFI_WRLVL_MAX__FLD LPDDR4__DENALI_CTL_416__TDFI_WRLVL_MAX
 
-#define LPDDR4__DENALI_CTL_417_READ_MASK				             0x0003FFFFU
-#define LPDDR4__DENALI_CTL_417_WRITE_MASK				            0x0003FFFFU
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK				   0x000000FFU
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_417_READ_MASK                             0x0003FFFFU
+#define LPDDR4__DENALI_CTL_417_WRITE_MASK                            0x0003FFFFU
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_MASK                   0x000000FFU
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN_WIDTH                           8U
 #define LPDDR4__TDFI_RDLVL_EN__REG DENALI_CTL_417
 #define LPDDR4__TDFI_RDLVL_EN__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_EN
 
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK				   0x0003FF00U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH				          10U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_MASK                   0x0003FF00U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR_WIDTH                          10U
 #define LPDDR4__TDFI_RDLVL_RR__REG DENALI_CTL_417
 #define LPDDR4__TDFI_RDLVL_RR__FLD LPDDR4__DENALI_CTL_417__TDFI_RDLVL_RR
 
-#define LPDDR4__DENALI_CTL_418_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_418_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP_WIDTH                        32U
 #define LPDDR4__TDFI_RDLVL_RESP__REG DENALI_CTL_418
 #define LPDDR4__TDFI_RDLVL_RESP__FLD LPDDR4__DENALI_CTL_418__TDFI_RDLVL_RESP
 
-#define LPDDR4__DENALI_CTL_419_READ_MASK				             0x000101FFU
-#define LPDDR4__DENALI_CTL_419_WRITE_MASK				            0x000101FFU
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK				 0x000000FFU
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH				         8U
+#define LPDDR4__DENALI_CTL_419_READ_MASK                             0x000101FFU
+#define LPDDR4__DENALI_CTL_419_WRITE_MASK                            0x000101FFU
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_MASK                 0x000000FFU
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK_WIDTH                         8U
 #define LPDDR4__RDLVL_RESP_MASK__REG DENALI_CTL_419
 #define LPDDR4__RDLVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_419__RDLVL_RESP_MASK
 
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK				        0x00000100U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT								8U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH								1U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR								0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET								0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_MASK                        0x00000100U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_EN_WOSET                                0U
 #define LPDDR4__RDLVL_EN__REG DENALI_CTL_419
 #define LPDDR4__RDLVL_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_EN
 
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK				   0x00010000U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET				           0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_MASK                   0x00010000U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN_WOSET                           0U
 #define LPDDR4__RDLVL_GATE_EN__REG DENALI_CTL_419
 #define LPDDR4__RDLVL_GATE_EN__FLD LPDDR4__DENALI_CTL_419__RDLVL_GATE_EN
 
-#define LPDDR4__DENALI_CTL_420_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK				  0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH				         32U
+#define LPDDR4__DENALI_CTL_420_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX_WIDTH                         32U
 #define LPDDR4__TDFI_RDLVL_MAX__REG DENALI_CTL_420
 #define LPDDR4__TDFI_RDLVL_MAX__FLD LPDDR4__DENALI_CTL_420__TDFI_RDLVL_MAX
 
-#define LPDDR4__DENALI_CTL_421_READ_MASK				             0x00FF0707U
-#define LPDDR4__DENALI_CTL_421_WRITE_MASK				            0x00FF0707U
+#define LPDDR4__DENALI_CTL_421_READ_MASK                             0x00FF0707U
+#define LPDDR4__DENALI_CTL_421_WRITE_MASK                            0x00FF0707U
 #define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_MASK              0x00000007U
-#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH				      3U
+#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS_WIDTH                      3U
 #define LPDDR4__RDLVL_ERROR_STATUS__REG DENALI_CTL_421
 #define LPDDR4__RDLVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_ERROR_STATUS
 
 #define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_MASK         0x00000700U
-#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT				 8U
-#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH				 3U
+#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS_WIDTH                 3U
 #define LPDDR4__RDLVL_GATE_ERROR_STATUS__REG DENALI_CTL_421
 #define LPDDR4__RDLVL_GATE_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_421__RDLVL_GATE_ERROR_STATUS
 
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK				   0x00FF0000U
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH				           8U
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_MASK                   0x00FF0000U
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN_WIDTH                           8U
 #define LPDDR4__TDFI_CALVL_EN__REG DENALI_CTL_421
 #define LPDDR4__TDFI_CALVL_EN__FLD LPDDR4__DENALI_CTL_421__TDFI_CALVL_EN
 
-#define LPDDR4__DENALI_CTL_422_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_422_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH				       10U
+#define LPDDR4__DENALI_CTL_422_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_422_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0_WIDTH                       10U
 #define LPDDR4__TDFI_CALVL_CC_F0__REG DENALI_CTL_422
 #define LPDDR4__TDFI_CALVL_CC_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CC_F0
 
 #define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_MASK           0x03FF0000U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH				  10U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0_WIDTH                  10U
 #define LPDDR4__TDFI_CALVL_CAPTURE_F0__REG DENALI_CTL_422
 #define LPDDR4__TDFI_CALVL_CAPTURE_F0__FLD LPDDR4__DENALI_CTL_422__TDFI_CALVL_CAPTURE_F0
 
-#define LPDDR4__DENALI_CTL_423_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_423_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH				       10U
+#define LPDDR4__DENALI_CTL_423_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_423_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1_WIDTH                       10U
 #define LPDDR4__TDFI_CALVL_CC_F1__REG DENALI_CTL_423
 #define LPDDR4__TDFI_CALVL_CC_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CC_F1
 
 #define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_MASK           0x03FF0000U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH				  10U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1_WIDTH                  10U
 #define LPDDR4__TDFI_CALVL_CAPTURE_F1__REG DENALI_CTL_423
 #define LPDDR4__TDFI_CALVL_CAPTURE_F1__FLD LPDDR4__DENALI_CTL_423__TDFI_CALVL_CAPTURE_F1
 
-#define LPDDR4__DENALI_CTL_424_READ_MASK				             0x03FF03FFU
-#define LPDDR4__DENALI_CTL_424_WRITE_MASK				            0x03FF03FFU
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK				0x000003FFU
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT				        0U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH				       10U
+#define LPDDR4__DENALI_CTL_424_READ_MASK                             0x03FF03FFU
+#define LPDDR4__DENALI_CTL_424_WRITE_MASK                            0x03FF03FFU
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_MASK                0x000003FFU
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_SHIFT                        0U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2_WIDTH                       10U
 #define LPDDR4__TDFI_CALVL_CC_F2__REG DENALI_CTL_424
 #define LPDDR4__TDFI_CALVL_CC_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CC_F2
 
 #define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_MASK           0x03FF0000U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT				  16U
-#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH				  10U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_SHIFT                  16U
+#define LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2_WIDTH                  10U
 #define LPDDR4__TDFI_CALVL_CAPTURE_F2__REG DENALI_CTL_424
 #define LPDDR4__TDFI_CALVL_CAPTURE_F2__FLD LPDDR4__DENALI_CTL_424__TDFI_CALVL_CAPTURE_F2
 
-#define LPDDR4__DENALI_CTL_425_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_425_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP_WIDTH                        32U
 #define LPDDR4__TDFI_CALVL_RESP__REG DENALI_CTL_425
 #define LPDDR4__TDFI_CALVL_RESP__FLD LPDDR4__DENALI_CTL_425__TDFI_CALVL_RESP
 
-#define LPDDR4__DENALI_CTL_426_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK				  0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT				          0U
-#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH				         32U
+#define LPDDR4__DENALI_CTL_426_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_MASK                  0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_SHIFT                          0U
+#define LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX_WIDTH                         32U
 #define LPDDR4__TDFI_CALVL_MAX__REG DENALI_CTL_426
 #define LPDDR4__TDFI_CALVL_MAX__FLD LPDDR4__DENALI_CTL_426__TDFI_CALVL_MAX
 
-#define LPDDR4__DENALI_CTL_427_READ_MASK				             0x070F0101U
-#define LPDDR4__DENALI_CTL_427_WRITE_MASK				            0x070F0101U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK				 0x00000001U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH				         1U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR				         0U
-#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET				         0U
+#define LPDDR4__DENALI_CTL_427_READ_MASK                             0x070F0101U
+#define LPDDR4__DENALI_CTL_427_WRITE_MASK                            0x070F0101U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_MASK                 0x00000001U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WIDTH                         1U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOCLR                         0U
+#define LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK_WOSET                         0U
 #define LPDDR4__CALVL_RESP_MASK__REG DENALI_CTL_427
 #define LPDDR4__CALVL_RESP_MASK__FLD LPDDR4__DENALI_CTL_427__CALVL_RESP_MASK
 
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK				        0x00000100U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT								8U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH								1U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR								0U
-#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET								0U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_MASK                        0x00000100U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_SHIFT                                8U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WIDTH                                1U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOCLR                                0U
+#define LPDDR4__DENALI_CTL_427__CALVL_EN_WOSET                                0U
 #define LPDDR4__CALVL_EN__REG DENALI_CTL_427
 #define LPDDR4__CALVL_EN__FLD LPDDR4__DENALI_CTL_427__CALVL_EN
 
 #define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_MASK              0x000F0000U
-#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT				     16U
-#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH				      4U
+#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_SHIFT                     16U
+#define LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS_WIDTH                      4U
 #define LPDDR4__CALVL_ERROR_STATUS__REG DENALI_CTL_427
 #define LPDDR4__CALVL_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_427__CALVL_ERROR_STATUS
 
 #define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_MASK              0x07000000U
-#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT				     24U
-#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH				      3U
+#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_SHIFT                     24U
+#define LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0_WIDTH                      3U
 #define LPDDR4__TDFI_PHY_WRDATA_F0__REG DENALI_CTL_427
 #define LPDDR4__TDFI_PHY_WRDATA_F0__FLD LPDDR4__DENALI_CTL_427__TDFI_PHY_WRDATA_F0
 
-#define LPDDR4__DENALI_CTL_428_READ_MASK				             0x7F7F0707U
-#define LPDDR4__DENALI_CTL_428_WRITE_MASK				            0x7F7F0707U
+#define LPDDR4__DENALI_CTL_428_READ_MASK                             0x7F7F0707U
+#define LPDDR4__DENALI_CTL_428_WRITE_MASK                            0x7F7F0707U
 #define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_MASK              0x00000007U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT				      0U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH				      3U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_SHIFT                      0U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1_WIDTH                      3U
 #define LPDDR4__TDFI_PHY_WRDATA_F1__REG DENALI_CTL_428
 #define LPDDR4__TDFI_PHY_WRDATA_F1__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F1
 
 #define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_MASK              0x00000700U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT				      8U
-#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH				      3U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_SHIFT                      8U
+#define LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2_WIDTH                      3U
 #define LPDDR4__TDFI_PHY_WRDATA_F2__REG DENALI_CTL_428
 #define LPDDR4__TDFI_PHY_WRDATA_F2__FLD LPDDR4__DENALI_CTL_428__TDFI_PHY_WRDATA_F2
 
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK				 0x007F0000U
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH				         7U
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_MASK                 0x007F0000U
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0_WIDTH                         7U
 #define LPDDR4__TDFI_RDCSLAT_F0__REG DENALI_CTL_428
 #define LPDDR4__TDFI_RDCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_RDCSLAT_F0
 
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK				 0x7F000000U
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH				         7U
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_MASK                 0x7F000000U
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0_WIDTH                         7U
 #define LPDDR4__TDFI_WRCSLAT_F0__REG DENALI_CTL_428
 #define LPDDR4__TDFI_WRCSLAT_F0__FLD LPDDR4__DENALI_CTL_428__TDFI_WRCSLAT_F0
 
-#define LPDDR4__DENALI_CTL_429_READ_MASK				             0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_429_WRITE_MASK				            0x7F7F7F7FU
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK				 0x0000007FU
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH				         7U
+#define LPDDR4__DENALI_CTL_429_READ_MASK                             0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_429_WRITE_MASK                            0x7F7F7F7FU
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_MASK                 0x0000007FU
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1_WIDTH                         7U
 #define LPDDR4__TDFI_RDCSLAT_F1__REG DENALI_CTL_429
 #define LPDDR4__TDFI_RDCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F1
 
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK				 0x00007F00U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT				         8U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH				         7U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_MASK                 0x00007F00U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_SHIFT                         8U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1_WIDTH                         7U
 #define LPDDR4__TDFI_WRCSLAT_F1__REG DENALI_CTL_429
 #define LPDDR4__TDFI_WRCSLAT_F1__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F1
 
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK				 0x007F0000U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT				        16U
-#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH				         7U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_MASK                 0x007F0000U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_SHIFT                        16U
+#define LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2_WIDTH                         7U
 #define LPDDR4__TDFI_RDCSLAT_F2__REG DENALI_CTL_429
 #define LPDDR4__TDFI_RDCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_RDCSLAT_F2
 
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK				 0x7F000000U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT				        24U
-#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH				         7U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_MASK                 0x7F000000U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_SHIFT                        24U
+#define LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2_WIDTH                         7U
 #define LPDDR4__TDFI_WRCSLAT_F2__REG DENALI_CTL_429
 #define LPDDR4__TDFI_WRCSLAT_F2__FLD LPDDR4__DENALI_CTL_429__TDFI_WRCSLAT_F2
 
-#define LPDDR4__DENALI_CTL_430_READ_MASK				             0x010101FFU
-#define LPDDR4__DENALI_CTL_430_WRITE_MASK				            0x010101FFU
+#define LPDDR4__DENALI_CTL_430_READ_MASK                             0x010101FFU
+#define LPDDR4__DENALI_CTL_430_WRITE_MASK                            0x010101FFU
 #define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_MASK               0x000000FFU
-#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH				       8U
+#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY_WIDTH                       8U
 #define LPDDR4__TDFI_WRDATA_DELAY__REG DENALI_CTL_430
 #define LPDDR4__TDFI_WRDATA_DELAY__FLD LPDDR4__DENALI_CTL_430__TDFI_WRDATA_DELAY
 
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK				    0x00000100U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT				            8U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH				            1U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR				            0U
-#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET				            0U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_MASK                    0x00000100U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_SHIFT                            8U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WIDTH                            1U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOCLR                            0U
+#define LPDDR4__DENALI_CTL_430__EN_1T_TIMING_WOSET                            0U
 #define LPDDR4__EN_1T_TIMING__REG DENALI_CTL_430
 #define LPDDR4__EN_1T_TIMING__FLD LPDDR4__DENALI_CTL_430__EN_1T_TIMING
 
@@ -7320,237 +7320,237 @@
 #define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__REG DENALI_CTL_430
 #define LPDDR4__DISABLE_MEMORY_MASKED_WRITE__FLD LPDDR4__DENALI_CTL_430__DISABLE_MEMORY_MASKED_WRITE
 
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK				0x01000000U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT				       24U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH				        1U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR				        0U
-#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET				        0U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_MASK                0x01000000U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_SHIFT                       24U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WIDTH                        1U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOCLR                        0U
+#define LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE_WOSET                        0U
 #define LPDDR4__BL_ON_FLY_ENABLE__REG DENALI_CTL_430
 #define LPDDR4__BL_ON_FLY_ENABLE__FLD LPDDR4__DENALI_CTL_430__BL_ON_FLY_ENABLE
 
-#define LPDDR4__DENALI_CTL_431_READ_MASK				             0x07070701U
-#define LPDDR4__DENALI_CTL_431_WRITE_MASK				            0x07070701U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK				   0x00000001U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET				           0U
+#define LPDDR4__DENALI_CTL_431_READ_MASK                             0x07070701U
+#define LPDDR4__DENALI_CTL_431_WRITE_MASK                            0x07070701U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_MASK                   0x00000001U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED32_WOSET                           0U
 #define LPDDR4__MC_RESERVED32__REG DENALI_CTL_431
 #define LPDDR4__MC_RESERVED32__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED32
 
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK				   0x00000700U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_MASK                   0x00000700U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED33_WIDTH                           3U
 #define LPDDR4__MC_RESERVED33__REG DENALI_CTL_431
 #define LPDDR4__MC_RESERVED33__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED33
 
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK				   0x00070000U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED34_WIDTH                           3U
 #define LPDDR4__MC_RESERVED34__REG DENALI_CTL_431
 #define LPDDR4__MC_RESERVED34__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED34
 
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK				   0x07000000U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_MASK                   0x07000000U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_431__MC_RESERVED35_WIDTH                           3U
 #define LPDDR4__MC_RESERVED35__REG DENALI_CTL_431
 #define LPDDR4__MC_RESERVED35__FLD LPDDR4__DENALI_CTL_431__MC_RESERVED35
 
-#define LPDDR4__DENALI_CTL_432_READ_MASK				             0x0F070707U
-#define LPDDR4__DENALI_CTL_432_WRITE_MASK				            0x0F070707U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK				   0x00000007U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_432_READ_MASK                             0x0F070707U
+#define LPDDR4__DENALI_CTL_432_WRITE_MASK                            0x0F070707U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_MASK                   0x00000007U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED36_WIDTH                           3U
 #define LPDDR4__MC_RESERVED36__REG DENALI_CTL_432
 #define LPDDR4__MC_RESERVED36__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED36
 
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK				   0x00000700U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_MASK                   0x00000700U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED37_WIDTH                           3U
 #define LPDDR4__MC_RESERVED37__REG DENALI_CTL_432
 #define LPDDR4__MC_RESERVED37__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED37
 
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK				   0x00070000U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH				           3U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_MASK                   0x00070000U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED38_WIDTH                           3U
 #define LPDDR4__MC_RESERVED38__REG DENALI_CTL_432
 #define LPDDR4__MC_RESERVED38__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED38
 
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_432__MC_RESERVED39_WIDTH                           4U
 #define LPDDR4__MC_RESERVED39__REG DENALI_CTL_432
 #define LPDDR4__MC_RESERVED39__FLD LPDDR4__DENALI_CTL_432__MC_RESERVED39
 
-#define LPDDR4__DENALI_CTL_433_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_433_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_433_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_433_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED40_WIDTH                           4U
 #define LPDDR4__MC_RESERVED40__REG DENALI_CTL_433
 #define LPDDR4__MC_RESERVED40__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED40
 
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED41_WIDTH                           4U
 #define LPDDR4__MC_RESERVED41__REG DENALI_CTL_433
 #define LPDDR4__MC_RESERVED41__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED41
 
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED42_WIDTH                           4U
 #define LPDDR4__MC_RESERVED42__REG DENALI_CTL_433
 #define LPDDR4__MC_RESERVED42__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED42
 
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_433__MC_RESERVED43_WIDTH                           4U
 #define LPDDR4__MC_RESERVED43__REG DENALI_CTL_433
 #define LPDDR4__MC_RESERVED43__FLD LPDDR4__DENALI_CTL_433__MC_RESERVED43
 
-#define LPDDR4__DENALI_CTL_434_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_434_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_434_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_434_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED44_WIDTH                           4U
 #define LPDDR4__MC_RESERVED44__REG DENALI_CTL_434
 #define LPDDR4__MC_RESERVED44__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED44
 
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED45_WIDTH                           4U
 #define LPDDR4__MC_RESERVED45__REG DENALI_CTL_434
 #define LPDDR4__MC_RESERVED45__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED45
 
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED46_WIDTH                           4U
 #define LPDDR4__MC_RESERVED46__REG DENALI_CTL_434
 #define LPDDR4__MC_RESERVED46__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED46
 
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_434__MC_RESERVED47_WIDTH                           4U
 #define LPDDR4__MC_RESERVED47__REG DENALI_CTL_434
 #define LPDDR4__MC_RESERVED47__FLD LPDDR4__DENALI_CTL_434__MC_RESERVED47
 
-#define LPDDR4__DENALI_CTL_435_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_435_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_435_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_435_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED48_WIDTH                           4U
 #define LPDDR4__MC_RESERVED48__REG DENALI_CTL_435
 #define LPDDR4__MC_RESERVED48__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED48
 
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED49_WIDTH                           4U
 #define LPDDR4__MC_RESERVED49__REG DENALI_CTL_435
 #define LPDDR4__MC_RESERVED49__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED49
 
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED50_WIDTH                           4U
 #define LPDDR4__MC_RESERVED50__REG DENALI_CTL_435
 #define LPDDR4__MC_RESERVED50__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED50
 
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_435__MC_RESERVED51_WIDTH                           4U
 #define LPDDR4__MC_RESERVED51__REG DENALI_CTL_435
 #define LPDDR4__MC_RESERVED51__FLD LPDDR4__DENALI_CTL_435__MC_RESERVED51
 
-#define LPDDR4__DENALI_CTL_436_READ_MASK				             0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_436_WRITE_MASK				            0x0F0F0F0FU
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_436_READ_MASK                             0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_436_WRITE_MASK                            0x0F0F0F0FU
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED52_WIDTH                           4U
 #define LPDDR4__MC_RESERVED52__REG DENALI_CTL_436
 #define LPDDR4__MC_RESERVED52__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED52
 
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED53_WIDTH                           4U
 #define LPDDR4__MC_RESERVED53__REG DENALI_CTL_436
 #define LPDDR4__MC_RESERVED53__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED53
 
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED54_WIDTH                           4U
 #define LPDDR4__MC_RESERVED54__REG DENALI_CTL_436
 #define LPDDR4__MC_RESERVED54__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED54
 
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK				   0x0F000000U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT				          24U
-#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_MASK                   0x0F000000U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_SHIFT                          24U
+#define LPDDR4__DENALI_CTL_436__MC_RESERVED55_WIDTH                           4U
 #define LPDDR4__MC_RESERVED55__REG DENALI_CTL_436
 #define LPDDR4__MC_RESERVED55__FLD LPDDR4__DENALI_CTL_436__MC_RESERVED55
 
-#define LPDDR4__DENALI_CTL_437_READ_MASK				             0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_437_WRITE_MASK				            0xFF0F0F0FU
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK				   0x0000000FU
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT				           0U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_437_READ_MASK                             0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_437_WRITE_MASK                            0xFF0F0F0FU
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_MASK                   0x0000000FU
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_SHIFT                           0U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED56_WIDTH                           4U
 #define LPDDR4__MC_RESERVED56__REG DENALI_CTL_437
 #define LPDDR4__MC_RESERVED56__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED56
 
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK				   0x00000F00U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_MASK                   0x00000F00U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED57_WIDTH                           4U
 #define LPDDR4__MC_RESERVED57__REG DENALI_CTL_437
 #define LPDDR4__MC_RESERVED57__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED57
 
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK				   0x000F0000U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT				          16U
-#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH				           4U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_MASK                   0x000F0000U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_SHIFT                          16U
+#define LPDDR4__DENALI_CTL_437__MC_RESERVED58_WIDTH                           4U
 #define LPDDR4__MC_RESERVED58__REG DENALI_CTL_437
 #define LPDDR4__MC_RESERVED58__FLD LPDDR4__DENALI_CTL_437__MC_RESERVED58
 
 #define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_MASK               0xFF000000U
-#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT				      24U
-#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH				       8U
+#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_SHIFT                      24U
+#define LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO_WIDTH                       8U
 #define LPDDR4__GLOBAL_ERROR_INFO__REG DENALI_CTL_437
 #define LPDDR4__GLOBAL_ERROR_INFO__FLD LPDDR4__DENALI_CTL_437__GLOBAL_ERROR_INFO
 
-#define LPDDR4__DENALI_CTL_438_READ_MASK				             0xFFFF03FFU
-#define LPDDR4__DENALI_CTL_438_WRITE_MASK				            0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_438_READ_MASK                             0xFFFF03FFU
+#define LPDDR4__DENALI_CTL_438_WRITE_MASK                            0xFFFF03FFU
 #define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_MASK               0x000000FFU
-#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT				       0U
-#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH				       8U
+#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_SHIFT                       0U
+#define LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK_WIDTH                       8U
 #define LPDDR4__GLOBAL_ERROR_MASK__REG DENALI_CTL_438
 #define LPDDR4__GLOBAL_ERROR_MASK__FLD LPDDR4__DENALI_CTL_438__GLOBAL_ERROR_MASK
 
 #define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_MASK         0x00000300U
-#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT				 8U
-#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH				 2U
+#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_SHIFT                 8U
+#define LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS_WIDTH                 2U
 #define LPDDR4__AXI_PARITY_ERROR_STATUS__REG DENALI_CTL_438
 #define LPDDR4__AXI_PARITY_ERROR_STATUS__FLD LPDDR4__DENALI_CTL_438__AXI_PARITY_ERROR_STATUS
 
-#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK				          0x00FF0000U
-#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT								 16U
-#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_438__NWR_F0_MASK                          0x00FF0000U
+#define LPDDR4__DENALI_CTL_438__NWR_F0_SHIFT                                 16U
+#define LPDDR4__DENALI_CTL_438__NWR_F0_WIDTH                                  8U
 #define LPDDR4__NWR_F0__REG DENALI_CTL_438
 #define LPDDR4__NWR_F0__FLD LPDDR4__DENALI_CTL_438__NWR_F0
 
-#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK				          0xFF000000U
-#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT								 24U
-#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_438__NWR_F1_MASK                          0xFF000000U
+#define LPDDR4__DENALI_CTL_438__NWR_F1_SHIFT                                 24U
+#define LPDDR4__DENALI_CTL_438__NWR_F1_WIDTH                                  8U
 #define LPDDR4__NWR_F1__REG DENALI_CTL_438
 #define LPDDR4__NWR_F1__FLD LPDDR4__DENALI_CTL_438__NWR_F1
 
-#define LPDDR4__DENALI_CTL_439_READ_MASK				             0x001F01FFU
-#define LPDDR4__DENALI_CTL_439_WRITE_MASK				            0x001F01FFU
-#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK				          0x000000FFU
-#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT								  0U
-#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH								  8U
+#define LPDDR4__DENALI_CTL_439_READ_MASK                             0x001F01FFU
+#define LPDDR4__DENALI_CTL_439_WRITE_MASK                            0x001F01FFU
+#define LPDDR4__DENALI_CTL_439__NWR_F2_MASK                          0x000000FFU
+#define LPDDR4__DENALI_CTL_439__NWR_F2_SHIFT                                  0U
+#define LPDDR4__DENALI_CTL_439__NWR_F2_WIDTH                                  8U
 #define LPDDR4__NWR_F2__REG DENALI_CTL_439
 #define LPDDR4__NWR_F2__FLD LPDDR4__DENALI_CTL_439__NWR_F2
 
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK				   0x00000100U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT				           8U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH				           1U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR				           0U
-#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET				           0U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_MASK                   0x00000100U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_SHIFT                           8U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WIDTH                           1U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOCLR                           0U
+#define LPDDR4__DENALI_CTL_439__MC_RESERVED59_WOSET                           0U
 #define LPDDR4__MC_RESERVED59__REG DENALI_CTL_439
 #define LPDDR4__MC_RESERVED59__FLD LPDDR4__DENALI_CTL_439__MC_RESERVED59
 
@@ -7560,29 +7560,29 @@
 #define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__REG DENALI_CTL_439
 #define LPDDR4__REGPORT_PARAM_PARITY_PROTECTION_STATUS__FLD LPDDR4__DENALI_CTL_439__REGPORT_PARAM_PARITY_PROTECTION_STATUS
 
-#define LPDDR4__DENALI_CTL_440_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_440_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_440_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_440_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_MASK 0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_SHIFT       0U
 #define LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0_WIDTH      32U
 #define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__REG DENALI_CTL_440
 #define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_0__FLD LPDDR4__DENALI_CTL_440__MC_PARITY_INJECTION_BYTE_ENABLE_0
 
-#define LPDDR4__DENALI_CTL_441_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_441_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_441_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_441_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_MASK 0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_SHIFT       0U
 #define LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1_WIDTH      32U
 #define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__REG DENALI_CTL_441
 #define LPDDR4__MC_PARITY_INJECTION_BYTE_ENABLE_1__FLD LPDDR4__DENALI_CTL_441__MC_PARITY_INJECTION_BYTE_ENABLE_1
 
-#define LPDDR4__DENALI_CTL_442_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_442_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_442_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_442_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_MASK            0x00000001U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT				    0U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH				    1U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR				    0U
-#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET				    0U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_SHIFT                    0U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WIDTH                    1U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOCLR                    0U
+#define LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE_WOSET                    0U
 #define LPDDR4__MC_PARITY_ERROR_TYPE__REG DENALI_CTL_442
 #define LPDDR4__MC_PARITY_ERROR_TYPE__FLD LPDDR4__DENALI_CTL_442__MC_PARITY_ERROR_TYPE
 
@@ -7610,8 +7610,8 @@
 #define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__REG DENALI_CTL_442
 #define LPDDR4__REGPORT_WRITE_PARITY_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_442__REGPORT_WRITE_PARITY_PROTECTION_EN
 
-#define LPDDR4__DENALI_CTL_443_READ_MASK				             0x01010101U
-#define LPDDR4__DENALI_CTL_443_WRITE_MASK				            0x01010101U
+#define LPDDR4__DENALI_CTL_443_READ_MASK                             0x01010101U
+#define LPDDR4__DENALI_CTL_443_WRITE_MASK                            0x01010101U
 #define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_MASK 0x00000001U
 #define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_SHIFT       0U
 #define LPDDR4__DENALI_CTL_443__REGPORT_READ_PARITY_PROTECTION_EN_WIDTH       1U
@@ -7644,8 +7644,8 @@
 #define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_443
 #define LPDDR4__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_443__REGPORT_WRITEMASK_PARITY_PROTECTION_INJECTION_EN
 
-#define LPDDR4__DENALI_CTL_444_READ_MASK				             0x00010101U
-#define LPDDR4__DENALI_CTL_444_WRITE_MASK				            0x00010101U
+#define LPDDR4__DENALI_CTL_444_READ_MASK                             0x00010101U
+#define LPDDR4__DENALI_CTL_444_WRITE_MASK                            0x00010101U
 #define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_MASK 0x00000001U
 #define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_SHIFT 0U
 #define LPDDR4__DENALI_CTL_444__REGPORT_WRITE_PARITY_PROTECTION_INJECTION_EN_WIDTH 1U
@@ -7670,27 +7670,27 @@
 #define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__REG DENALI_CTL_444
 #define LPDDR4__PARAMREG_PARITY_PROTECTION_INJECTION_EN__FLD LPDDR4__DENALI_CTL_444__PARAMREG_PARITY_PROTECTION_INJECTION_EN
 
-#define LPDDR4__DENALI_CTL_445_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_445_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_445__MC_RESERVED60_0_WIDTH                        32U
 #define LPDDR4__MC_RESERVED60_0__REG DENALI_CTL_445
 #define LPDDR4__MC_RESERVED60_0__FLD LPDDR4__DENALI_CTL_445__MC_RESERVED60_0
 
-#define LPDDR4__DENALI_CTL_446_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_446_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_446__MC_RESERVED60_1_WIDTH                        32U
 #define LPDDR4__MC_RESERVED60_1__REG DENALI_CTL_446
 #define LPDDR4__MC_RESERVED60_1__FLD LPDDR4__DENALI_CTL_446__MC_RESERVED60_1
 
-#define LPDDR4__DENALI_CTL_447_READ_MASK				             0x00000107U
-#define LPDDR4__DENALI_CTL_447_WRITE_MASK				            0x00000107U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK				 0x00000007U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH				         3U
+#define LPDDR4__DENALI_CTL_447_READ_MASK                             0x00000107U
+#define LPDDR4__DENALI_CTL_447_WRITE_MASK                            0x00000107U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_MASK                 0x00000007U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_447__MC_RESERVED60_2_WIDTH                         3U
 #define LPDDR4__MC_RESERVED60_2__REG DENALI_CTL_447
 #define LPDDR4__MC_RESERVED60_2__FLD LPDDR4__DENALI_CTL_447__MC_RESERVED60_2
 
@@ -7702,88 +7702,88 @@
 #define LPDDR4__PORT_TO_CORE_PROTECTION_EN__REG DENALI_CTL_447
 #define LPDDR4__PORT_TO_CORE_PROTECTION_EN__FLD LPDDR4__DENALI_CTL_447__PORT_TO_CORE_PROTECTION_EN
 
-#define LPDDR4__DENALI_CTL_448_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_448_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_448_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_448_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_MASK 0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_SHIFT  0U
 #define LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0_WIDTH 32U
 #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__REG DENALI_CTL_448
 #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_0__FLD LPDDR4__DENALI_CTL_448__PORT_TO_CORE_PROTECTION_INJECTION_EN_0
 
-#define LPDDR4__DENALI_CTL_449_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_449_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_449_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_449_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_MASK 0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_SHIFT  0U
 #define LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1_WIDTH 32U
 #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__REG DENALI_CTL_449
 #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_1__FLD LPDDR4__DENALI_CTL_449__PORT_TO_CORE_PROTECTION_INJECTION_EN_1
 
-#define LPDDR4__DENALI_CTL_450_READ_MASK				             0x00000007U
-#define LPDDR4__DENALI_CTL_450_WRITE_MASK				            0x00000007U
+#define LPDDR4__DENALI_CTL_450_READ_MASK                             0x00000007U
+#define LPDDR4__DENALI_CTL_450_WRITE_MASK                            0x00000007U
 #define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_MASK 0x00000007U
 #define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_SHIFT  0U
 #define LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2_WIDTH  3U
 #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__REG DENALI_CTL_450
 #define LPDDR4__PORT_TO_CORE_PROTECTION_INJECTION_EN_2__FLD LPDDR4__DENALI_CTL_450__PORT_TO_CORE_PROTECTION_INJECTION_EN_2
 
-#define LPDDR4__DENALI_CTL_451_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_451_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_451__MC_RESERVED61_0_WIDTH                        32U
 #define LPDDR4__MC_RESERVED61_0__REG DENALI_CTL_451
 #define LPDDR4__MC_RESERVED61_0__FLD LPDDR4__DENALI_CTL_451__MC_RESERVED61_0
 
-#define LPDDR4__DENALI_CTL_452_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_452_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_452__MC_RESERVED61_1_WIDTH                        32U
 #define LPDDR4__MC_RESERVED61_1__REG DENALI_CTL_452
 #define LPDDR4__MC_RESERVED61_1__FLD LPDDR4__DENALI_CTL_452__MC_RESERVED61_1
 
-#define LPDDR4__DENALI_CTL_453_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453_WRITE_MASK				            0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK				 0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH				        32U
+#define LPDDR4__DENALI_CTL_453_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453_WRITE_MASK                            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_MASK                 0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_453__MC_RESERVED61_2_WIDTH                        32U
 #define LPDDR4__MC_RESERVED61_2__REG DENALI_CTL_453
 #define LPDDR4__MC_RESERVED61_2__FLD LPDDR4__DENALI_CTL_453__MC_RESERVED61_2
 
-#define LPDDR4__DENALI_CTL_454_READ_MASK				             0x0000000FU
-#define LPDDR4__DENALI_CTL_454_WRITE_MASK				            0x0000000FU
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK				 0x0000000FU
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT				         0U
-#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH				         4U
+#define LPDDR4__DENALI_CTL_454_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_CTL_454_WRITE_MASK                            0x0000000FU
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_MASK                 0x0000000FU
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_SHIFT                         0U
+#define LPDDR4__DENALI_CTL_454__MC_RESERVED61_3_WIDTH                         4U
 #define LPDDR4__MC_RESERVED61_3__REG DENALI_CTL_454
 #define LPDDR4__MC_RESERVED61_3__FLD LPDDR4__DENALI_CTL_454__MC_RESERVED61_3
 
-#define LPDDR4__DENALI_CTL_455_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_455_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_455_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_455_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_MASK    0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_SHIFT            0U
 #define LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0_WIDTH           32U
 #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__REG DENALI_CTL_455
 #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_0__FLD LPDDR4__DENALI_CTL_455__PORT_TO_CORE_LR_ERR_INJ_EN_0
 
-#define LPDDR4__DENALI_CTL_456_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_456_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_456_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_456_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_MASK    0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_SHIFT            0U
 #define LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1_WIDTH           32U
 #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__REG DENALI_CTL_456
 #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_1__FLD LPDDR4__DENALI_CTL_456__PORT_TO_CORE_LR_ERR_INJ_EN_1
 
-#define LPDDR4__DENALI_CTL_457_READ_MASK				             0xFFFFFFFFU
-#define LPDDR4__DENALI_CTL_457_WRITE_MASK				            0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_457_READ_MASK                             0xFFFFFFFFU
+#define LPDDR4__DENALI_CTL_457_WRITE_MASK                            0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_MASK    0xFFFFFFFFU
 #define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_SHIFT            0U
 #define LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2_WIDTH           32U
 #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__REG DENALI_CTL_457
 #define LPDDR4__PORT_TO_CORE_LR_ERR_INJ_EN_2__FLD LPDDR4__DENALI_CTL_457__PORT_TO_CORE_LR_ERR_INJ_EN_2
 
-#define LPDDR4__DENALI_CTL_458_READ_MASK				             0x0000000FU
-#define LPDDR4__DENALI_CTL_458_WRITE_MASK				            0x0000000FU
+#define LPDDR4__DENALI_CTL_458_READ_MASK                             0x0000000FU
+#define LPDDR4__DENALI_CTL_458_WRITE_MASK                            0x0000000FU
 #define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_MASK    0x0000000FU
 #define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_SHIFT            0U
 #define LPDDR4__DENALI_CTL_458__PORT_TO_CORE_LR_ERR_INJ_EN_3_WIDTH            4U
-- 
2.28.0



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