[PATCH v7 1/8] riscv: cpu: fu740: Add support for cpu fu740
Dimitri John Ledkov
dimitri.ledkov at canonical.com
Tue May 4 12:04:50 CEST 2021
(resending to the list after subscribing)
Hi,
On Thu, Apr 22, 2021 at 10:14 AM Green Wan <green.wan at sifive.com> wrote:
>
> Add SiFive fu740 cpu to support RISC-V arch
>
> Signed-off-by: Green Wan <green.wan at sifive.com>
> Reviewed-by: Bin Meng <bmeng.cn at gmail.com>
> ---
> arch/riscv/Kconfig | 1 +
> arch/riscv/cpu/fu740/Kconfig | 37 +++++++++++++++
> arch/riscv/cpu/fu740/Makefile | 12 +++++
> arch/riscv/cpu/fu740/cache.c | 55 +++++++++++++++++++++++
> arch/riscv/cpu/fu740/cpu.c | 22 +++++++++
> arch/riscv/cpu/fu740/dram.c | 38 ++++++++++++++++
> arch/riscv/cpu/fu740/spl.c | 23 ++++++++++
> arch/riscv/include/asm/arch-fu740/cache.h | 14 ++++++
> arch/riscv/include/asm/arch-fu740/clk.h | 14 ++++++
> arch/riscv/include/asm/arch-fu740/gpio.h | 38 ++++++++++++++++
> arch/riscv/include/asm/arch-fu740/reset.h | 13 ++++++
> arch/riscv/include/asm/arch-fu740/spl.h | 14 ++++++
> arch/riscv/lib/sifive_clint.c | 1 -
> 13 files changed, 281 insertions(+), 1 deletion(-)
> create mode 100644 arch/riscv/cpu/fu740/Kconfig
> create mode 100644 arch/riscv/cpu/fu740/Makefile
> create mode 100644 arch/riscv/cpu/fu740/cache.c
> create mode 100644 arch/riscv/cpu/fu740/cpu.c
> create mode 100644 arch/riscv/cpu/fu740/dram.c
> create mode 100644 arch/riscv/cpu/fu740/spl.c
> create mode 100644 arch/riscv/include/asm/arch-fu740/cache.h
> create mode 100644 arch/riscv/include/asm/arch-fu740/clk.h
> create mode 100644 arch/riscv/include/asm/arch-fu740/gpio.h
> create mode 100644 arch/riscv/include/asm/arch-fu740/reset.h
> create mode 100644 arch/riscv/include/asm/arch-fu740/spl.h
>
> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
> index 3f221dccdb..4177253e44 100644
> --- a/arch/riscv/Kconfig
> +++ b/arch/riscv/Kconfig
> @@ -61,6 +61,7 @@ source "board/sipeed/maix/Kconfig"
> # platform-specific options below
> source "arch/riscv/cpu/ax25/Kconfig"
> source "arch/riscv/cpu/fu540/Kconfig"
> +source "arch/riscv/cpu/fu740/Kconfig"
> source "arch/riscv/cpu/generic/Kconfig"
>
> # architecture-specific options below
> diff --git a/arch/riscv/cpu/fu740/Kconfig b/arch/riscv/cpu/fu740/Kconfig
> new file mode 100644
> index 0000000000..24788beab1
> --- /dev/null
> +++ b/arch/riscv/cpu/fu740/Kconfig
> @@ -0,0 +1,37 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2020-2021 SiFive, Inc
> +# Pragnesh Patel <pragnesh.patel at sifive.com>
> +
> +config SIFIVE_FU740
> + bool
> + select ARCH_EARLY_INIT_R
> + select RAM
> + select SPL_RAM if SPL
> + imply CPU
> + imply CPU_RISCV
> + imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
> + imply SIFIVE_CLINT if (RISCV_MMODE || SPL_RISCV_MMODE)
> + imply CMD_CPU
> + imply SPL_CPU
> + imply SPL_OPENSBI
> + imply SPL_LOAD_FIT
> + imply SMP
> + imply CLK_SIFIVE
> + imply CLK_SIFIVE_PRCI
> + imply SIFIVE_SERIAL
> + imply MACB
> + imply MII
> + imply SPI
> + imply SPI_SIFIVE
> + imply MMC
> + imply MMC_SPI
> + imply MMC_BROKEN_CD
> + imply CMD_MMC
> + imply DM_GPIO
> + imply SIFIVE_GPIO
> + imply CMD_GPIO
> + imply MISC
> + imply SIFIVE_OTP
> + imply DM_PWM
> + imply PWM_SIFIVE
> diff --git a/arch/riscv/cpu/fu740/Makefile b/arch/riscv/cpu/fu740/Makefile
> new file mode 100644
> index 0000000000..5ef8ac18a7
> --- /dev/null
> +++ b/arch/riscv/cpu/fu740/Makefile
> @@ -0,0 +1,12 @@
> +# SPDX-License-Identifier: GPL-2.0+
> +#
> +# Copyright (C) 2020-2021 SiFive, Inc
> +# Pragnesh Patel <pragnesh.patel at sifive.com>
> +
> +ifeq ($(CONFIG_SPL_BUILD),y)
> +obj-y += spl.o
> +else
> +obj-y += dram.o
> +obj-y += cpu.o
> +obj-y += cache.o
> +endif
> diff --git a/arch/riscv/cpu/fu740/cache.c b/arch/riscv/cpu/fu740/cache.c
> new file mode 100644
> index 0000000000..680955c9e3
> --- /dev/null
> +++ b/arch/riscv/cpu/fu740/cache.c
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020-2021 SiFive, Inc
> + *
> + * Authors:
> + * Pragnesh Patel <pragnesh.patel at sifive.com>
> + */
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <linux/bitops.h>
> +#include <asm/global_data.h>
> +
> +/* Register offsets */
> +#define L2_CACHE_CONFIG 0x000
> +#define L2_CACHE_ENABLE 0x008
> +
> +#define MASK_NUM_WAYS GENMASK(15, 8)
> +#define NUM_WAYS_SHIFT 8
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int cache_enable_ways(void)
> +{
> + const void *blob = gd->fdt_blob;
> + int node;
> + fdt_addr_t base;
> + u32 config;
> + u32 ways;
> +
> + volatile u32 *enable;
> +
> + node = fdt_node_offset_by_compatible(blob, -1,
> + "sifive,fu740-c000-ccache");
> +
> + if (node < 0)
> + return node;
> +
> + base = fdtdec_get_addr_size_auto_parent(blob, 0, node, "reg", 0,
> + NULL, false);
> + if (base == FDT_ADDR_T_NONE)
> + return FDT_ADDR_T_NONE;
> +
> + config = readl((volatile u32 *)base + L2_CACHE_CONFIG);
> + ways = (config & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
> +
> + enable = (volatile u32 *)(base + L2_CACHE_ENABLE);
> +
> + /* memory barrier */
> + mb();
> + (*enable) = ways - 1;
> + /* memory barrier */
> + mb();
> + return 0;
> +}
> diff --git a/arch/riscv/cpu/fu740/cpu.c b/arch/riscv/cpu/fu740/cpu.c
> new file mode 100644
> index 0000000000..f13c18942f
> --- /dev/null
> +++ b/arch/riscv/cpu/fu740/cpu.c
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng <bmeng.cn at gmail.com>
> + */
> +
> +#include <irq_func.h>
> +#include <asm/cache.h>
> +
> +/*
> + * cleanup_before_linux() is called just before we call linux
> + * it prepares the processor for linux
> + *
> + * we disable interrupt and caches.
> + */
> +int cleanup_before_linux(void)
> +{
> + disable_interrupts();
> +
> + cache_flush();
> +
> + return 0;
> +}
> diff --git a/arch/riscv/cpu/fu740/dram.c b/arch/riscv/cpu/fu740/dram.c
> new file mode 100644
> index 0000000000..1dc77efeca
> --- /dev/null
> +++ b/arch/riscv/cpu/fu740/dram.c
> @@ -0,0 +1,38 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018, Bin Meng <bmeng.cn at gmail.com>
> + */
> +
> +#include <common.h>
> +#include <fdtdec.h>
> +#include <init.h>
> +#include <linux/sizes.h>
> +
> +DECLARE_GLOBAL_DATA_PTR;
> +
> +int dram_init(void)
> +{
> + return fdtdec_setup_mem_size_base();
> +}
> +
> +int dram_init_banksize(void)
> +{
> + return fdtdec_setup_memory_banksize();
> +}
> +
> +ulong board_get_usable_ram_top(ulong total_size)
> +{
> +#ifdef CONFIG_64BIT
> + /*
> + * Ensure that we run from first 4GB so that all
> + * addresses used by U-Boot are 32bit addresses.
> + *
> + * This in-turn ensures that 32bit DMA capable
> + * devices work fine because DMA mapping APIs will
> + * provide 32bit DMA addresses only.
> + */
> + if (gd->ram_top > SZ_4G)
> + return SZ_4G;
> +#endif
> + return gd->ram_top;
> +}
> diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c
> new file mode 100644
> index 0000000000..ea0b2283a2
> --- /dev/null
> +++ b/arch/riscv/cpu/fu740/spl.c
> @@ -0,0 +1,23 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2020-201 SiFive, Inc
> + * Pragnesh Patel <pragnesh.patel at sifive.com>
> + */
> +
> +#include <dm.h>
> +#include <log.h>
> +
> +int spl_soc_init(void)
> +{
> + int ret;
> + struct udevice *dev;
> +
> + /* DDR init */
> + ret = uclass_get_device(UCLASS_RAM, 0, &dev);
> + if (ret) {
> + debug("DRAM init failed: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> diff --git a/arch/riscv/include/asm/arch-fu740/cache.h b/arch/riscv/include/asm/arch-fu740/cache.h
> new file mode 100644
> index 0000000000..7d4fe9942b
> --- /dev/null
> +++ b/arch/riscv/include/asm/arch-fu740/cache.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020-2021 SiFive, Inc.
> + *
> + * Authors:
> + * Pragnesh Patel <pragnesh.patel at sifve.com>
> + */
> +
> +#ifndef _CACHE_SIFIVE_H
> +#define _CACHE_SIFIVE_H
> +
> +int cache_enable_ways(void);
> +
> +#endif /* _CACHE_SIFIVE_H */
> diff --git a/arch/riscv/include/asm/arch-fu740/clk.h b/arch/riscv/include/asm/arch-fu740/clk.h
> new file mode 100644
> index 0000000000..9f883616b2
> --- /dev/null
> +++ b/arch/riscv/include/asm/arch-fu740/clk.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2020-2021 SiFive Inc
> + *
> + * Authors:
> + * Pragnesh Patel <pragnesh.patel at sifive.com>
> + */
> +
> +#ifndef __CLK_SIFIVE_H
> +#define __CLK_SIFIVE_H
> +
> +/* Note: This is a placeholder header for driver compilation. */
> +
> +#endif
> diff --git a/arch/riscv/include/asm/arch-fu740/gpio.h b/arch/riscv/include/asm/arch-fu740/gpio.h
> new file mode 100644
> index 0000000000..908e2e5563
> --- /dev/null
> +++ b/arch/riscv/include/asm/arch-fu740/gpio.h
> @@ -0,0 +1,38 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020-2021 SiFive, Inc.
> + */
> +
> +#ifndef _GPIO_SIFIVE_H
> +#define _GPIO_SIFIVE_H
> +
> +#define GPIO_INPUT_VAL 0x00
> +#define GPIO_INPUT_EN 0x04
> +#define GPIO_OUTPUT_EN 0x08
> +#define GPIO_OUTPUT_VAL 0x0C
> +#define GPIO_RISE_IE 0x18
> +#define GPIO_RISE_IP 0x1C
> +#define GPIO_FALL_IE 0x20
> +#define GPIO_FALL_IP 0x24
> +#define GPIO_HIGH_IE 0x28
> +#define GPIO_HIGH_IP 0x2C
> +#define GPIO_LOW_IE 0x30
> +#define GPIO_LOW_IP 0x34
> +#define GPIO_OUTPUT_XOR 0x40
> +
> +#define NR_GPIOS 16
> +
> +enum gpio_state {
> + LOW,
> + HIGH
> +};
> +
> +/* Details about a GPIO bank */
> +struct sifive_gpio_plat {
> + void *base; /* address of registers in physical memory */
> +};
> +
> +#define SIFIVE_GENERIC_GPIO_NR(port, index) \
> + (((port) * NR_GPIOS) + ((index) & (NR_GPIOS - 1)))
> +
> +#endif /* _GPIO_SIFIVE_H */
> diff --git a/arch/riscv/include/asm/arch-fu740/reset.h b/arch/riscv/include/asm/arch-fu740/reset.h
> new file mode 100644
> index 0000000000..538ef87410
> --- /dev/null
> +++ b/arch/riscv/include/asm/arch-fu740/reset.h
> @@ -0,0 +1,13 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (c) 2020-2021 SiFive, Inc.
> + *
> + * Author: Sagar Kadam <sagar.kadam at sifive.com>
> + */
> +
> +#ifndef __RESET_SIFIVE_H
> +#define __RESET_SIFIVE_H
> +
> +int sifive_reset_bind(struct udevice *dev, ulong count);
> +
> +#endif
> diff --git a/arch/riscv/include/asm/arch-fu740/spl.h b/arch/riscv/include/asm/arch-fu740/spl.h
> new file mode 100644
> index 0000000000..15ad9e7c8b
> --- /dev/null
> +++ b/arch/riscv/include/asm/arch-fu740/spl.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright (C) 2020-2021 SiFive, Inc.
> + *
> + * Authors:
> + * Pragnesh Patel <pragnesh.patel at sifve.com>
> + */
> +
> +#ifndef _SPL_SIFIVE_H
> +#define _SPL_SIFIVE_H
> +
> +int spl_soc_init(void);
> +
> +#endif /* _SPL_SIFIVE_H */
> diff --git a/arch/riscv/lib/sifive_clint.c b/arch/riscv/lib/sifive_clint.c
> index ab22395c55..cfa288a01a 100644
> --- a/arch/riscv/lib/sifive_clint.c
> +++ b/arch/riscv/lib/sifive_clint.c
> @@ -10,7 +10,6 @@
>
> #include <common.h>
> #include <dm.h>
> -#include <asm/global_data.h>
> #include <asm/io.h>
> #include <asm/smp.h>
> #include <linux/err.h>
Why is this include being removed? As far as I can tell the file does
use things from asm/global_data.h i.e. a little further down it does
...
DECLARE_GLOBAL_DATA_PTR;
...
gd->arch.clint
Which come from asm/global_data.h header. Am I missing something?
--
Regards,
Dimitri.
--
Regards,
Dimitri.
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