[PATCH v9 21/28] mtd: spi-nor-core: Do not make invalid quad enable fatal

Pratyush Yadav p.yadav at ti.com
Wed May 5 11:41:31 CEST 2021

The Micron MT35XU512ABA flash does not support the quad enable bit. But
instead of programming the Quad Enable Require field to 000b ("Device
does not have a QE bit"), it is programmed to 111b ("Reserved").

While this is technically incorrect, it is not reason enough to abort
BFPT parsing. Instead, continue BFPT parsing assuming there is no quad
enable bit present.

Signed-off-by: Pratyush Yadav <p.yadav at ti.com>
 drivers/mtd/spi/spi-nor-core.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index b041ccac18..12e2037f01 100644
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -2100,7 +2100,8 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
-		return -EINVAL;
+		dev_dbg(nor->dev, "BFPT QER reserved value used\n");
+		break;
 	/* Stop here if JESD216 rev B. */

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