[PATCH 13/15] ram: k3-ddrss: Introduce common driver with J7 SoC support
Tero Kristo
kristo at kernel.org
Wed May 5 16:22:08 CEST 2021
Hi Dave,
This patch is rather massive, so I did quite sparse review of the patch.
Anyways, it seems like this is mostly attempting to clean up the
existing code in various places so I believe any kind of improvement is
good, so you can consider my comments as something to think about only.
I would not hold back the patch based on those.
On 04/05/2021 05:52, Dave Gerlach wrote:
> Introduce a new version of the ddr driver which has the ability to
> support different variations of the controller. Also introduce support
> for the 32bit variation of the controller which is what was already
> supported by the previous version used for J721e and J7200.
>
> Signed-off-by: Dave Gerlach <d-gerlach at ti.com>
> ---
> drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h | 91 +
> .../ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h | 14 +
> .../k3-ddrss/32bit/lpddr4_32bit_structs_if.h | 15 +
> .../lpddr4_address_slice_0_macros.h | 9 +-
> .../k3-ddrss/{ => 32bit}/lpddr4_ctl_regs.h | 9 +-
> .../k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h | 23 +
> .../{ => 32bit}/lpddr4_data_slice_0_macros.h | 9 +-
> .../{ => 32bit}/lpddr4_data_slice_1_macros.h | 9 +-
> .../{ => 32bit}/lpddr4_data_slice_2_macros.h | 9 +-
> .../{ => 32bit}/lpddr4_data_slice_3_macros.h | 9 +-
> .../lpddr4_ddr_controller_macros.h | 0
> .../{ => 32bit}/lpddr4_phy_core_macros.h | 9 +-
> .../k3-ddrss/{ => 32bit}/lpddr4_pi_macros.h | 0
> drivers/ram/k3-ddrss/Makefile | 13 +-
> drivers/ram/k3-ddrss/cdn_errno.h | 140 +
> drivers/ram/k3-ddrss/cdn_inttypes.h | 14 +
> drivers/ram/k3-ddrss/cdn_stdint.h | 14 +
> drivers/ram/k3-ddrss/cdn_stdtypes.h | 19 +
> drivers/ram/k3-ddrss/cps_drv_lpddr4.h | 157 +-
> .../k3-ddrss/{k3-j721e-ddrss.c => k3-ddrss.c} | 220 +-
> drivers/ram/k3-ddrss/lpddr4.c | 2262 +++++------------
> drivers/ram/k3-ddrss/lpddr4.h | 73 +
> drivers/ram/k3-ddrss/lpddr4_32bit.c | 302 +++
> drivers/ram/k3-ddrss/lpddr4_32bit.h | 30 +
> .../k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c | 1548 +++++++++++
> drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h | 223 ++
> drivers/ram/k3-ddrss/lpddr4_if.h | 658 +----
> drivers/ram/k3-ddrss/lpddr4_obj_if.c | 86 +-
> drivers/ram/k3-ddrss/lpddr4_obj_if.h | 455 +---
> drivers/ram/k3-ddrss/lpddr4_sanity.h | 1222 ++-------
> drivers/ram/k3-ddrss/lpddr4_structs_if.h | 128 +-
> 31 files changed, 3882 insertions(+), 3888 deletions(-)
> create mode 100644 drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
> create mode 100644 drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
> create mode 100644 drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_address_slice_0_macros.h (99%)
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_ctl_regs.h (99%)
> create mode 100644 drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_data_slice_0_macros.h (99%)
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_data_slice_1_macros.h (99%)
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_data_slice_2_macros.h (99%)
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_data_slice_3_macros.h (99%)
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_ddr_controller_macros.h (100%)
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_phy_core_macros.h (99%)
> rename drivers/ram/k3-ddrss/{ => 32bit}/lpddr4_pi_macros.h (100%)
> create mode 100644 drivers/ram/k3-ddrss/cdn_errno.h
> create mode 100644 drivers/ram/k3-ddrss/cdn_inttypes.h
> create mode 100644 drivers/ram/k3-ddrss/cdn_stdint.h
> create mode 100644 drivers/ram/k3-ddrss/cdn_stdtypes.h
> rename drivers/ram/k3-ddrss/{k3-j721e-ddrss.c => k3-ddrss.c} (60%)
> create mode 100644 drivers/ram/k3-ddrss/lpddr4.h
> create mode 100644 drivers/ram/k3-ddrss/lpddr4_32bit.c
> create mode 100644 drivers/ram/k3-ddrss/lpddr4_32bit.h
> create mode 100644 drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
> create mode 100644 drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
>
> diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
> new file mode 100644
> index 000000000000..c30a24780324
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_if.h
> @@ -0,0 +1,91 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef LPDDR4_32BIT_IF_H
> +#define LPDDR4_32BIT_IF_H
> +
> +#include "cdn_stdtypes.h"
> +
> +#define LPDDR4_INTR_MAX_CS (2U)
> +
> +#define LPDDR4_INTR_CTL_REG_COUNT (459U)
> +
> +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (300U)
> +
> +#define LPDDR4_INTR_PHY_REG_COUNT (1423U)
> +
> +typedef enum {
> + LPDDR4_INTR_RESET_DONE = 0U,
> + LPDDR4_INTR_BUS_ACCESS_ERROR = 1U,
> + LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR = 2U,
> + LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR = 3U,
> + LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR = 4U,
> + LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR = 5U,
> + LPDDR4_INTR_ECC_SCRUB_DONE = 6U,
> + LPDDR4_INTR_ECC_SCRUB_ERROR = 7U,
> + LPDDR4_INTR_PORT_COMMAND_ERROR = 8U,
> + LPDDR4_INTR_MC_INIT_DONE = 9U,
> + LPDDR4_INTR_LP_DONE = 10U,
> + LPDDR4_INTR_BIST_DONE = 11U,
> + LPDDR4_INTR_WRAP_ERROR = 12U,
> + LPDDR4_INTR_INVALID_BURST_ERROR = 13U,
> + LPDDR4_INTR_RDLVL_ERROR = 14U,
> + LPDDR4_INTR_RDLVL_GATE_ERROR = 15U,
> + LPDDR4_INTR_WRLVL_ERROR = 16U,
> + LPDDR4_INTR_CA_TRAINING_ERROR = 17U,
> + LPDDR4_INTR_DFI_UPDATE_ERROR = 18U,
> + LPDDR4_INTR_MRR_ERROR = 19U,
> + LPDDR4_INTR_PHY_MASTER_ERROR = 20U,
> + LPDDR4_INTR_WRLVL_REQ = 21U,
> + LPDDR4_INTR_RDLVL_REQ = 22U,
> + LPDDR4_INTR_RDLVL_GATE_REQ = 23U,
> + LPDDR4_INTR_CA_TRAINING_REQ = 24U,
> + LPDDR4_INTR_LEVELING_DONE = 25U,
> + LPDDR4_INTR_PHY_ERROR = 26U,
> + LPDDR4_INTR_MR_READ_DONE = 27U,
> + LPDDR4_INTR_TEMP_CHANGE = 28U,
> + LPDDR4_INTR_TEMP_ALERT = 29U,
> + LPDDR4_INTR_SW_DQS_COMPLETE = 30U,
> + LPDDR4_INTR_DQS_OSC_BV_UPDATED = 31U,
> + LPDDR4_INTR_DQS_OSC_OVERFLOW = 32U,
> + LPDDR4_INTR_DQS_OSC_VAR_OUT = 33U,
> + LPDDR4_INTR_MR_WRITE_DONE = 34U,
> + LPDDR4_INTR_INHIBIT_DRAM_DONE = 35U,
> + LPDDR4_INTR_DFI_INIT_STATE = 36U,
> + LPDDR4_INTR_DLL_RESYNC_DONE = 37U,
> + LPDDR4_INTR_TDFI_TO = 38U,
> + LPDDR4_INTR_DFS_DONE = 39U,
> + LPDDR4_INTR_DFS_STATUS = 40U,
> + LPDDR4_INTR_REFRESH_STATUS = 41U,
> + LPDDR4_INTR_ZQ_STATUS = 42U,
> + LPDDR4_INTR_SW_REQ_MODE = 43U,
> + LPDDR4_INTR_LOR_BITS = 44U
> +} lpddr4_intr_ctlinterrupt;
> +
> +typedef enum {
> + LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT = 0U,
> + LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
> + LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
> + LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
> + LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT = 4U,
> + LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
> + LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT = 6U,
> + LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
> + LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
> + LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT = 9U,
> + LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
> + LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT = 11U,
> + LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT = 12U,
> + LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
> + LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT = 14U,
> + LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT = 15U,
> + LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
> + LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
> +} lpddr4_intr_phyindepinterrupt;
> +
> +#endif /* LPDDR4_32BIT_IF_H */
> diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
> new file mode 100644
> index 000000000000..7fee54f00d5a
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_obj_if.h
Whats the purpose of this header? Seems pretty pointless wrapper for
lpddr4_32bit_if.h. More so, this doesn't appear to be used from anywhere
either.
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef LPDDR4_32BIT_OBJ_IF_H
> +#define LPDDR4_32BIT_OBJ_IF_H
> +
> +#include "lpddr4_32bit_if.h"
> +
> +#endif /* LPDDR4_32BIT_OBJ_IF_H */
> diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
> new file mode 100644
> index 000000000000..90c24dec3948
> --- /dev/null > +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_32bit_structs_if.h
Same question for this header.
> @@ -0,0 +1,15 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef LPDDR4_32BIT_STRUCTS_IF_H
> +#define LPDDR4_32BIT_STRUCTS_IF_H
> +
> +#include "cdn_stdtypes.h"
> +#include "lpddr4_32bit_if.h"
> +
> +#endif /* LPDDR4_32BIT_STRUCTS_IF_H */
> diff --git a/drivers/ram/k3-ddrss/lpddr4_address_slice_0_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
> similarity index 99%
> rename from drivers/ram/k3-ddrss/lpddr4_address_slice_0_macros.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
> index 6fc9b0f74a84..58ba340e7874 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_address_slice_0_macros.h
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_address_slice_0_macros.h
> @@ -1,10 +1,9 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> +/*
> + * Cadence DDR Driver
> *
> - * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
> - *
> - **********************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef REG_LPDDR4_ADDRESS_SLICE_0_MACROS_H_
> diff --git a/drivers/ram/k3-ddrss/lpddr4_ctl_regs.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
> similarity index 99%
> rename from drivers/ram/k3-ddrss/lpddr4_ctl_regs.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
> index 34e6698906ff..4113608434c3 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_ctl_regs.h
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs.h
> @@ -1,10 +1,9 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> +/*
> + * Cadence DDR Driver
> *
> - * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
> - *
> - **********************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef REG_LPDDR4_CTL_REGS_H_
> diff --git a/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
> new file mode 100644
> index 000000000000..d126e9589109
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_ctl_regs_rw_masks.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef LPDDR4_RW_MASKS_H_
> +#define LPDDR4_RW_MASKS_H_
> +
> +#include "cdn_stdint.h"
> +
> +extern u32 g_lpddr4_ddr_controller_rw_mask[459];
> +extern u32 g_lpddr4_pi_rw_mask[300];
> +extern u32 g_lpddr4_data_slice_0_rw_mask[140];
> +extern u32 g_lpddr4_data_slice_1_rw_mask[140];
> +extern u32 g_lpddr4_data_slice_2_rw_mask[140];
> +extern u32 g_lpddr4_data_slice_3_rw_mask[140];
> +extern u32 g_lpddr4_address_slice_0_rw_mask[52];
> +extern u32 g_lpddr4_phy_core_rw_mask[143];
> +
> +#endif /* LPDDR4_RW_MASKS_H_ */
> diff --git a/drivers/ram/k3-ddrss/lpddr4_data_slice_0_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
> similarity index 99%
> rename from drivers/ram/k3-ddrss/lpddr4_data_slice_0_macros.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
> index e1a1620c3e93..ad45dd98d793 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_data_slice_0_macros.h
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_0_macros.h
> @@ -1,10 +1,9 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> +/*
> + * Cadence DDR Driver
> *
> - * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
> - *
> - **********************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef REG_LPDDR4_DATA_SLICE_0_MACROS_H_
> diff --git a/drivers/ram/k3-ddrss/lpddr4_data_slice_1_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
> similarity index 99%
> rename from drivers/ram/k3-ddrss/lpddr4_data_slice_1_macros.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
> index ea1c25e171dc..5385e1e87b1e 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_data_slice_1_macros.h
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_1_macros.h
> @@ -1,10 +1,9 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> +/*
> + * Cadence DDR Driver
> *
> - * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
> - *
> - **********************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef REG_LPDDR4_DATA_SLICE_1_MACROS_H_
> diff --git a/drivers/ram/k3-ddrss/lpddr4_data_slice_2_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
> similarity index 99%
> rename from drivers/ram/k3-ddrss/lpddr4_data_slice_2_macros.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
> index 7ace5fa1c194..f6edad4eab9e 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_data_slice_2_macros.h
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_2_macros.h
> @@ -1,10 +1,9 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> +/*
> + * Cadence DDR Driver
> *
> - * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
> - *
> - **********************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef REG_LPDDR4_DATA_SLICE_2_MACROS_H_
> diff --git a/drivers/ram/k3-ddrss/lpddr4_data_slice_3_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
> similarity index 99%
> rename from drivers/ram/k3-ddrss/lpddr4_data_slice_3_macros.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
> index 25631b5ad34c..73e5f71df972 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_data_slice_3_macros.h
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_data_slice_3_macros.h
> @@ -1,10 +1,9 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> +/*
> + * Cadence DDR Driver
> *
> - * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
> - *
> - **********************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef REG_LPDDR4_DATA_SLICE_3_MACROS_H_
> diff --git a/drivers/ram/k3-ddrss/lpddr4_ddr_controller_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
> similarity index 100%
> rename from drivers/ram/k3-ddrss/lpddr4_ddr_controller_macros.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_ddr_controller_macros.h
> diff --git a/drivers/ram/k3-ddrss/lpddr4_phy_core_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
> similarity index 99%
> rename from drivers/ram/k3-ddrss/lpddr4_phy_core_macros.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
> index 67dff89783b0..d8c7a5222e56 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_phy_core_macros.h
> +++ b/drivers/ram/k3-ddrss/32bit/lpddr4_phy_core_macros.h
> @@ -1,10 +1,9 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> +/*
> + * Cadence DDR Driver
> *
> - * THIS FILE IS AUTOMATICALLY GENERATED, DO NOT EDIT
> - *
> - **********************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef REG_LPDDR4_PHY_CORE_MACROS_H_
> diff --git a/drivers/ram/k3-ddrss/lpddr4_pi_macros.h b/drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
> similarity index 100%
> rename from drivers/ram/k3-ddrss/lpddr4_pi_macros.h
> rename to drivers/ram/k3-ddrss/32bit/lpddr4_pi_macros.h
> diff --git a/drivers/ram/k3-ddrss/Makefile b/drivers/ram/k3-ddrss/Makefile
> index d60cc626e02f..c26fbc3dca55 100644
> --- a/drivers/ram/k3-ddrss/Makefile
> +++ b/drivers/ram/k3-ddrss/Makefile
> @@ -1,8 +1,13 @@
> # SPDX-License-Identifier: GPL-2.0+
> #
> -# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
> +# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
> #
>
> -obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e-ddrss.o
> -obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_obj_if.o
> -obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4.o
> +obj-$(CONFIG_K3_DDRSS) += k3-ddrss.o
> +obj-$(CONFIG_K3_DDRSS) += lpddr4_obj_if.o
> +obj-$(CONFIG_K3_DDRSS) += lpddr4.o
> +ccflags-$(CONFIG_K3_DDRSS) += -Idrivers/ram/k3-ddrss/
> +
> +obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit.o
> +obj-$(CONFIG_K3_J721E_DDRSS) += lpddr4_32bit_ctl_regs_rw_masks.o
> +ccflags-$(CONFIG_K3_J721E_DDRSS) += -Idrivers/ram/k3-ddrss/32bit/
> diff --git a/drivers/ram/k3-ddrss/cdn_errno.h b/drivers/ram/k3-ddrss/cdn_errno.h
> new file mode 100644
> index 000000000000..8a83f967ed66
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/cdn_errno.h
> @@ -0,0 +1,140 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef INCLUDE_CDN_ERRNO_H
> +#define INCLUDE_CDN_ERRNO_H
> +
> +#ifndef ERRNO_H_NOT_PRESENT
> +#include <errno.h>
> +#endif //ERRNO_H_NOT_PRESENT
> +
> +#ifndef REMOVE_OLD_ERRORCODES
> +
Oh no, this doesn't look good. Why are you doing this? If it doesn't
cause any actual errors, it will definitely confuse people at least.
> +#ifndef EOK
> +#define EOK 0 /* no error */
> +#endif //EOK
> +
> +#ifndef EPERM
> +#define EPERM 1 /* Operation not permitted */
> +#endif //EPERM
> +
> +#ifndef ENOENT
> +#define ENOENT 2 /* No such file or directory */
> +#endif //ENOENT
> +
> +#ifndef EIO
> +#define EIO 5 /* I/O error */
> +#endif //EIO
> +
> +#ifndef ENOEXEC
> +#define ENOEXEC 8 /* Exec format error */
> +#endif //ENOEXEC
> +
> +#ifndef EAGAIN
> +#define EAGAIN 11 /* Try again */
> +#endif //EAGAIN
> +
> +#ifndef ENOMEM
> +#define ENOMEM 12 /* Out of memory */
> +#endif //ENOMEM
> +
> +#ifndef EFAULT
> +#define EFAULT 14 /* Bad address */
> +#endif //EFAULT
> +
> +#ifndef EBUSY
> +#define EBUSY 16 /* Device or resource busy */
> +#endif //EBUSY
> +
> +#ifndef EINVAL
> +#define EINVAL 22 /* Invalid argument */
> +#endif //EINVAL
> +
> +#ifndef ENOSPC
> +#define ENOSPC 28 /* No space left on device */
> +#endif //ENOSPC
> +
> +#ifndef EBADSLT
> +#define EBADSLT 57 /* Invalid slot */
> +#endif //EBADSLT
> +
> +#ifndef EPROTO
> +#define EPROTO 71 /* Protocol error */
> +#endif //EPROTO
> +
> +#ifndef EOVERFLOW
> +#define EOVERFLOW 75 /* Value too large for defined data type */
> +#endif //EOVERFLOW
> +
> +#ifndef EOPNOTSUPP
> +#define EOPNOTSUPP 95 /* Operation not supported */
> +#endif //EOPNOTSUPP
> +
> +#ifndef ETIMEDOUT
> +#define ETIMEDOUT 110 /* Connection timed out */
> +#endif //ETIMEDOUT
> +
> +#ifndef EINPROGRESS
> +#define EINPROGRESS 115 /* Operation now in progress */
> +#endif //EINPROGRESS
> +
> +#ifndef EDQUOT
> +#define EDQUOT 122 /* Quota exceeded */
> +#endif //EDQUOT
> +
> +#ifndef ENOTSUP
> +#define ENOTSUP EOPNOTSUPP
> +#endif //ENOTSUP
> +
> +#ifndef ECANCELED
> +#define ECANCELED 126 /* Cancelled */
> +#endif //ECANCELED
> +
> +#endif //REMOVE_OLD_ERRORCODES
> +
> +#define CDN_EOK 0U /* no error */
> +
I would rather see all of these gone also; introducing vendor specific
error codes on top of existing error code framework
(include/linux/errno.h) is a recipe for disaster waiting to happen. That
said, it might be pretty painful to fix all of these...
> +#define CDN_EPERM 1U /* Operation not permitted */
> +
> +#define CDN_ENOENT 2U /* No such file or directory */
> +
> +#define CDN_EIO 5U /* I/O error */
> +
> +#define CDN_ENOEXEC 8U /* Exec format error */
> +
> +#define CDN_EAGAIN 11U /* Try again */
> +
> +#define CDN_ENOMEM 12U /* Out of memory */
> +
> +#define CDN_EFAULT 14U /* Bad address */
> +
> +#define CDN_EBUSY 16U /* Device or resource busy */
> +
> +#define CDN_EINVAL 22U /* Invalid argument */
> +
> +#define CDN_ENOSPC 28U /* No space left on device */
> +
> +#define CDN_EBADSLT 57U /* Invalid slot */
> +
> +#define CDN_EPROTO 71U /* Protocol error */
> +
> +#define CDN_EOVERFLOW 75U /* Value too large for defined data type */
> +
> +#define CDN_EOPNOTSUPP 95U /* Operation not supported */
> +
> +#define CDN_ETIMEDOUT 110U /* Connection timed out */
> +
> +#define CDN_EINPROGRESS 115U /* Operation now in progress */
> +
> +#define CDN_EDQUOT 122U /* Quota exceeded */
> +
> +#define CDN_ENOTSUP CDN_EOPNOTSUPP
> +
> +#define CDN_ECANCELED 126U /* Cancelled */
> +
> +#endif //INCLUDE_CDN_ERRNO_H
> diff --git a/drivers/ram/k3-ddrss/cdn_inttypes.h b/drivers/ram/k3-ddrss/cdn_inttypes.h
> new file mode 100644
> index 000000000000..2e1d376b4a84
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/cdn_inttypes.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef CDN_INTTYPES_H
> +#define CDN_INTTYPES_H
> +
> +#include <inttypes.h>
All of these seem like useless wrapper headers again. Why not use the
real headers in the first place?
> +
> +#endif
> diff --git a/drivers/ram/k3-ddrss/cdn_stdint.h b/drivers/ram/k3-ddrss/cdn_stdint.h
> new file mode 100644
> index 000000000000..2f4fe5d557f8
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/cdn_stdint.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef CDN_STDINT
> +#define CDN_STDINT
> +
> +#include <stdint.h>
> +
> +#endif
> diff --git a/drivers/ram/k3-ddrss/cdn_stdtypes.h b/drivers/ram/k3-ddrss/cdn_stdtypes.h
> new file mode 100644
> index 000000000000..5a150cae5248
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/cdn_stdtypes.h
> @@ -0,0 +1,19 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef INCLUDE_CDN_STDTYPES_H___
> +#define INCLUDE_CDN_STDTYPES_H___
> +#ifdef __KERNEL__
> +#include <linux/types.h>
> +#else
> +#include "cdn_stdint.h"
> +#include <stddef.h>
> +#include <stdbool.h>
> +
> +#endif /* __KERNEL__ */
> +#endif /* INCLUDE_CDN_STDTYPES_H__ */
> diff --git a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
> index 706a5cde01ac..b541719b4ecf 100644
> --- a/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
> +++ b/drivers/ram/k3-ddrss/cps_drv_lpddr4.h
> @@ -1,119 +1,102 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/******************************************************************************
> +/*
> + * Cadence DDR Driver
> *
> - * Copyright (C) 2017-2018 Cadence Design Systems, Inc.
> - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
> - *
> - * cps_drv_lpddr4.h
> - * Interface for the Register Accaess Layer of Cadence Platform Service (CPS)
> - *****************************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef CPS_DRV_H_
> #define CPS_DRV_H_
>
> -#include <stddef.h>
> -#include <inttypes.h>
> +#ifdef DEMO_TB
> +#include <cdn_demo.h>
> +#else
> #include <asm/io.h>
> +#endif
>
> -/**
> - * \brief Read a 32-bit value from memory.
> - * \param reg address of the memory mapped hardware register
> - * \return the value at the given address
> - */
> -#define CPS_REG_READ(reg) (readl((volatile uint32_t*)(reg)))
> +#define CPS_REG_READ(reg) (cps_regread((volatile u32 *)(reg)))
>
> -/**
> - * \brief Write a 32-bit address value to memory.
> - * \param reg address of the memory mapped hardware register
> - * \param value unsigned 32-bit value to write
> - */
> -#define CPS_REG_WRITE(reg, value) (writel((uint32_t)(value), (volatile uint32_t*)(reg)))
> +#define CPS_REG_WRITE(reg, value) (cps_regwrite((volatile u32 *)(reg), (u32)(value)))
>
> -/**
> - * \brief Subtitue the value of fld macro and concatinate with required string
> - * \param fld field name
> - */
> #define CPS_FLD_MASK(fld) (fld ## _MASK)
> #define CPS_FLD_SHIFT(fld) (fld ## _SHIFT)
> #define CPS_FLD_WIDTH(fld) (fld ## _WIDTH)
> #define CPS_FLD_WOCLR(fld) (fld ## _WOCLR)
> #define CPS_FLD_WOSET(fld) (fld ## _WOSET)
>
> -/**
> - * \brief Read a value of bit-field from the register value.
> - * \param reg register name
> - * \param fld field name
> - * \param reg_value register value
> - * \return bit-field value
> - */
> -#define CPS_FLD_READ(fld, reg_value) (cps_fldread((uint32_t)(CPS_FLD_MASK(fld)), \
> - (uint32_t)(CPS_FLD_SHIFT(fld)), \
> - (uint32_t)(reg_value)))
> -
> -/**
> - * \brief Write a value of the bit-field into the register value.
> - * \param reg register name
> - * \param fld field name
> - * \param reg_value register value
> - * \param value value to be written to bit-field
> - * \return modified register value
> - */
> -#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((uint32_t)(CPS_FLD_MASK(fld)), \
> - (uint32_t)(CPS_FLD_SHIFT(fld)), \
> - (uint32_t)(reg_value), (uint32_t)(value)))
> -
> -/**
> - * \brief Set bit within the register value.
> - * \param reg register name
> - * \param fld field name
> - * \param reg_value register value
> - * \return modified register value
> - */
> -#define CPS_FLD_SET(fld, reg_value) (cps_fldset((uint32_t)(CPS_FLD_WIDTH(fld)), \
> - (uint32_t)(CPS_FLD_MASK(fld)), \
> - (uint32_t)(CPS_FLD_WOCLR(fld)), \
> - (uint32_t)(reg_value)))
> +#define CPS_FLD_READ(fld, reg_value) (cps_fldread((u32)(CPS_FLD_MASK(fld)), \
> + (u32)(CPS_FLD_SHIFT(fld)), \
> + (u32)(reg_value)))
>
> -static inline uint32_t cps_fldread(uint32_t mask, uint32_t shift, uint32_t reg_value)
> +#define CPS_FLD_WRITE(fld, reg_value, value) (cps_fldwrite((u32)(CPS_FLD_MASK(fld)), \
> + (u32)(CPS_FLD_SHIFT(fld)), \
> + (u32)(reg_value), (u32)(value)))
> +
> +#define CPS_FLD_SET(fld, reg_value) (cps_fldset((u32)(CPS_FLD_WIDTH(fld)), \
> + (u32)(CPS_FLD_MASK(fld)), \
> + (u32)(CPS_FLD_WOCLR(fld)), \
> + (u32)(reg_value)))
> +
> +#ifdef CLR_USED
> +#define CPS_FLD_CLEAR(reg, fld, reg_value) (CPS_FldClear((u32)(CPS_FLD_WIDTH(fld)), \
> + (u32)(CPS_FLD_MASK(fld)), \
> + (u32)(CPS_FLD_WOSET(fld)), \
> + (u32)(CPS_FLD_WOCLR(fld)), \
> + (u32)(reg_value)))
> +
> +#endif
> +static inline u32 cps_regread(volatile u32 *reg);
> +static inline u32 cps_regread(volatile u32 *reg)
> {
> - uint32_t result = (reg_value & mask) >> shift;
> + return readl(reg);
> +}
>
> - return (result);
> +static inline void cps_regwrite(volatile u32 *reg, u32 value);
> +static inline void cps_regwrite(volatile u32 *reg, u32 value)
> +{
> + writel(value, reg);
> }
>
> -/**
> - * \brief Write a value of the bit-field into the register value.
> - * \param mask mask for the bit-field
> - * \param shift bit-field shift from LSB
> - * \param reg_value register value
> - * \param value value to be written to bit-field
> - * \return modified register value
> - */
> -static inline uint32_t cps_fldwrite(uint32_t mask, uint32_t shift, uint32_t reg_value, uint32_t value)
> +static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value);
> +static inline u32 cps_fldread(u32 mask, u32 shift, u32 reg_value)
> {
> - uint32_t new_value = (value << shift) & mask;
> + u32 result = (reg_value & mask) >> shift;
> +
> + return result;
> +}
> +
> +static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value);
> +static inline u32 cps_fldwrite(u32 mask, u32 shift, u32 reg_value, u32 value)
> +{
> + u32 new_value = (value << shift) & mask;
>
> new_value = (reg_value & ~mask) | new_value;
> - return (new_value);
> + return new_value;
> }
>
> -/**
> - * \brief Set bit within the register value.
> - * \param width width of the bit-field
> - * \param mask mask for the bit-field
> - * \param is_woclr is bit-field has 'write one to clear' flag set
> - * \param reg_value register value
> - * \return modified register value
> - */
> -static inline uint32_t cps_fldset(uint32_t width, uint32_t mask, uint32_t is_woclr, uint32_t reg_value)
> +static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value);
> +static inline u32 cps_fldset(u32 width, u32 mask, u32 is_woclr, u32 reg_value)
> {
> - uint32_t new_value = reg_value;
> - /* Confirm the field to be bit and not write to clear type */
> - if ((width == 1U) && (is_woclr == 0U)) {
> + u32 new_value = reg_value;
> +
> + if ((width == 1U) && (is_woclr == 0U))
> new_value |= mask;
> - }
>
> - return (new_value);
> + return new_value;
> }
> +
> +#ifdef CLR_USED
What is the CLR_USED? Should it be Kconfig? Or should it just be removed?
> +static inline u32 CPS_FldClear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value);
> +static inline u32 CPS_FldClear(u32 width, u32 mask, u32 is_woset, u32 is_woclr, u32 reg_value)
Camel-case looks nasty. Is this actually used anywhere?
> +{
> + u32 new_value = reg_value;
> +
> + if ((width == 1U) && (is_woset == 0U))
> + new_value = (new_value & ~mask) | ((is_woclr != 0U) ? mask : 0U);
> +
> + return new_value;
> +}
> +#endif /* CLR_USED */
> +
> #endif /* CPS_DRV_H_ */
> diff --git a/drivers/ram/k3-ddrss/k3-j721e-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
> similarity index 60%
> rename from drivers/ram/k3-ddrss/k3-j721e-ddrss.c
> rename to drivers/ram/k3-ddrss/k3-ddrss.c
> index 9fb1eeea454d..01a319533097 100644
> --- a/drivers/ram/k3-ddrss/k3-j721e-ddrss.c
> +++ b/drivers/ram/k3-ddrss/k3-ddrss.c
> @@ -1,20 +1,20 @@
> // SPDX-License-Identifier: GPL-2.0+
> /*
> - * Texas Instruments' J721E DDRSS driver
> + * Texas Instruments' K3 DDRSS driver
> *
> - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
> + * Copyright (C) 2020-2021 Texas Instruments Incorporated - http://www.ti.com/
> */
>
> #include <common.h>
> #include <clk.h>
> #include <dm.h>
> +#include <dm/device_compat.h>
> +#include <ram.h>
> #include <hang.h>
> #include <log.h>
> -#include <ram.h>
> #include <asm/io.h>
> #include <power-domain.h>
> #include <wait_bit.h>
> -#include <dm/device_compat.h>
>
> #include "lpddr4_obj_if.h"
> #include "lpddr4_if.h"
> @@ -26,7 +26,7 @@
> #define CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS 0x80
> #define CTRLMMR_DDR4_FSP_CLKCHNG_ACK_OFFS 0xc0
>
> -struct j721e_ddrss_desc {
> +struct k3_ddrss_desc {
> struct udevice *dev;
> void __iomem *ddrss_ss_cfg;
> void __iomem *ddrss_ctrl_mmr;
> @@ -39,11 +39,20 @@ struct j721e_ddrss_desc {
> u32 ddr_fhs_cnt;
> };
>
> -static LPDDR4_OBJ *driverdt;
> +static lpddr4_obj *driverdt;
> static lpddr4_config config;
> static lpddr4_privatedata pd;
>
> -static struct j721e_ddrss_desc *ddrss;
> +static struct k3_ddrss_desc *ddrss;
> +
> +struct reginitdata {
> + u32 ctl_regs[LPDDR4_INTR_CTL_REG_COUNT];
> + u16 ctl_regs_offs[LPDDR4_INTR_CTL_REG_COUNT];
> + u32 pi_regs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
> + u16 pi_regs_offs[LPDDR4_INTR_PHY_INDEP_REG_COUNT];
> + u32 phy_regs[LPDDR4_INTR_PHY_REG_COUNT];
> + u16 phy_regs_offs[LPDDR4_INTR_PHY_REG_COUNT];
> +};
>
> #define TH_MACRO_EXP(fld, str) (fld##str)
>
> @@ -56,21 +65,46 @@ static struct j721e_ddrss_desc *ddrss;
> #define str(s) #s
> #define xstr(s) str(s)
>
> -#define CTL_SHIFT 11
> -#define PHY_SHIFT 11
> -#define PI_SHIFT 10
> +#define CTL_SHIFT 11
> +#define PHY_SHIFT 11
> +#define PI_SHIFT 10
> +
> +#define DENALI_CTL_0_DRAM_CLASS_DDR4 0xA
> +#define DENALI_CTL_0_DRAM_CLASS_LPDDR4 0xB
>
> #define TH_OFFSET_FROM_REG(REG, SHIFT, offset) do {\
> - char *i, *pstr= xstr(REG); offset = 0;\
> + char *i, *pstr = xstr(REG); offset = 0;\
> for (i = &pstr[SHIFT]; *i != '\0'; ++i) {\
> - offset = offset * 10 + (*i - '0'); }\
> + offset = offset * 10 + (*i - '0'); } \
> } while (0)
>
> -static void j721e_lpddr4_ack_freq_upd_req(void)
> +static u32 k3_lpddr4_read_ddr_type(void)
> {
> - unsigned int req_type, counter;
> + u32 status = 0U;
> + u32 offset = 0U;
> + u32 regval = 0U;
> + u32 dram_class = 0U;
>
> - debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
> + TH_OFFSET_FROM_REG(LPDDR4__DRAM_CLASS__REG, CTL_SHIFT, offset);
> + status = driverdt->readreg(&pd, LPDDR4_CTL_REGS, offset, ®val);
> + if (status > 0U) {
> + printf("%s: Failed to read DRAM_CLASS\n", __func__);
> + hang();
> + }
> +
> + dram_class = ((regval & TH_FLD_MASK(LPDDR4__DRAM_CLASS__FLD)) >>
> + TH_FLD_SHIFT(LPDDR4__DRAM_CLASS__FLD));
> + return dram_class;
> +}
> +
> +static void k3_ddr4_freq_update(void)
> +{
> + clk_set_rate(&ddrss->ddr_clk, ddrss->ddr_freq1);
> +}
> +
> +static void k3_lpddr4_freq_update(void)
> +{
> + unsigned int req_type, counter;
>
> for (counter = 0; counter < ddrss->ddr_fhs_cnt; counter++) {
> if (wait_for_bit_le32(ddrss->ddrss_ctrl_mmr +
> @@ -83,7 +117,7 @@ static void j721e_lpddr4_ack_freq_upd_req(void)
> req_type = readl(ddrss->ddrss_ctrl_mmr +
> CTRLMMR_DDR4_FSP_CLKCHNG_REQ_OFFS) & 0x03;
>
> - debug("%s: received freq change req: req type = %d, req no. = %d \n",
> + debug("%s: received freq change req: req type = %d, req no. = %d\n",
> __func__, req_type, counter);
>
> if (req_type == 1)
> @@ -110,15 +144,34 @@ static void j721e_lpddr4_ack_freq_upd_req(void)
> }
> }
>
> -static void j721e_lpddr4_info_handler(const lpddr4_privatedata * pd,
> - lpddr4_infotype infotype)
> +static void k3_lpddr4_ack_freq_upd_req(void)
> {
> - if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE) {
> - j721e_lpddr4_ack_freq_upd_req();
> + u32 dram_class;
> +
> + debug("--->>> LPDDR4 Initialization is in progress ... <<<---\n");
> +
> + dram_class = k3_lpddr4_read_ddr_type();
> +
> + switch (dram_class) {
> + case DENALI_CTL_0_DRAM_CLASS_DDR4:
> + k3_ddr4_freq_update();
> + break;
> + case DENALI_CTL_0_DRAM_CLASS_LPDDR4:
> + k3_lpddr4_freq_update();
> + break;
> + default:
> + printf("Unrecognized dram_class cannot update frequency!\n");
> }
> }
>
> -static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
> +static void k3_lpddr4_info_handler(const lpddr4_privatedata *pd,
> + lpddr4_infotype infotype)
> +{
> + if (infotype == LPDDR4_DRV_SOC_PLL_UPDATE)
> + k3_lpddr4_ack_freq_upd_req();
> +}
> +
> +static int k3_ddrss_power_on(struct k3_ddrss_desc *ddrss)
> {
> int ret;
>
> @@ -139,9 +192,9 @@ static int j721e_ddrss_power_on(struct j721e_ddrss_desc *ddrss)
> return 0;
> }
>
> -static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
> +static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
> {
> - struct j721e_ddrss_desc *ddrss = dev_get_priv(dev);
> + struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
> phys_addr_t reg;
> int ret;
>
> @@ -195,16 +248,18 @@ static int j721e_ddrss_ofdata_to_priv(struct udevice *dev)
>
> /* Put DDR pll in bypass mode */
> ret = clk_set_rate(&ddrss->ddr_clk, clk_get_rate(&ddrss->osc_clk));
> - if (ret)
> - dev_err(dev, "ddr clk bypass failed\n");
> + if (ret < 0)
> + dev_err(dev, "ddr clk bypass failed: %d\n", ret);
> + else
> + ret = 0;
>
> return ret;
> }
>
> -void j721e_lpddr4_probe(void)
> +void k3_lpddr4_probe(void)
> {
> - uint32_t status = 0U;
> - uint16_t configsize = 0U;
> + u32 status = 0U;
> + u16 configsize = 0U;
>
> status = driverdt->probe(&config, &configsize);
>
> @@ -217,9 +272,9 @@ void j721e_lpddr4_probe(void)
> }
> }
>
> -void j721e_lpddr4_init(void)
> +void k3_lpddr4_init(void)
> {
> - uint32_t status = 0U;
> + u32 status = 0U;
>
> if ((sizeof(pd) != sizeof(lpddr4_privatedata))
> || (sizeof(pd) > SRAM_MAX)) {
> @@ -228,7 +283,7 @@ void j721e_lpddr4_init(void)
> }
>
> config.ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
> - config.infohandler = (lpddr4_infocallback) j721e_lpddr4_info_handler;
> + config.infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
>
> status = driverdt->init(&pd, &config);
>
> @@ -236,72 +291,74 @@ void j721e_lpddr4_init(void)
> (pd.ctlbase != (struct lpddr4_ctlregs_s *)config.ctlbase) ||
> (pd.ctlinterrupthandler != config.ctlinterrupthandler) ||
> (pd.phyindepinterrupthandler != config.phyindepinterrupthandler)) {
> - printf("LPDDR4_Init: FAIL\n");
> + printf("lpddr4_init: FAIL\n");
> hang();
> } else {
> debug("LPDDR4_Init: PASS\n");
> }
> }
>
> -void populate_data_array_from_dt(lpddr4_reginitdata * reginit_data)
> +void populate_data_array_from_dt(struct reginitdata *reginit_data)
> {
> int ret, i;
>
> ret = dev_read_u32_array(ddrss->dev, "ti,ctl-data",
> - (u32 *) reginit_data->denalictlreg,
> - LPDDR4_CTL_REG_COUNT);
> + (u32 *)reginit_data->ctl_regs,
> + LPDDR4_INTR_CTL_REG_COUNT);
> if (ret)
> - printf("Error reading ctrl data\n");
> + printf("Error reading ctrl data %d\n", ret);
>
> - for (i = 0; i < LPDDR4_CTL_REG_COUNT; i++)
> - reginit_data->updatectlreg[i] = true;
> + for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++)
> + reginit_data->ctl_regs_offs[i] = i;
>
> ret = dev_read_u32_array(ddrss->dev, "ti,pi-data",
> - (u32 *) reginit_data->denaliphyindepreg,
> - LPDDR4_PHY_INDEP_REG_COUNT);
> + (u32 *)reginit_data->pi_regs,
> + LPDDR4_INTR_PHY_INDEP_REG_COUNT);
> if (ret)
> printf("Error reading PI data\n");
>
> - for (i = 0; i < LPDDR4_PHY_INDEP_REG_COUNT; i++)
> - reginit_data->updatephyindepreg[i] = true;
> + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++)
> + reginit_data->pi_regs_offs[i] = i;
>
> ret = dev_read_u32_array(ddrss->dev, "ti,phy-data",
> - (u32 *) reginit_data->denaliphyreg,
> - LPDDR4_PHY_REG_COUNT);
> + (u32 *)reginit_data->phy_regs,
> + LPDDR4_INTR_PHY_REG_COUNT);
> if (ret)
> - printf("Error reading PHY data\n");
> + printf("Error reading PHY data %d\n", ret);
>
> - for (i = 0; i < LPDDR4_PHY_REG_COUNT; i++)
> - reginit_data->updatephyreg[i] = true;
> + for (i = 0; i < LPDDR4_INTR_PHY_REG_COUNT; i++)
> + reginit_data->phy_regs_offs[i] = i;
> }
>
> -void j721e_lpddr4_hardware_reg_init(void)
> +void k3_lpddr4_hardware_reg_init(void)
> {
> - uint32_t status = 0U;
> - lpddr4_reginitdata reginitdata;
> + u32 status = 0U;
> + struct reginitdata reginitdata;
>
> populate_data_array_from_dt(®initdata);
>
> - status = driverdt->writectlconfig(&pd, ®initdata);
> - if (!status) {
> - status = driverdt->writephyindepconfig(&pd, ®initdata);
> - }
> - if (!status) {
> - status = driverdt->writephyconfig(&pd, ®initdata);
> - }
> + status = driverdt->writectlconfig(&pd, reginitdata.ctl_regs,
> + reginitdata.ctl_regs_offs,
> + LPDDR4_INTR_CTL_REG_COUNT);
> + if (!status)
> + status = driverdt->writephyindepconfig(&pd, reginitdata.pi_regs,
> + reginitdata.pi_regs_offs,
> + LPDDR4_INTR_PHY_INDEP_REG_COUNT);
> + if (!status)
> + status = driverdt->writephyconfig(&pd, reginitdata.phy_regs,
> + reginitdata.phy_regs_offs,
> + LPDDR4_INTR_PHY_REG_COUNT);
> if (status) {
> printf(" ERROR: LPDDR4_HardwareRegInit failed!!\n");
Use actual function name above?
> hang();
> }
> -
> - return;
> }
>
> -void j721e_lpddr4_start(void)
> +void k3_lpddr4_start(void)
> {
> - uint32_t status = 0U;
> - uint32_t regval = 0U;
> - uint32_t offset = 0U;
> + u32 status = 0U;
> + u32 regval = 0U;
> + u32 offset = 0U;
>
> TH_OFFSET_FROM_REG(LPDDR4__START__REG, CTL_SHIFT, offset);
>
> @@ -326,50 +383,51 @@ void j721e_lpddr4_start(void)
> }
> }
>
> -static int j721e_ddrss_probe(struct udevice *dev)
> +static int k3_ddrss_probe(struct udevice *dev)
> {
> int ret;
> +
> ddrss = dev_get_priv(dev);
>
> debug("%s(dev=%p)\n", __func__, dev);
>
> - ret = j721e_ddrss_ofdata_to_priv(dev);
> + ret = k3_ddrss_ofdata_to_priv(dev);
> if (ret)
> return ret;
>
> ddrss->dev = dev;
> - ret = j721e_ddrss_power_on(ddrss);
> + ret = k3_ddrss_power_on(ddrss);
> if (ret)
> return ret;
>
> driverdt = lpddr4_getinstance();
> - j721e_lpddr4_probe();
> - j721e_lpddr4_init();
> - j721e_lpddr4_hardware_reg_init();
> - j721e_lpddr4_start();
> + k3_lpddr4_probe();
> + k3_lpddr4_init();
> + k3_lpddr4_hardware_reg_init();
> + k3_lpddr4_start();
>
> return ret;
> }
>
> -static int j721e_ddrss_get_info(struct udevice *dev, struct ram_info *info)
> +static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
> {
> return 0;
> }
>
> -static struct ram_ops j721e_ddrss_ops = {
> - .get_info = j721e_ddrss_get_info,
> +static struct ram_ops k3_ddrss_ops = {
> + .get_info = k3_ddrss_get_info,
> };
>
> -static const struct udevice_id j721e_ddrss_ids[] = {
> +static const struct udevice_id k3_ddrss_ids[] = {
> {.compatible = "ti,j721e-ddrss"},
> {}
> };
>
> -U_BOOT_DRIVER(j721e_ddrss) = {
> - .name = "j721e_ddrss",
> - .id = UCLASS_RAM,
> - .of_match = j721e_ddrss_ids,
> - .ops = &j721e_ddrss_ops,
> - .probe = j721e_ddrss_probe,
> - .priv_auto = sizeof(struct j721e_ddrss_desc),
> +U_BOOT_DRIVER(k3_ddrss) = {
> + .name = "k3_ddrss",
> + .id = UCLASS_RAM,
> + .of_match = k3_ddrss_ids,
> + .ops = &k3_ddrss_ops,
> + .probe = k3_ddrss_probe,
> + .priv_auto = sizeof(struct k3_ddrss_desc),
> };
> diff --git a/drivers/ram/k3-ddrss/lpddr4.c b/drivers/ram/k3-ddrss/lpddr4.c
> index 68043d7cb615..290dafb3691e 100644
> --- a/drivers/ram/k3-ddrss/lpddr4.c
> +++ b/drivers/ram/k3-ddrss/lpddr4.c
> @@ -1,144 +1,124 @@
> // SPDX-License-Identifier: BSD-3-Clause
> -/******************************************************************************
> - * Copyright (C) 2012-2018 Cadence Design Systems, Inc.
> - * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
> +/*
> + * Cadence DDR Driver
> *
> - * lpddr4.c
> - *
> - *****************************************************************************
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
> +
> +#include <cdn_errno.h>
> +
> #include "cps_drv_lpddr4.h"
> -#include "lpddr4_ctl_regs.h"
> #include "lpddr4_if.h"
> -#include "lpddr4_private.h"
> -#include "lpddr4_sanity.h"
> +#include "lpddr4.h"
> #include "lpddr4_structs_if.h"
>
> +#ifndef LPDDR4_CUSTOM_TIMEOUT_DELAY
> #define LPDDR4_CUSTOM_TIMEOUT_DELAY 100000000U
> -
> -/**
> - * Internal Function:Poll for status of interrupt received by the Controller.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] irqBit Interrupt status bit to be checked.
> - * @param[in] delay time delay.
> - * @return CDN_EOK on success (Interrupt status high).
> - * @return EIO on poll time out.
> - * @return EINVAL checking status was not successful.
> - */
> -static uint32_t lpddr4_pollctlirq(const lpddr4_privatedata * pd,
> - lpddr4_ctlinterrupt irqbit, uint32_t delay)
> -{
> -
> - uint32_t result = 0U;
> - uint32_t timeout = 0U;
> +#endif
> +
> +#ifndef LPDDR4_CPS_NS_DELAY_TIME
> +#define LPDDR4_CPS_NS_DELAY_TIME 10000000U
> +#endif
> +
> +static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay);
> +static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd);
> +static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd);
> +static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval);
> +static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
> +static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
> +static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
> +static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
> +static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits);
> +static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
> +static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
> +static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
> +static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
> +static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
> +static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
> +static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
> +static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
> +static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles);
> +static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
> +static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
> +static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
> +static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
> +static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
> +static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
> +static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
> +static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles);
> +static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
> +static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
> +static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
> +static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max);
> +#ifdef REG_WRITE_VERIF
> +static u32 lpddr4_getphyrwmask(u32 regoffset);
> +static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
> +#endif
> +
> +u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay)
All of these are kind of painful, not sure if you want to modify them,
but having standard u-boot error handling would be really nice. So,
changing any prototypes like this to return "int" instead of "u32", and
return standard error.
> +{
> + u32 result = 0U;
int result = 0;
> + u32 timeout = 0U;
> bool irqstatus = false;
>
> - /* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
> do {
> if (++timeout == delay) {
> - result = EIO;
> + result = (u32)CDN_EIO;
result = -EIO.
> break;
> }
> - /* cps_delayns(10000000U); */
> result = lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus);
> - } while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
> + } while ((irqstatus == (bool)false) && (result == (u32)CDN_EOK));
>
> return result;
> }
>
> -/**
> - * Internal Function:Poll for status of interrupt received by the PHY Independent Module.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] irqBit Interrupt status bit to be checked.
> - * @param[in] delay time delay.
> - * @return CDN_EOK on success (Interrupt status high).
> - * @return EIO on poll time out.
> - * @return EINVAL checking status was not successful.
> - */
> -static uint32_t lpddr4_pollphyindepirq(const lpddr4_privatedata * pd,
> - lpddr4_phyindepinterrupt irqbit,
> - uint32_t delay)
> +static u32 lpddr4_pollphyindepirq(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt irqbit, u32 delay)
> {
> -
> - uint32_t result = 0U;
> - uint32_t timeout = 0U;
> + u32 result = 0U;
> + u32 timeout = 0U;
> bool irqstatus = false;
>
> - /* Loop until irqStatus found to be 1 or if value of 'result' !=CDN_EOK */
> do {
> if (++timeout == delay) {
> - result = EIO;
> + result = (u32)CDN_EIO;
> break;
> }
> - /* cps_delayns(10000000U); */
> result = lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus);
> - } while ((irqstatus == false) && (result == (uint32_t) CDN_EOK));
> + } while ((irqstatus == (bool)false) && (result == (u32)CDN_EOK));
>
> return result;
> }
>
> -/**
> - * Internal Function:Trigger function to poll and Ack IRQs
> - * @param[in] pD Driver state info specific to this instance.
> - * @return CDN_EOK on success (Interrupt status high).
> - * @return EIO on poll time out.
> - * @return EINVAL checking status was not successful.
> - */
> -static uint32_t lpddr4_pollandackirq(const lpddr4_privatedata * pd)
> +static u32 lpddr4_pollandackirq(const lpddr4_privatedata *pd)
> {
> - uint32_t result = 0U;
> -
> - /* Wait for PhyIndependent module to finish up ctl init sequence */
> - result =
> - lpddr4_pollphyindepirq(pd, LPDDR4_PHY_INDEP_INIT_DONE_BIT,
> - LPDDR4_CUSTOM_TIMEOUT_DELAY);
> -
> - /* Ack to clear the PhyIndependent interrupt bit */
> - if (result == (uint32_t) CDN_EOK) {
> - result =
> - lpddr4_ackphyindepinterrupt(pd,
> - LPDDR4_PHY_INDEP_INIT_DONE_BIT);
> - }
> - /* Wait for the CTL end of initialization */
> - if (result == (uint32_t) CDN_EOK) {
> - result =
> - lpddr4_pollctlirq(pd, LPDDR4_MC_INIT_DONE,
> - LPDDR4_CUSTOM_TIMEOUT_DELAY);
> - }
> - /* Ack to clear the Ctl interrupt bit */
> - if (result == (uint32_t) CDN_EOK) {
> - result = lpddr4_ackctlinterrupt(pd, LPDDR4_MC_INIT_DONE);
> - }
> + u32 result = 0U;
> +
> + result = lpddr4_pollphyindepirq(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT, LPDDR4_CUSTOM_TIMEOUT_DELAY);
> +
> + if (result == (u32)CDN_EOK)
> + result = lpddr4_ackphyindepinterrupt(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT);
> + if (result == (u32)CDN_EOK)
> + result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MC_INIT_DONE, LPDDR4_CUSTOM_TIMEOUT_DELAY);
> + if (result == (u32)CDN_EOK)
> + result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MC_INIT_DONE);
> return result;
> }
>
> -/**
> - * Internal Function: Controller start sequence.
> - * @param[in] pD Driver state info specific to this instance.
> - * @return CDN_EOK on success.
> - * @return EINVAL starting controller was not successful.
> - */
> -static uint32_t lpddr4_startsequencecontroller(const lpddr4_privatedata * pd)
> +static u32 lpddr4_startsequencecontroller(const lpddr4_privatedata *pd)
> {
> - uint32_t result = 0U;
> - uint32_t regval = 0U;
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> + u32 result = 0U;
> + u32 regval = 0U;
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> lpddr4_infotype infotype;
>
> - /* Set the PI_start to initiate leveling procedure */
> - regval =
> - CPS_FLD_SET(LPDDR4__PI_START__FLD,
> - CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
> + regval = CPS_FLD_SET(LPDDR4__PI_START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_START__REG)));
> CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_START__REG)), regval);
>
> - /* Set the Ctl_start */
> - regval =
> - CPS_FLD_SET(LPDDR4__START__FLD,
> - CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
> + regval = CPS_FLD_SET(LPDDR4__START__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__START__REG)));
> CPS_REG_WRITE(&(ctlregbase->LPDDR4__START__REG), regval);
>
> - if (pd->infohandler != NULL) {
> - /* If a handler is registered, call it with the relevant information type */
> + if (pd->infohandler != (lpddr4_infocallback)NULL) {
> infotype = LPDDR4_DRV_SOC_PLL_UPDATE;
> pd->infohandler(pd, infotype);
> }
> @@ -148,1958 +128,952 @@ static uint32_t lpddr4_startsequencecontroller(const lpddr4_privatedata * pd)
> return result;
> }
>
> -/**
> - * Internal Function: To add the offset to given address.
> - * @param[in] addr Address to which the offset has to be added.
> - * @param[in] regOffset The offset
> - * @return regAddr The address value after the summation.
> - */
> -static volatile uint32_t *lpddr4_addoffset(volatile uint32_t * addr,
> - uint32_t regoffset)
> +volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset)
> {
> + volatile u32 *local_addr = addr;
> + volatile u32 *regaddr = &local_addr[regoffset];
>
> - volatile uint32_t *local_addr = addr;
> - /* Declaring as array to add the offset value. */
> - volatile uint32_t *regaddr = &local_addr[regoffset];
> return regaddr;
> }
>
> -/**
> - * Checks configuration object.
> - * @param[in] config Driver/hardware configuration required.
> - * @param[out] configSize Size of memory allocations required.
> - * @return CDN_EOK on success (requirements structure filled).
> - * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
> - */
> -uint32_t lpddr4_probe(const lpddr4_config * config, uint16_t * configsize)
> +u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize)
> {
> - uint32_t result;
> + u32 result;
>
> - result = (uint32_t) (lpddr4_probesf(config, configsize));
> - if (result == (uint32_t) CDN_EOK) {
> - *configsize = (uint16_t) (sizeof(lpddr4_privatedata));
> - }
> + result = (u32)(lpddr4_probesf(config, configsize));
> + if (result == (u32)CDN_EOK)
> + *configsize = (u16)(sizeof(lpddr4_privatedata));
> return result;
> }
>
> -/**
> - * Init function to be called after LPDDR4_probe() to set up the driver configuration.
> - * Memory should be allocated for drv_data (using the size determined using LPDDR4_probe) before
> - * calling this API, init_settings should be initialized with base addresses for PHY Independent Module,
> - * Controller and PHY before calling this function.
> - * If callbacks are required for interrupt handling, these should also be configured in init_settings.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cfg Specifies driver/hardware configuration.
> - * @return CDN_EOK on success
> - * @return EINVAL if illegal/inconsistent values in cfg.
> - * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s)
> - * required by 'config' parameters.
> - */
> -uint32_t lpddr4_init(lpddr4_privatedata * pd, const lpddr4_config * cfg)
> +u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg)
> {
> - uint32_t result = 0U;
> - uint16_t productid = 0U;
> + u32 result = 0U;
>
> result = lpddr4_initsf(pd, cfg);
> - if (result == (uint32_t) CDN_EOK) {
> - /* Validate Magic number */
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) cfg->ctlbase;
> - productid = (uint16_t) (CPS_FLD_READ(LPDDR4__CONTROLLER_ID__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__CONTROLLER_ID__REG))));
> - if (productid == PRODUCT_ID) {
> - /* Populating configuration data to pD */
> - pd->ctlbase = ctlregbase;
> - pd->infohandler =
> - (lpddr4_infocallback) cfg->infohandler;
> - pd->ctlinterrupthandler =
> - (lpddr4_ctlcallback) cfg->ctlinterrupthandler;
> - pd->phyindepinterrupthandler =
> - (lpddr4_phyindepcallback) cfg->
> - phyindepinterrupthandler;
> - } else {
> - /* Magic number validation failed - Driver doesn't support given IP version */
> - result = (uint32_t) EOPNOTSUPP;
> - }
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)cfg->ctlbase;
> + pd->ctlbase = ctlregbase;
> + pd->infohandler = (lpddr4_infocallback)cfg->infohandler;
> + pd->ctlinterrupthandler = (lpddr4_ctlcallback)cfg->ctlinterrupthandler;
> + pd->phyindepinterrupthandler = (lpddr4_phyindepcallback)cfg->phyindepinterrupthandler;
> }
> return result;
> }
>
> -/**
> - * Start the driver.
> - * @param[in] pD Driver state info specific to this instance.
> - */
> -uint32_t lpddr4_start(const lpddr4_privatedata * pd)
> +u32 lpddr4_start(const lpddr4_privatedata *pd)
> {
> - uint32_t result = 0U;
> - uint32_t regval = 0U;
> + u32 result = 0U;
>
> result = lpddr4_startsf(pd);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Enable PI as the initiator for DRAM */
> - regval =
> - CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__PI_INIT_LVL_EN__REG)));
> - regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
> - CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)),
> - regval);
> -
> - /* Start PI init sequence. */
> + if (result == (u32)CDN_EOK) {
> + result = lpddr4_enablepiinitiator(pd);
> result = lpddr4_startsequencecontroller(pd);
> }
> return result;
> }
>
> -/**
> - * Read a register from the controller, PHY or PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
> - * @param[in] regOffset Register offset
> - * @param[out] regValue Register value read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regOffset if out of range or regValue is NULL
> - */
> -uint32_t lpddr4_readreg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
> - uint32_t regoffset, uint32_t * regvalue)
> +u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue)
> {
> - uint32_t result = 0U;
> + u32 result = 0U;
>
> result = lpddr4_readregsf(pd, cpp, regvalue);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
>
> if (cpp == LPDDR4_CTL_REGS) {
> - if (regoffset >= LPDDR4_CTL_REG_COUNT) {
> - /* Return if user provider invalid register number */
> - result = EINVAL;
> - } else {
> - *regvalue =
> - CPS_REG_READ(lpddr4_addoffset
> - (&(ctlregbase->DENALI_CTL_0),
> - regoffset));
> - }
> + if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
> + result = (u32)CDN_EINVAL;
> + else
> + *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset));
> } else if (cpp == LPDDR4_PHY_REGS) {
> - if (regoffset >= LPDDR4_PHY_REG_COUNT) {
> - /* Return if user provider invalid register number */
> - result = EINVAL;
> - } else {
> - *regvalue =
> - CPS_REG_READ(lpddr4_addoffset
> - (&(ctlregbase->DENALI_PHY_0),
> - regoffset));
> - }
> + if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
> + result = (u32)CDN_EINVAL;
> + else
> + *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset));
>
> } else {
> - if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
> - /* Return if user provider invalid register number */
> - result = EINVAL;
> - } else {
> - *regvalue =
> - CPS_REG_READ(lpddr4_addoffset
> - (&(ctlregbase->DENALI_PI_0),
> - regoffset));
> - }
> + if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
> + result = (u32)CDN_EINVAL;
> + else
> + *regvalue = CPS_REG_READ(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset));
> }
> }
> return result;
> }
>
> -uint32_t lpddr4_writereg(const lpddr4_privatedata * pd, lpddr4_regblock cpp,
> - uint32_t regoffset, uint32_t regvalue)
> +#ifdef REG_WRITE_VERIF
> +
> +static u32 lpddr4_getphyrwmask(u32 regoffset)
> {
> - uint32_t result = 0U;
> + u32 rwmask = 0U;
> + u32 arrayoffset = 0U;
> + u32 slicenum, sliceoffset = 0U;
>
> - result = lpddr4_writeregsf(pd, cpp);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> + for (slicenum = (u32)0U; slicenum <= (DSLICE_NUM + ASLICE_NUM); slicenum++) {
> + sliceoffset = sliceoffset + (u32)SLICE_WIDTH;
> + if (regoffset < sliceoffset)
> + break;
> + }
> + arrayoffset = regoffset - (sliceoffset - (u32)SLICE_WIDTH);
>
> - if (cpp == LPDDR4_CTL_REGS) {
> - if (regoffset >= LPDDR4_CTL_REG_COUNT) {
> - /* Return if user provider invalid register number */
> - result = EINVAL;
> - } else {
> - CPS_REG_WRITE(lpddr4_addoffset
> - (&(ctlregbase->DENALI_CTL_0),
> - regoffset), regvalue);
> - }
> - } else if (cpp == LPDDR4_PHY_REGS) {
> - if (regoffset >= LPDDR4_PHY_REG_COUNT) {
> - /* Return if user provider invalid register number */
> - result = EINVAL;
> - } else {
> - CPS_REG_WRITE(lpddr4_addoffset
> - (&(ctlregbase->DENALI_PHY_0),
> - regoffset), regvalue);
> - }
> + if (slicenum < DSLICE_NUM) {
> + rwmask = lpddr4_getdslicemask(slicenum, arrayoffset);
> + } else {
> + if (slicenum == DSLICE_NUM) {
> + if (arrayoffset < ASLICE0_REG_COUNT)
> + rwmask = g_lpddr4_address_slice_0_rw_mask[arrayoffset];
> } else {
> - if (regoffset >= LPDDR4_PHY_INDEP_REG_COUNT) {
> - /* Return if user provider invalid register number */
> - result = EINVAL;
> - } else {
> - CPS_REG_WRITE(lpddr4_addoffset
> - (&(ctlregbase->DENALI_PI_0),
> - regoffset), regvalue);
> - }
> + if (arrayoffset < PHY_CORE_REG_COUNT)
> + rwmask = g_lpddr4_phy_core_rw_mask[arrayoffset];
> }
> }
> + return rwmask;
> +}
> +
> +static u32 lpddr4_verifyregwrite(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
> +{
> + u32 result = (u32)CDN_EOK;
> + u32 regreadval = 0U;
> + u32 rwmask = 0U;
> +
> + result = lpddr4_readreg(pd, cpp, regoffset, ®readval);
>
> + if (result == (u32)CDN_EOK) {
> + switch (cpp) {
> + case LPDDR4_PHY_INDEP_REGS:
> + rwmask = g_lpddr4_pi_rw_mask[regoffset];
> + break;
> + case LPDDR4_PHY_REGS:
> + rwmask = lpddr4_getphyrwmask(regoffset);
> + break;
> + default:
> + rwmask = g_lpddr4_ddr_controller_rw_mask[regoffset];
> + break;
> + }
> +
> + if ((rwmask & regreadval) != (regvalue & rwmask))
> + result = CDN_EIO;
> + }
> return result;
> }
> +#endif
>
> -static uint32_t lpddr4_checkmmrreaderror(const lpddr4_privatedata * pd,
> - uint64_t * mmrvalue,
> - uint8_t * mrrstatus)
> +u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue)
> {
> + u32 result = 0U;
>
> - uint64_t lowerdata;
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - uint32_t result = (uint32_t) CDN_EOK;
> -
> - /* Check if mode register read error interrupt occurred */
> - if (lpddr4_pollctlirq(pd, LPDDR4_MRR_ERROR, 100) == 0U) {
> - /* Mode register read error interrupt, read MRR status register and return. */
> - *mrrstatus =
> - (uint8_t) CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__MRR_ERROR_STATUS__REG)));
> - *mmrvalue = 0;
> - result = EIO;
> - } else {
> - *mrrstatus = 0;
> - /* Mode register read was successful, read DATA */
> - lowerdata =
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
> - *mmrvalue =
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
> - *mmrvalue = (uint64_t) ((*mmrvalue << WORD_SHIFT) | lowerdata);
> - /* Acknowledge MR_READ_DONE interrupt to clear it */
> - result = lpddr4_ackctlinterrupt(pd, LPDDR4_MR_READ_DONE);
> + result = lpddr4_writeregsf(pd, cpp);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + if (cpp == LPDDR4_CTL_REGS) {
> + if (regoffset >= LPDDR4_INTR_CTL_REG_COUNT)
> + result = (u32)CDN_EINVAL;
> + else
> + CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_CTL_0), regoffset), regvalue);
> + } else if (cpp == LPDDR4_PHY_REGS) {
> + if (regoffset >= LPDDR4_INTR_PHY_REG_COUNT)
> + result = (u32)CDN_EINVAL;
> + else
> + CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PHY_0), regoffset), regvalue);
> + } else {
> + if (regoffset >= LPDDR4_INTR_PHY_INDEP_REG_COUNT)
> + result = (u32)CDN_EINVAL;
> + else
> + CPS_REG_WRITE(lpddr4_addoffset(&(ctlregbase->DENALI_PI_0), regoffset), regvalue);
> + }
> }
> +#ifdef REG_WRITE_VERIF
> + if (result == (u32)CDN_EOK)
> + result = lpddr4_verifyregwrite(pd, cpp, regoffset, regvalue);
> +
> +#endif
> +
> return result;
> }
>
> -uint32_t lpddr4_getmmrregister(const lpddr4_privatedata * pd,
> - uint32_t readmoderegval, uint64_t * mmrvalue,
> - uint8_t * mmrstatus)
> +u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus)
> {
> -
> - uint32_t result = 0U;
> - uint32_t tdelay = 1000U;
> - uint32_t regval = 0U;
> + u32 result = 0U;
> + u32 tdelay = 1000U;
> + u32 regval = 0U;
>
> result = lpddr4_getmmrregistersf(pd, mmrvalue, mmrstatus);
> - if (result == (uint32_t) CDN_EOK) {
> -
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
>
> - /* Populate the calculated value to the register */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__READ_MODEREG__REG)),
> - readmoderegval);
> + regval = CPS_FLD_WRITE(LPDDR4__READ_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__READ_MODEREG__REG)), readmoderegval);
> CPS_REG_WRITE(&(ctlregbase->LPDDR4__READ_MODEREG__REG), regval);
>
> - /* Wait until the Read is done */
> - result = lpddr4_pollctlirq(pd, LPDDR4_MR_READ_DONE, tdelay);
> + result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_READ_DONE, tdelay);
> }
> - if (result == (uint32_t) CDN_EOK) {
> + if (result == (u32)CDN_EOK)
> result = lpddr4_checkmmrreaderror(pd, mmrvalue, mmrstatus);
> - }
> return result;
> }
>
> -static uint32_t lpddr4_writemmrregister(const lpddr4_privatedata * pd,
> - uint32_t writemoderegval)
> +static u32 lpddr4_writemmrregister(const lpddr4_privatedata *pd, u32 writemoderegval)
> {
> + u32 result = (u32)CDN_EOK;
> + u32 tdelay = 1000U;
> + u32 regval = 0U;
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
>
> - uint32_t result = (uint32_t) CDN_EOK;
> - uint32_t tdelay = 1000U;
> - uint32_t regval = 0U;
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Populate the calculated value to the register */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__WRITE_MODEREG__REG)),
> - writemoderegval);
> + regval = CPS_FLD_WRITE(LPDDR4__WRITE_MODEREG__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG)), writemoderegval);
> CPS_REG_WRITE(&(ctlregbase->LPDDR4__WRITE_MODEREG__REG), regval);
>
> - result = lpddr4_pollctlirq(pd, LPDDR4_MR_WRITE_DONE, tdelay);
> + result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MR_WRITE_DONE, tdelay);
>
> return result;
> }
>
> -uint32_t lpddr4_setmmrregister(const lpddr4_privatedata * pd,
> - uint32_t writemoderegval, uint8_t * mrwstatus)
> +u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus)
> {
> - uint32_t result = 0U;
> + u32 result = 0U;
>
> result = lpddr4_setmmrregistersf(pd, mrwstatus);
> - if (result == (uint32_t) CDN_EOK) {
> -
> - /* Function call to trigger Mode register write */
> + if (result == (u32)CDN_EOK) {
> result = lpddr4_writemmrregister(pd, writemoderegval);
>
> - if (result == (uint32_t) CDN_EOK) {
> - result =
> - lpddr4_ackctlinterrupt(pd, LPDDR4_MR_WRITE_DONE);
> - }
> - /* Read the status of mode register write */
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase =
> - (lpddr4_ctlregs *) pd->ctlbase;
> - *mrwstatus =
> - (uint8_t) CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__MRW_STATUS__REG)));
> - if ((*mrwstatus) != 0U) {
> - result = EIO;
> - }
> + if (result == (u32)CDN_EOK)
> + result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_WRITE_DONE);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + *mrwstatus = (u8)CPS_FLD_READ(LPDDR4__MRW_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRW_STATUS__REG)));
> + if ((*mrwstatus) != 0U)
> + result = (u32)CDN_EIO;
> }
> }
>
> - return result;
> -}
> +#ifdef ASILC
> +#endif
That doesn't seem too useful.
>
> -uint32_t lpddr4_writectlconfig(const lpddr4_privatedata * pd,
> - const lpddr4_reginitdata * regvalues)
> -{
> - uint32_t result;
> - uint32_t regnum;
> -
> - result = lpddr4_writectlconfigsf(pd, regvalues);
> - if (result == (uint32_t) CDN_EOK) {
> -
> - /* Iterate through CTL register numbers. */
> - for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
> - /* Check if the user has requested update */
> - if (regvalues->updatectlreg[regnum]) {
> - result =
> - lpddr4_writereg(pd, LPDDR4_CTL_REGS, regnum,
> - (uint32_t) (regvalues->
> - denalictlreg
> - [regnum]));
> - }
> - }
> - }
> return result;
> }
>
> -uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata * pd,
> - const lpddr4_reginitdata * regvalues)
> +u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
> {
> - uint32_t result;
> - uint32_t regnum;
> -
> - result = lpddr4_writephyindepconfigsf(pd, regvalues);
> - if (result == (uint32_t) CDN_EOK) {
> -
> - /* Iterate through PHY Independent module register numbers. */
> - for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
> - /* Check if the user has requested update */
> - if (regvalues->updatephyindepreg[regnum]) {
> - result =
> - lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS,
> - regnum,
> - (uint32_t) (regvalues->
> - denaliphyindepreg
> - [regnum]));
> - }
> - }
> - }
> - return result;
> -}
> + u32 result;
> + u32 aindex;
>
> -uint32_t lpddr4_writephyconfig(const lpddr4_privatedata * pd,
> - const lpddr4_reginitdata * regvalues)
> -{
> - uint32_t result;
> - uint32_t regnum;
> -
> - result = lpddr4_writephyconfigsf(pd, regvalues);
> - if (result == (uint32_t) CDN_EOK) {
> -
> - /* Iterate through PHY register numbers. */
> - for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
> - /* Check if the user has requested update */
> - if (regvalues->updatephyreg[regnum]) {
> - result =
> - lpddr4_writereg(pd, LPDDR4_PHY_REGS, regnum,
> - (uint32_t) (regvalues->
> - denaliphyreg
> - [regnum]));
> - }
> - }
> - }
> - return result;
> -}
> + result = lpddr4_writectlconfigsf(pd);
> + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
> + result = CDN_EINVAL;
>
> -uint32_t lpddr4_readctlconfig(const lpddr4_privatedata * pd,
> - lpddr4_reginitdata * regvalues)
> -{
> - uint32_t result;
> - uint32_t regnum;
> - result = lpddr4_readctlconfigsf(pd, regvalues);
> - if (result == (uint32_t) CDN_EOK) {
> - /* Iterate through CTL register numbers. */
> - for (regnum = 0; regnum < LPDDR4_CTL_REG_COUNT; regnum++) {
> - /* Check if the user has requested read (updateCtlReg=1) */
> - if (regvalues->updatectlreg[regnum]) {
> - result =
> - lpddr4_readreg(pd, LPDDR4_CTL_REGS, regnum,
> - (uint32_t *) (®values->
> - denalictlreg
> - [regnum]));
> - }
> - }
> + if (result == (u32)CDN_EOK) {
> + for (aindex = 0; aindex < regcount; aindex++)
> + result = (u32)lpddr4_writereg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
> + (u32)regvalues[aindex]);
> }
> return result;
> }
>
> -uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata * pd,
> - lpddr4_reginitdata * regvalues)
> +u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
> {
> - uint32_t result;
> - uint32_t regnum;
> -
> - result = lpddr4_readphyindepconfigsf(pd, regvalues);
> - if (result == (uint32_t) CDN_EOK) {
> - /* Iterate through PHY Independent module register numbers. */
> - for (regnum = 0; regnum < LPDDR4_PHY_INDEP_REG_COUNT; regnum++) {
> - /* Check if the user has requested read (updateCtlReg=1) */
> - if (regvalues->updatephyindepreg[regnum]) {
> - result =
> - lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS,
> - regnum,
> - (uint32_t *) (®values->
> - denaliphyindepreg
> - [regnum]));
> - }
> - }
> - }
> - return result;
> -}
> + u32 result;
> + u32 aindex;
>
> -uint32_t lpddr4_readphyconfig(const lpddr4_privatedata * pd,
> - lpddr4_reginitdata * regvalues)
> -{
> - uint32_t result;
> - uint32_t regnum;
> -
> - result = lpddr4_readphyconfigsf(pd, regvalues);
> - if (result == (uint32_t) CDN_EOK) {
> - /* Iterate through PHY register numbers. */
> - for (regnum = 0; regnum < LPDDR4_PHY_REG_COUNT; regnum++) {
> - /* Check if the user has requested read (updateCtlReg=1) */
> - if (regvalues->updatephyreg[regnum]) {
> - result =
> - lpddr4_readreg(pd, LPDDR4_PHY_REGS, regnum,
> - (uint32_t *) (®values->
> - denaliphyreg
> - [regnum]));
> - }
> - }
> + result = lpddr4_writephyindepconfigsf(pd);
> + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
> + result = CDN_EINVAL;
> + if (result == (u32)CDN_EOK) {
> + for (aindex = 0; aindex < regcount; aindex++)
> + result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
> + (u32)regvalues[aindex]);
> }
> return result;
> }
>
> -uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata * pd,
> - uint64_t * mask)
> +u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
> {
> - uint32_t result = 0U;
> - uint64_t lowermask = 0U;
> -
> - result = lpddr4_getctlinterruptmasksf(pd, mask);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - /* Reading the lower mask register */
> - lowermask =
> - (uint64_t) (CPS_FLD_READ
> - (LPDDR4__INT_MASK_0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__INT_MASK_0__REG))));
> - /* Reading the upper mask register */
> - *mask =
> - (uint64_t) (CPS_FLD_READ
> - (LPDDR4__INT_MASK_1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__INT_MASK_1__REG))));
> - /* Concatenate both register informations */
> - *mask = (uint64_t) ((*mask << WORD_SHIFT) | lowermask);
> + u32 result;
> + u32 aindex;
> +
> + result = lpddr4_writephyconfigsf(pd);
> + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
> + result = CDN_EINVAL;
> + if (result == (u32)CDN_EOK) {
> + for (aindex = 0; aindex < regcount; aindex++)
> + result = (u32)lpddr4_writereg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
> + (u32)regvalues[aindex]);
This only captures the result of last register write, all others are
ignored. Similar issue appears copied all over the place.
> }
> return result;
> }
>
> -uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata * pd,
> - const uint64_t * mask)
> +u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
> {
> - uint32_t result;
> - uint32_t regval = 0;
> - const uint64_t ui64one = 1ULL;
> - const uint32_t ui32irqcount = (uint32_t) LPDDR4_LOR_BITS + 1U;
> -
> - result = lpddr4_setctlinterruptmasksf(pd, mask);
> - if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < 64U)) {
> - /* Return if the user given value is higher than the field width */
> - if (*mask >= (ui64one << ui32irqcount)) {
> - result = EINVAL;
> - }
> - }
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Extracting the lower 32 bits and writing to lower mask register */
> - regval = (uint32_t) (*mask & WORD_MASK);
> - regval =
> - CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__INT_MASK_0__REG)),
> - regval);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
> -
> - /* Extracting the upper 32 bits and writing to upper mask register */
> - regval = (uint32_t) ((*mask >> WORD_SHIFT) & WORD_MASK);
> - regval =
> - CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__INT_MASK_1__REG)),
> - regval);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
> + u32 result;
> + u32 aindex;
> +
> + result = lpddr4_readctlconfigsf(pd);
> + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
> + result = CDN_EINVAL;
> + if (result == (u32)CDN_EOK) {
> + for (aindex = 0; aindex < regcount; aindex++)
> + result = (u32)lpddr4_readreg(pd, LPDDR4_CTL_REGS, (u32)regnum[aindex],
> + (u32 *)(®values[aindex]));
> }
> return result;
> }
>
> -uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata * pd,
> - lpddr4_ctlinterrupt intr, bool * irqstatus)
> +u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
> {
> - uint32_t result;
> - uint32_t ctlirqstatus = 0;
> - uint32_t fieldshift = 0;
> -
> - /* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
> - * Value of 'interrupt' should be less than 64 */
> - result = lpddr4_checkctlinterruptsf(pd, intr, irqstatus);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - if ((uint32_t) intr >= WORD_SHIFT) {
> - ctlirqstatus =
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__INT_STATUS_1__REG));
> - /* Reduce the shift value as we are considering upper register */
> - fieldshift = (uint32_t) intr - ((uint32_t) WORD_SHIFT);
> - } else {
> - ctlirqstatus =
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__INT_STATUS_0__REG));
> - /* The shift value remains same for lower interrupt register */
> - fieldshift = (uint32_t) intr;
> - }
> + u32 result;
> + u32 aindex;
>
> - /* MISRA compliance (Shifting operation) check */
> - if (fieldshift < WORD_SHIFT) {
> - if ((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) {
> - *irqstatus = true;
> - } else {
> - *irqstatus = false;
> - }
> - }
> + result = lpddr4_readphyindepconfigsf(pd);
> + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
> + result = CDN_EINVAL;
> + if (result == (u32)CDN_EOK) {
> + for (aindex = 0; aindex < regcount; aindex++)
> + result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_INDEP_REGS, (u32)regnum[aindex],
> + (u32 *)(®values[aindex])) > }
> return result;
> }
>
> -uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata * pd,
> - lpddr4_ctlinterrupt intr)
> +u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount)
> {
> - uint32_t result = 0;
> - uint32_t regval = 0;
> - uint32_t localinterrupt = (uint32_t) intr;
> -
> - /* NOTE:This function assume irq status is mentioned in NOT more than 2 registers.
> - * Value of 'interrupt' should be less than 64 */
> - result = lpddr4_ackctlinterruptsf(pd, intr);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Check if the requested bit is in upper register */
> - if (localinterrupt > WORD_SHIFT) {
> - localinterrupt =
> - (localinterrupt - (uint32_t) WORD_SHIFT);
> - regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG),
> - regval);
> - } else {
> - regval = (uint32_t)LPDDR4_BIT_MASK << localinterrupt;
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG),
> - regval);
> - }
> - }
> + u32 result;
> + u32 aindex;
>
> + result = lpddr4_readphyconfigsf(pd);
> + if ((regvalues == (u32 *)NULL) || (regnum == (u16 *)NULL))
> + result = CDN_EINVAL;
> + if (result == (u32)CDN_EOK) {
> + for (aindex = 0; aindex < regcount; aindex++)
> + result = (u32)lpddr4_readreg(pd, LPDDR4_PHY_REGS, (u32)regnum[aindex],
> + (u32 *)(®values[aindex]));
> + }
> return result;
> }
>
> -uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata * pd,
> - uint32_t * mask)
> +u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask)
> {
> - uint32_t result;
> -
> - result = lpddr4_getphyindepinterruptmsf(pd, mask);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - /* Reading mask register */
> - *mask =
> - CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__PI_INT_MASK__REG)));
> + u32 result;
> +
> + result = LPDDR4_GetPhyIndepInterruptMSF(pd, mask);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + *mask = CPS_FLD_READ(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)));
> }
> return result;
> }
>
> -uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata * pd,
> - const uint32_t * mask)
> +u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask)
> {
> - uint32_t result;
> - uint32_t regval = 0;
> - const uint32_t ui32irqcount =
> - (uint32_t) LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
> -
> - result = lpddr4_setphyindepinterruptmsf(pd, mask);
> - if ((result == (uint32_t) CDN_EOK) && (ui32irqcount < WORD_SHIFT)) {
> - /* Return if the user given value is higher than the field width */
> - if (*mask >= (1U << ui32irqcount)) {
> - result = EINVAL;
> - }
> + u32 result;
> + u32 regval = 0;
> + const u32 ui32irqcount = (u32)LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT + 1U;
> +
> + result = LPDDR4_SetPhyIndepInterruptMSF(pd, mask);
> + if ((result == (u32)CDN_EOK) && (ui32irqcount < WORD_SHIFT)) {
> + if (*mask >= (1U << ui32irqcount))
> + result = (u32)CDN_EINVAL;
> }
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Writing to the user requested interrupt mask */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__PI_INT_MASK__REG)),
> - *mask);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + regval = CPS_FLD_WRITE(LPDDR4__PI_INT_MASK__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_MASK__REG)), *mask);
> CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_MASK__REG), regval);
> }
> return result;
> }
>
> -uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata * pd,
> - lpddr4_phyindepinterrupt intr,
> - bool * irqstatus)
> +u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus)
> {
> - uint32_t result = 0;
> - uint32_t phyindepirqstatus = 0;
> -
> - result = lpddr4_checkphyindepinterrupsf(pd, intr, irqstatus);
> - /* Confirming that the value of interrupt is less than register width */
> - if ((result == (uint32_t) CDN_EOK) && ((uint32_t) intr < WORD_SHIFT)) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Reading the requested bit to check interrupt status */
> - phyindepirqstatus =
> - CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
> - *irqstatus =
> - !!((phyindepirqstatus >> (uint32_t)intr) & LPDDR4_BIT_MASK);
> + u32 result = 0;
> + u32 phyindepirqstatus = 0;
> +
> + result = LPDDR4_INTR_CheckPhyIndepIntSF(pd, intr, irqstatus);
> + if ((result == (u32)CDN_EOK) && ((u32)intr < WORD_SHIFT)) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + phyindepirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INT_STATUS__REG));
> + *irqstatus = (bool)(((phyindepirqstatus >> (u32)intr) & LPDDR4_BIT_MASK) > 0U);
> }
> return result;
> }
>
> -uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata * pd,
> - lpddr4_phyindepinterrupt intr)
> +u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr)
> {
> - uint32_t result = 0U;
> - uint32_t regval = 0U;
> - uint32_t ui32shiftinterrupt = (uint32_t) intr;
> + u32 result = 0U;
> + u32 regval = 0U;
>
> - result = lpddr4_ackphyindepinterruptsf(pd, intr);
> - /* Confirming that the value of interrupt is less than register width */
> - if ((result == (uint32_t) CDN_EOK) && (ui32shiftinterrupt < WORD_SHIFT)) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> + result = LPDDR4_INTR_AckPhyIndepIntSF(pd, intr);
> + if ((result == (u32)CDN_EOK) && ((u32)intr < WORD_SHIFT)) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
>
> - /* Write 1 to the requested bit to ACk the interrupt */
> - regval = (uint32_t)LPDDR4_BIT_MASK << ui32shiftinterrupt;
> + regval = ((u32)LPDDR4_BIT_MASK << (u32)intr);
> CPS_REG_WRITE(&(ctlregbase->LPDDR4__PI_INT_ACK__REG), regval);
> }
>
> return result;
> }
>
> -/* Check for caTrainingError */
> -static void lpddr4_checkcatrainingerror(lpddr4_ctlregs * ctlregbase,
> - lpddr4_debuginfo * debuginfo,
> - bool * errfoundptr)
> +static void lpddr4_checkcatrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
> {
> + u32 regval;
> + u32 errbitmask = 0U;
> + u32 snum;
> + volatile u32 *regaddress;
>
> - uint32_t regval;
> - uint32_t errbitmask = 0U;
> - uint32_t snum;
> - volatile uint32_t *regaddress;
> -
> - regaddress =
> - (volatile uint32_t
> - *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
> + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_ADR_CALVL_OBS1_0__REG));
> errbitmask = (CA_TRAIN_RL) | (NIBBLE_MASK);
> - /* PHY_ADR_CALVL_OBS1[4] – Right found
> - PHY_ADR_CALVL_OBS1[5] – left found
> - both the above fields should be high and below field should be zero.
> - PHY_ADR_CALVL_OBS1[3:0] – calvl_state
> - */
> for (snum = 0U; snum < ASLICE_NUM; snum++) {
> regval = CPS_REG_READ(regaddress);
> if ((regval & errbitmask) != CA_TRAIN_RL) {
> - debuginfo->catraingerror = true;
> - *errfoundptr = true;
> - }
> - regaddress =
> - lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
> - }
> -}
> -
> -/* Check for wrLvlError */
> -static void lpddr4_checkwrlvlerror(lpddr4_ctlregs * ctlregbase,
> - lpddr4_debuginfo * debuginfo,
> - bool * errfoundptr)
> -{
> -
> - uint32_t regval;
> - uint32_t errbitmask = 0U;
> - uint32_t snum;
> - volatile uint32_t *regaddress;
> -
> - regaddress =
> - (volatile uint32_t
> - *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
> - /* PHY_WRLVL_ERROR_OBS_X[1:0] should be zero */
> - errbitmask = (LPDDR4_BIT_MASK << 1) | LPDDR4_BIT_MASK;
> - for (snum = 0U; snum < DSLICE_NUM; snum++) {
> - regval = CPS_REG_READ(regaddress);
> - if ((regval & errbitmask) != 0U) {
> - debuginfo->wrlvlerror = true;
> + debuginfo->catraingerror = CDN_TRUE;
> *errfoundptr = true;
> }
> - regaddress =
> - lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
> + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
> }
> }
>
> -/* Check for GateLvlError */
> -static void lpddr4_checkgatelvlerror(lpddr4_ctlregs * ctlregbase,
> - lpddr4_debuginfo * debuginfo,
> - bool * errfoundptr)
> +static void lpddr4_checkgatelvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
> {
> + u32 regval;
> + u32 errbitmask = 0U;
> + u32 snum;
> + volatile u32 *regaddress;
>
> - uint32_t regval;
> - uint32_t errbitmask = 0U;
> - uint32_t snum;
> - volatile uint32_t *regaddress;
> -
> - regaddress =
> - (volatile uint32_t
> - *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
> - /* PHY_GTLVL_STATUS_OBS[6] – gate_level min error
> - * PHY_GTLVL_STATUS_OBS[7] – gate_level max error
> - * All the above bit fields should be zero */
> + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_GTLVL_STATUS_OBS_0__REG));
> errbitmask = GATE_LVL_ERROR_FIELDS;
> - for (snum = 0U; snum < DSLICE_NUM; snum++) {
> + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
> regval = CPS_REG_READ(regaddress);
> if ((regval & errbitmask) != 0U) {
> - debuginfo->gatelvlerror = true;
> + debuginfo->gatelvlerror = CDN_TRUE;
> *errfoundptr = true;
> }
> - regaddress =
> - lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
> + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
> }
> }
>
> -/* Check for ReadLvlError */
> -static void lpddr4_checkreadlvlerror(lpddr4_ctlregs * ctlregbase,
> - lpddr4_debuginfo * debuginfo,
> - bool * errfoundptr)
> +static void lpddr4_checkreadlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
> {
> + u32 regval;
> + u32 errbitmask = 0U;
> + u32 snum;
> + volatile u32 *regaddress;
>
> - uint32_t regval;
> - uint32_t errbitmask = 0U;
> - uint32_t snum;
> - volatile uint32_t *regaddress;
> -
> - regaddress =
> - (volatile uint32_t
> - *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
> - /* PHY_RDLVL_STATUS_OBS[23:16] – failed bits : should be zero.
> - PHY_RDLVL_STATUS_OBS[31:28] – rdlvl_state : should be zero */
> + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RDLVL_STATUS_OBS_0__REG));
> errbitmask = READ_LVL_ERROR_FIELDS;
> - for (snum = 0U; snum < DSLICE_NUM; snum++) {
> + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
> regval = CPS_REG_READ(regaddress);
> if ((regval & errbitmask) != 0U) {
> - debuginfo->readlvlerror = true;
> + debuginfo->readlvlerror = CDN_TRUE;
> *errfoundptr = true;
> }
> - regaddress =
> - lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
> + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
> }
> }
>
> -/* Check for DqTrainingError */
> -static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs * ctlregbase,
> - lpddr4_debuginfo * debuginfo,
> - bool * errfoundptr)
> +static void lpddr4_checkdqtrainingerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
> {
> + u32 regval;
> + u32 errbitmask = 0U;
> + u32 snum;
> + volatile u32 *regaddress;
>
> - uint32_t regval;
> - uint32_t errbitmask = 0U;
> - uint32_t snum;
> - volatile uint32_t *regaddress;
> -
> - regaddress =
> - (volatile uint32_t
> - *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
> - /* PHY_WDQLVL_STATUS_OBS[26:18] should all be zero. */
> + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WDQLVL_STATUS_OBS_0__REG));
> errbitmask = DQ_LVL_STATUS;
> - for (snum = 0U; snum < DSLICE_NUM; snum++) {
> + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
> regval = CPS_REG_READ(regaddress);
> if ((regval & errbitmask) != 0U) {
> - debuginfo->dqtrainingerror = true;
> + debuginfo->dqtrainingerror = CDN_TRUE;
> *errfoundptr = true;
> }
> - regaddress =
> - lpddr4_addoffset(regaddress, (uint32_t) SLICE_WIDTH);
> + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
> }
> }
>
> -/**
> - * Internal Function:For checking errors in training/levelling sequence.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] debugInfo pointer to debug information.
> - * @param[out] errFoundPtr pointer to return if error found.
> - * @return CDN_EOK on success (Interrupt status high).
> - * @return EINVAL checking or unmasking was not successful.
> - */
> -static bool lpddr4_checklvlerrors(const lpddr4_privatedata * pd,
> - lpddr4_debuginfo * debuginfo, bool errfound)
> +bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound)
> {
> -
> bool localerrfound = errfound;
>
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
>
> - if (localerrfound == false) {
> - /* Check for ca training error */
> - lpddr4_checkcatrainingerror(ctlregbase, debuginfo,
> - &localerrfound);
> - }
> + if (localerrfound == (bool)false)
> + lpddr4_checkcatrainingerror(ctlregbase, debuginfo, &localerrfound);
>
> - if (localerrfound == false) {
> - /* Check for Write leveling error */
> + if (localerrfound == (bool)false)
> lpddr4_checkwrlvlerror(ctlregbase, debuginfo, &localerrfound);
> - }
>
> - if (localerrfound == false) {
> - /* Check for Gate leveling error */
> + if (localerrfound == (bool)false)
> lpddr4_checkgatelvlerror(ctlregbase, debuginfo, &localerrfound);
> - }
>
> - if (localerrfound == false) {
> - /* Check for Read leveling error */
> + if (localerrfound == (bool)false)
> lpddr4_checkreadlvlerror(ctlregbase, debuginfo, &localerrfound);
> - }
>
> - if (localerrfound == false) {
> - /* Check for DQ training error */
> - lpddr4_checkdqtrainingerror(ctlregbase, debuginfo,
> - &localerrfound);
> - }
> + if (localerrfound == (bool)false)
> + lpddr4_checkdqtrainingerror(ctlregbase, debuginfo, &localerrfound);
> return localerrfound;
> }
>
> -static bool lpddr4_seterror(volatile uint32_t * reg, uint32_t errbitmask,
> - bool * errfoundptr, const uint32_t errorinfobits)
> +static u8 lpddr4_seterror(volatile u32 *reg, u32 errbitmask, u8 *errfoundptr, const u32 errorinfobits)
> {
> + u32 regval = 0U;
>
> - uint32_t regval = 0U;
> -
> - /* Read the respective observation register */
> regval = CPS_REG_READ(reg);
> - /* Compare the error bit values */
> - if ((regval & errbitmask) != errorinfobits) {
> - *errfoundptr = true;
> - }
> + if ((regval & errbitmask) != errorinfobits)
> + *errfoundptr = CDN_TRUE;
> return *errfoundptr;
> }
>
> -static void lpddr4_seterrors(lpddr4_ctlregs * ctlregbase,
> - lpddr4_debuginfo * debuginfo, bool * errfoundptr)
> +void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr)
> {
> + u32 errbitmask = (LPDDR4_BIT_MASK << 0x1U) | (LPDDR4_BIT_MASK);
>
> - uint32_t errbitmask = (LPDDR4_BIT_MASK << 0x1U) | LPDDR4_BIT_MASK;
> - /* Check PLL observation registers for PLL lock errors */
> -
> - debuginfo->pllerror =
> - lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
> - errbitmask, errfoundptr, PLL_READY);
> - if (*errfoundptr == false) {
> - debuginfo->pllerror =
> - lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
> - errbitmask, errfoundptr, PLL_READY);
> - }
> + debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_0__REG),
> + errbitmask, errfoundptr, PLL_READY);
> + if (*errfoundptr == CDN_FALSE)
> + debuginfo->pllerror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_PLL_OBS_1__REG),
> + errbitmask, errfoundptr, PLL_READY);
>
> - /* Check for IO Calibration errors */
> - if (*errfoundptr == false) {
> - debuginfo->iocaliberror =
> - lpddr4_seterror(&
> - (ctlregbase->
> - LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
> - IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
> - }
> - if (*errfoundptr == false) {
> - debuginfo->iocaliberror =
> - lpddr4_seterror(&
> - (ctlregbase->
> - LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
> - IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
> - }
> - if (*errfoundptr == false) {
> - debuginfo->iocaliberror =
> - lpddr4_seterror(&
> - (ctlregbase->
> - LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
> - IO_CALIB_FIELD, errfoundptr,
> - IO_CALIB_STATE);
> - }
> + if (*errfoundptr == CDN_FALSE)
> + debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT_OBS_0__REG),
> + IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
> + if (*errfoundptr == CDN_FALSE)
> + debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT2_OBS_0__REG),
> + IO_CALIB_DONE, errfoundptr, IO_CALIB_DONE);
> + if (*errfoundptr == CDN_FALSE)
> + debuginfo->iocaliberror = lpddr4_seterror(&(ctlregbase->LPDDR4__PHY_CAL_RESULT3_OBS_0__REG),
> + IO_CALIB_FIELD, errfoundptr, IO_CALIB_STATE);
> }
>
> -static void lpddr4_setphysnapsettings(lpddr4_ctlregs * ctlregbase,
> - const bool errorfound)
> +static void lpddr4_setphysnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
> {
> + u32 snum = 0U;
> + volatile u32 *regaddress;
> + u32 regval = 0U;
>
> - uint32_t snum = 0U;
> - volatile uint32_t *regaddress;
> - uint32_t regval = 0U;
> -
> - /* Setting SC_PHY_SNAP_OBS_REGS_x to get a snapshot */
> - if (errorfound == false) {
> - regaddress =
> - (volatile uint32_t
> - *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
> - /* Iterate through each PHY Data Slice */
> - for (snum = 0U; snum < DSLICE_NUM; snum++) {
> - regval =
> - CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD,
> - CPS_REG_READ(regaddress));
> + if (errorfound == (bool)false) {
> + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_SNAP_OBS_REGS_0__REG));
> + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
> + regval = CPS_FLD_SET(LPDDR4__SC_PHY_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
> CPS_REG_WRITE(regaddress, regval);
> - regaddress =
> - lpddr4_addoffset(regaddress,
> - (uint32_t) SLICE_WIDTH);
> + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
> }
> }
> }
>
> -static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs * ctlregbase,
> - const bool errorfound)
> +static void lpddr4_setphyadrsnapsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
> {
> + u32 snum = 0U;
> + volatile u32 *regaddress;
> + u32 regval = 0U;
>
> - uint32_t snum = 0U;
> - volatile uint32_t *regaddress;
> - uint32_t regval = 0U;
> -
> - /* Setting SC_PHY ADR_SNAP_OBS_REGS_x to get a snapshot */
> - if (errorfound == false) {
> - regaddress =
> - (volatile uint32_t
> - *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
> - /* Iterate through each PHY Address Slice */
> - for (snum = 0U; snum < ASLICE_NUM; snum++) {
> - regval =
> - CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD,
> - CPS_REG_READ(regaddress));
> + if (errorfound == (bool)false) {
false is bool already, no?
You could also just do !errorfound.
> + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__REG));
> + for (snum = (u32)0U; snum < ASLICE_NUM; snum++) {
> + regval = CPS_FLD_SET(LPDDR4__SC_PHY_ADR_SNAP_OBS_REGS_0__FLD, CPS_REG_READ(regaddress));
> CPS_REG_WRITE(regaddress, regval);
> - regaddress =
> - lpddr4_addoffset(regaddress,
> - (uint32_t) SLICE_WIDTH);
> + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
> }
> }
> }
>
> -static void lpddr4_setsettings(lpddr4_ctlregs * ctlregbase,
> - const bool errorfound)
> +void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound)
> {
> -
> - /* Calling functions to enable snap shots of OBS registers */
> lpddr4_setphysnapsettings(ctlregbase, errorfound);
> lpddr4_setphyadrsnapsettings(ctlregbase, errorfound);
> }
>
> -static void lpddr4_setrxoffseterror(lpddr4_ctlregs * ctlregbase,
> - lpddr4_debuginfo * debuginfo,
> - bool * errorfound)
> +static void readpdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
> {
> -
> - volatile uint32_t *regaddress;
> - uint32_t snum = 0U;
> - uint32_t errbitmask = 0U;
> - uint32_t regval = 0U;
> -
> - /* Check for rxOffsetError */
> - if (*errorfound == false) {
> - regaddress =
> - (volatile uint32_t
> - *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
> - errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
> - /* PHY_RX_CAL_LOCK_OBS_x[4] – RX_CAL_DONE : should be high
> - phy_rx_cal_lock_obs_x[3:0] – RX_CAL_STATE : should be zero. */
> - for (snum = 0U; snum < DSLICE_NUM; snum++) {
> - regval =
> - CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD,
> - CPS_REG_READ(regaddress));
> - if ((regval & errbitmask) != RX_CAL_DONE) {
> - debuginfo->rxoffseterror = true;
> - *errorfound = true;
> - }
> - regaddress =
> - lpddr4_addoffset(regaddress,
> - (uint32_t) SLICE_WIDTH);
> - }
> - }
> + if (*fspnum == LPDDR4_FSP_0)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)));
> + else if (*fspnum == LPDDR4_FSP_1)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)));
> + else
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)));
> }
>
> -uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata * pd,
> - lpddr4_debuginfo * debuginfo)
> +static void readsrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
> {
> -
> - uint32_t result = 0U;
> - bool errorfound = false;
> -
> - /* Calling Sanity Function to verify the input variables */
> - result = lpddr4_getdebuginitinfosf(pd, debuginfo);
> - if (result == (uint32_t) CDN_EOK) {
> -
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - lpddr4_seterrors(ctlregbase, debuginfo, &errorfound);
> - /* Function to setup Snap for OBS registers */
> - lpddr4_setsettings(ctlregbase, errorfound);
> - /* Function to check for Rx offset error */
> - lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
> - /* Function Check various levelling errors */
> - errorfound = lpddr4_checklvlerrors(pd, debuginfo, errorfound);
> - }
> -
> - if (errorfound == true) {
> - result = (uint32_t) EPROTO;
> - }
> -
> - return result;
> -}
> -
> -static void readpdwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
> -{
> -
> - /* Read the appropriate register, based on user given frequency. */
> - if (*fspnum == LPDDR4_FSP_0) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_PD_WAKEUP_F0__REG)));
> - } else if (*fspnum == LPDDR4_FSP_1) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_PD_WAKEUP_F1__REG)));
> - } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_PD_WAKEUP_F2__REG)));
> - }
> -}
> -
> -static void readsrshortwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
> -{
> -
> - /* Read the appropriate register, based on user given frequency. */
> - if (*fspnum == LPDDR4_FSP_0) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
> - } else if (*fspnum == LPDDR4_FSP_1) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
> - } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
> - }
> + if (*fspnum == LPDDR4_FSP_0)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)));
> + else if (*fspnum == LPDDR4_FSP_1)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)));
> + else
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)));
> }
>
> -static void readsrlongwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
> +static void readsrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
> {
> -
> - /* Read the appropriate register, based on user given frequency. */
> - if (*fspnum == LPDDR4_FSP_0) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
> - } else if (*fspnum == LPDDR4_FSP_1) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
> - } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
> - }
> + if (*fspnum == LPDDR4_FSP_0)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)));
> + else if (*fspnum == LPDDR4_FSP_1)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)));
> + else
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)));
> }
>
> -static void readsrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
> +static void readsrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
> {
> -
> - /* Read the appropriate register, based on user given frequency. */
> - if (*fspnum == LPDDR4_FSP_0) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
> - } else if (*fspnum == LPDDR4_FSP_1) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
> - } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
> - }
> + if (*fspnum == LPDDR4_FSP_0)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
> + else if (*fspnum == LPDDR4_FSP_1)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
> + else
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
> }
>
> -static void readsrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
> +static void readsrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
> {
> -
> - /* Read the appropriate register, based on user given frequency. */
> - if (*fspnum == LPDDR4_FSP_0) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
> - } else if (*fspnum == LPDDR4_FSP_1) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
> - } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
> - }
> + if (*fspnum == LPDDR4_FSP_0)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)));
> + else if (*fspnum == LPDDR4_FSP_1)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)));
> + else
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)));
> }
>
> -static void readsrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase, uint32_t * cycles)
> +static void readsrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
> {
> -
> - /* Read the appropriate register, based on user given frequency. */
> - if (*fspnum == LPDDR4_FSP_0) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
> - } else if (*fspnum == LPDDR4_FSP_1) {
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
> - } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - *cycles =
> - CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
> - }
> + if (*fspnum == LPDDR4_FSP_0)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)));
> + else if (*fspnum == LPDDR4_FSP_1)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)));
> + else
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)));
> }
>
> -static void readsrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase,
> - uint32_t * cycles)
> +static void readsrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, u32 *cycles)
> {
> -
> - /* Read the appropriate register, based on user given frequency. */
> - if (*fspnum == LPDDR4_FSP_0) {
> - *cycles =
> - CPS_FLD_READ
> - (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
> - } else if (*fspnum == LPDDR4_FSP_1) {
> - *cycles =
> - CPS_FLD_READ
> - (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
> - } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - *cycles =
> - CPS_FLD_READ
> - (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
> - }
> + if (*fspnum == LPDDR4_FSP_0)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)));
> + else if (*fspnum == LPDDR4_FSP_1)
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)));
> + else
> + *cycles = CPS_FLD_READ(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)));
>
> }
>
> -static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs * ctlregbase,
> - const lpddr4_lpiwakeupparam *
> - lpiwakeupparam,
> - const lpddr4_ctlfspnum * fspnum,
> - uint32_t * cycles)
> +static void lpddr4_readlpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
> {
> -
> - /* Iterate through each of the Wake up parameter type */
> - if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
> - /* Calling appropriate function for register read */
> + if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
> readpdwakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
> readsrshortwakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
> readsrlongwakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
> readsrlonggatewakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
> readsrdpshortwakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
> readsrdplongwakeup(fspnum, ctlregbase, cycles);
> - } else {
> - /* Default function (sanity function already confirmed the variable value) */
> + else
> readsrdplonggatewakeup(fspnum, ctlregbase, cycles);
> - }
> }
>
> -uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata * pd,
> - const lpddr4_lpiwakeupparam * lpiwakeupparam,
> - const lpddr4_ctlfspnum * fspnum,
> - uint32_t * cycles)
> +u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles)
> {
> + u32 result = 0U;
>
> - uint32_t result = 0U;
> -
> - /* Calling Sanity Function to verify the input variables */
> result = lpddr4_getlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
> - cycles);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + lpddr4_readlpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
> }
> return result;
> }
>
> -static void writepdwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase, const uint32_t * cycles)
> +static void writepdwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
> {
> + u32 regval = 0U;
>
> - uint32_t regval = 0U;
> - /* Write to appropriate register ,based on user given frequency. */
> if (*fspnum == LPDDR4_FSP_0) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_PD_WAKEUP_F0__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F0__REG), regval);
> } else if (*fspnum == LPDDR4_FSP_1) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_PD_WAKEUP_F1__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F1__REG), regval);
> } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_PD_WAKEUP_F2__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_PD_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_PD_WAKEUP_F2__REG), regval);
> }
> }
>
> -static void writesrshortwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase,
> - const uint32_t * cycles)
> +static void writesrshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
> {
> + u32 regval = 0U;
>
> - uint32_t regval = 0U;
> - /* Write to appropriate register ,based on user given frequency. */
> if (*fspnum == LPDDR4_FSP_0) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F0__REG), regval);
> } else if (*fspnum == LPDDR4_FSP_1) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F1__REG), regval);
> } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_SHORT_WAKEUP_F2__REG), regval);
> }
> }
>
> -static void writesrlongwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase,
> - const uint32_t * cycles)
> +static void writesrlongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
> {
> + u32 regval = 0U;
>
> - uint32_t regval = 0U;
> - /* Write to appropriate register ,based on user given frequency. */
> if (*fspnum == LPDDR4_FSP_0) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F0__REG), regval);
> } else if (*fspnum == LPDDR4_FSP_1) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F1__REG), regval);
> } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_WAKEUP_F2__REG), regval);
> }
> }
>
> -static void writesrlonggatewakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase,
> - const uint32_t * cycles)
> +static void writesrlonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
> {
> + u32 regval = 0U;
>
> - uint32_t regval = 0U;
> - /* Write to appropriate register ,based on user given frequency. */
> if (*fspnum == LPDDR4_FSP_0) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
> } else if (*fspnum == LPDDR4_FSP_1) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
> } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
> }
> }
>
> -static void writesrdpshortwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase,
> - const uint32_t * cycles)
> +static void writesrdpshortwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
> {
> + u32 regval = 0U;
>
> - uint32_t regval = 0U;
> - /* Write to appropriate register ,based on user given frequency. */
> if (*fspnum == LPDDR4_FSP_0) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F0__REG), regval);
> } else if (*fspnum == LPDDR4_FSP_1) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F1__REG), regval);
> } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_SHORT_WAKEUP_F2__REG), regval);
> }
> }
>
> -static void writesrdplongwakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase,
> - const uint32_t * cycles)
> +static void writesrdplongwakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
> {
> + u32 regval = 0U;
>
> - uint32_t regval = 0U;
> - /* Write to appropriate register ,based on user given frequency. */
> if (*fspnum == LPDDR4_FSP_0) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F0__REG), regval);
> } else if (*fspnum == LPDDR4_FSP_1) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F1__REG), regval);
> } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_WAKEUP_F2__REG), regval);
> }
> }
> -
> -static void writesrdplonggatewakeup(const lpddr4_ctlfspnum * fspnum,
> - lpddr4_ctlregs * ctlregbase,
> - const uint32_t * cycles)
> +static void writesrdplonggatewakeup(const lpddr4_ctlfspnum *fspnum, lpddr4_ctlregs *ctlregbase, const u32 *cycles)
> {
> + u32 regval = 0U;
>
> - uint32_t regval = 0U;
> - /* Write to appropriate register ,based on user given frequency. */
> if (*fspnum == LPDDR4_FSP_0) {
> - regval =
> - CPS_FLD_WRITE
> - (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0__REG), regval);
> } else if (*fspnum == LPDDR4_FSP_1) {
> - regval =
> - CPS_FLD_WRITE
> - (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1__REG), regval);
> } else {
> - /* Default register (sanity function already confirmed the variable value) */
> - regval =
> - CPS_FLD_WRITE
> - (LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)),
> - *cycles);
> - CPS_REG_WRITE(&
> - (ctlregbase->
> - LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG),
> - regval);
> + regval = CPS_FLD_WRITE(LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG)), *cycles);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2__REG), regval);
> }
> }
>
> -static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs * ctlregbase,
> - const lpddr4_lpiwakeupparam *
> - lpiwakeupparam,
> - const lpddr4_ctlfspnum * fspnum,
> - const uint32_t * cycles)
> +static void lpddr4_writelpiwakeuptime(lpddr4_ctlregs *ctlregbase, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
> {
> -
> - /* Iterate through each of the Wake up parameter type */
> - if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN) {
> - /* Calling appropriate function for register write */
> + if (*lpiwakeupparam == LPDDR4_LPI_PD_WAKEUP_FN)
> writepdwakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SR_SHORT_WAKEUP_FN)
> writesrshortwakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_WAKEUP_FN)
> writesrlongwakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN)
> writesrlonggatewakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN)
> writesrdpshortwakeup(fspnum, ctlregbase, cycles);
> - } else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) {
> + else if (*lpiwakeupparam == LPDDR4_LPI_SRPD_LONG_WAKEUP_FN)
> writesrdplongwakeup(fspnum, ctlregbase, cycles);
> - } else {
> - /* Default function (sanity function already confirmed the variable value) */
> + else
> writesrdplonggatewakeup(fspnum, ctlregbase, cycles);
> - }
The above could be switch / case. There are plenty of similar examples
in the code.
> }
>
> -uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata * pd,
> - const lpddr4_lpiwakeupparam * lpiwakeupparam,
> - const lpddr4_ctlfspnum * fspnum,
> - const uint32_t * cycles)
> +u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
> {
> - uint32_t result = 0U;
> + u32 result = 0U;
>
> - /* Calling Sanity Function to verify the input variables */
> result = lpddr4_setlpiwakeuptimesf(pd, lpiwakeupparam, fspnum, cycles);
> - if (result == (uint32_t) CDN_EOK) {
> - /* Return if the user given value is higher than the field width */
> - if (*cycles > NIBBLE_MASK) {
> - result = EINVAL;
> - }
> + if (result == (u32)CDN_EOK) {
> + if (*cycles > NIBBLE_MASK)
> + result = (u32)CDN_EINVAL;
> }
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum,
> - cycles);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + lpddr4_writelpiwakeuptime(ctlregbase, lpiwakeupparam, fspnum, cycles);
> }
> return result;
> }
>
> -uint32_t lpddr4_geteccenable(const lpddr4_privatedata * pd,
> - lpddr4_eccenable * eccparam)
> +u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off)
> {
> - uint32_t result = 0U;
> - uint32_t fldval = 0U;
> -
> - /* Calling Sanity Function to verify the input variables */
> - result = lpddr4_geteccenablesf(pd, eccparam);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Reading the ECC_Enable field from the register. */
> - fldval =
> - CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__ECC_ENABLE__REG)));
> - switch (fldval) {
> - case 3:
> - *eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
> - break;
> - case 2:
> - *eccparam = LPDDR4_ECC_ERR_DETECT;
> - break;
> - case 1:
> - *eccparam = LPDDR4_ECC_ENABLED;
> - break;
> - default:
> - /* Default ECC (Sanity function already confirmed the value to be in expected range.) */
> - *eccparam = LPDDR4_ECC_DISABLED;
> - break;
> - }
> - }
> - return result;
> -}
> -
> -uint32_t lpddr4_seteccenable(const lpddr4_privatedata * pd,
> - const lpddr4_eccenable * eccparam)
> -{
> -
> - uint32_t result = 0U;
> - uint32_t regval = 0U;
> -
> - /* Calling Sanity Function to verify the input variables */
> - result = lpddr4_seteccenablesf(pd, eccparam);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Updating the ECC_Enable field based on the user given value. */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__ECC_ENABLE__REG)),
> - *eccparam);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
> - }
> - return result;
> -}
> + u32 result = 0U;
>
> -uint32_t lpddr4_getreducmode(const lpddr4_privatedata * pd,
> - lpddr4_reducmode * mode)
> -{
> - uint32_t result = 0U;
> -
> - /* Calling Sanity Function to verify the input variables */
> - result = lpddr4_getreducmodesf(pd, mode);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - /* Read the value of reduc parameter. */
> - if (CPS_FLD_READ
> - (LPDDR4__REDUC__FLD,
> - CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U) {
> - *mode = LPDDR4_REDUC_ON;
> - } else {
> - *mode = LPDDR4_REDUC_OFF;
> - }
> - }
> - return result;
> -}
> -
> -uint32_t lpddr4_setreducmode(const lpddr4_privatedata * pd,
> - const lpddr4_reducmode * mode)
> -{
> - uint32_t result = 0U;
> - uint32_t regval = 0U;
> -
> - /* Calling Sanity Function to verify the input variables */
> - result = lpddr4_setreducmodesf(pd, mode);
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - /* Setting to enable Half data path. */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__REDUC__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__REDUC__REG)), *mode);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
> - }
> - return result;
> -}
> -
> -uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata * pd, bool * on_off)
> -{
> -
> - uint32_t result = 0U;
> -
> - /* Calling Sanity Function to verify the input variables */
> result = lpddr4_getdbireadmodesf(pd, on_off);
>
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - /* Reading the field value from the register. */
> - if (CPS_FLD_READ
> - (LPDDR4__RD_DBI_EN__FLD,
> - CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) ==
> - 0U) {
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + if (CPS_FLD_READ(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG))) == 0U)
> *on_off = false;
> - } else {
> + else
> *on_off = true;
> - }
> }
> return result;
> }
>
> -uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata * pd, bool * on_off)
> +u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off)
> {
> + u32 result = 0U;
>
> - uint32_t result = 0U;
> -
> - /* Calling Sanity Function to verify the input variables */
> result = lpddr4_getdbireadmodesf(pd, on_off);
>
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - /* Reading the field value from the register. */
> - if (CPS_FLD_READ
> - (LPDDR4__WR_DBI_EN__FLD,
> - CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) ==
> - 0U) {
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + if (CPS_FLD_READ(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG))) == 0U)
> *on_off = false;
> - } else {
> + else
> *on_off = true;
> - }
> }
> return result;
> }
>
> -uint32_t lpddr4_setdbimode(const lpddr4_privatedata * pd,
> - const lpddr4_dbimode * mode)
> +u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
> {
> + u32 result = 0U;
> + u32 regval = 0U;
>
> - uint32_t result = 0U;
> - uint32_t regval = 0U;
> -
> - /* Calling Sanity Function to verify the input variables */
> result = lpddr4_setdbimodesf(pd, mode);
>
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> -
> - /* Updating the appropriate field value based on the user given mode */
> - if (*mode == LPDDR4_DBI_RD_ON) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__RD_DBI_EN__REG)),
> - 1U);
> - } else if (*mode == LPDDR4_DBI_RD_OFF) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__RD_DBI_EN__REG)),
> - 0U);
> - } else if (*mode == LPDDR4_DBI_WR_ON) {
> - regval =
> - CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__WR_DBI_EN__REG)),
> - 1U);
> - } else {
> - /* Default field (Sanity function already confirmed the value to be in expected range.) */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__WR_DBI_EN__REG)),
> - 0U);
> - }
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + if (*mode == LPDDR4_DBI_RD_ON)
> + regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 1U);
> + else if (*mode == LPDDR4_DBI_RD_OFF)
> + regval = CPS_FLD_WRITE(LPDDR4__RD_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__RD_DBI_EN__REG)), 0U);
> + else if (*mode == LPDDR4_DBI_WR_ON)
> + regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 1U);
> + else
> + regval = CPS_FLD_WRITE(LPDDR4__WR_DBI_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__WR_DBI_EN__REG)), 0U);
> CPS_REG_WRITE(&(ctlregbase->LPDDR4__RD_DBI_EN__REG), regval);
> }
> return result;
> }
>
> -uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata * pd,
> - const lpddr4_ctlfspnum * fspnum,
> - uint32_t * cycles)
> +u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max)
> {
> - uint32_t result = 0U;
> + u32 result = 0U;
>
> - /* Calling Sanity Function to verify the input variables */
> - result = lpddr4_getrefreshratesf(pd, fspnum, cycles);
> + result = lpddr4_getrefreshratesf(pd, fspnum, tref, tras_max);
>
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
>
> - /* Selecting the appropriate register for the user requested Frequency */
> switch (*fspnum) {
> case LPDDR4_FSP_2:
> - *cycles =
> - CPS_FLD_READ(LPDDR4__TREF_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__TREF_F2__REG)));
> + *tref = CPS_FLD_READ(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)));
> + *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)));
> break;
> case LPDDR4_FSP_1:
> - *cycles =
> - CPS_FLD_READ(LPDDR4__TREF_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__TREF_F1__REG)));
> + *tref = CPS_FLD_READ(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)));
> + *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)));
> break;
> default:
> - /* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
> - *cycles =
> - CPS_FLD_READ(LPDDR4__TREF_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__TREF_F0__REG)));
> + *tref = CPS_FLD_READ(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)));
> + *tras_max = CPS_FLD_READ(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)));
> break;
> }
> }
> return result;
> }
>
> -uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata * pd,
> - const lpddr4_ctlfspnum * fspnum,
> - const uint32_t * cycles)
> +static void lpddr4_updatefsp2refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
> +{
> + u32 regval = 0U;
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + regval = CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F2__REG)), *tref);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F2__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG)), *tras_max);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F2__REG), regval);
> +}
> +
> +static void lpddr4_updatefsp1refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
> {
> - uint32_t result = 0U;
> - uint32_t regval = 0U;
> + u32 regval = 0U;
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
>
> - /* Calling Sanity Function to verify the input variables */
> - result = lpddr4_setrefreshratesf(pd, fspnum, cycles);
> + regval = CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F1__REG)), *tref);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG)), *tras_max);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F1__REG), regval);;
> +}
> +
> +static void lpddr4_updatefsp0refrateparams(const lpddr4_privatedata *pd, const u32 *tref, const u32 *tras_max)
> +{
> + u32 regval = 0U;
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + regval = CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_F0__REG)), *tref);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG), regval);
> + regval = CPS_FLD_WRITE(LPDDR4__TRAS_MAX_F0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG)), *tras_max);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TRAS_MAX_F0__REG), regval);
> +}
> +
> +u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
> +{
> + u32 result = 0U;
>
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> + result = lpddr4_setrefreshratesf(pd, fspnum, tref, tras_max);
>
> - /* Selecting the appropriate register for the user requested Frequency */
> + if (result == (u32)CDN_EOK) {
> switch (*fspnum) {
> case LPDDR4_FSP_2:
> - regval =
> - CPS_FLD_WRITE(LPDDR4__TREF_F2__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__TREF_F2__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F2__REG),
> - regval);
> + lpddr4_updatefsp2refrateparams(pd, tref, tras_max);
> break;
> case LPDDR4_FSP_1:
> - regval =
> - CPS_FLD_WRITE(LPDDR4__TREF_F1__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__TREF_F1__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F1__REG),
> - regval);
> + lpddr4_updatefsp1refrateparams(pd, tref, tras_max);
> break;
> default:
> - /* FSP_0 is considered as the default (sanity check already confirmed it as valid FSP) */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__TREF_F0__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__TREF_F0__REG)),
> - *cycles);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_F0__REG),
> - regval);
> + lpddr4_updatefsp0refrateparams(pd, tref, tras_max);
> break;
> }
> }
> return result;
> }
>
> -uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata * pd,
> - const uint32_t trefinterval)
> +u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval)
> {
> - uint32_t result = 0U;
> - uint32_t regval = 0U;
> + u32 result = 0U;
> + u32 regval = 0U;
>
> - /* Calling Sanity Function to verify the input variables */
> result = lpddr4_refreshperchipselectsf(pd);
>
> - if (result == (uint32_t) CDN_EOK) {
> - lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *) pd->ctlbase;
> - /* Setting tref_interval parameter to enable/disable Refresh per chip select. */
> - regval =
> - CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD,
> - CPS_REG_READ(&
> - (ctlregbase->
> - LPDDR4__TREF_INTERVAL__REG)),
> - trefinterval);
> - CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG),
> - regval);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + regval = CPS_FLD_WRITE(LPDDR4__TREF_INTERVAL__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG)), trefinterval);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__TREF_INTERVAL__REG), regval);
> }
> return result;
> }
> diff --git a/drivers/ram/k3-ddrss/lpddr4.h b/drivers/ram/k3-ddrss/lpddr4.h
> new file mode 100644
> index 000000000000..5b77ea9e6e94
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/lpddr4.h
> @@ -0,0 +1,73 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef LPDDR4_H
> +#define LPDDR4_H
> +
> +#include "lpddr4_ctl_regs.h"
> +#include "lpddr4_sanity.h"
> +#ifdef CONFIG_K3_AM64_DDRSS
> +#include "lpddr4_16bit.h"
> +#include "lpddr4_16bit_sanity.h"
> +#else
> +#include "lpddr4_32bit.h"
> +#include "lpddr4_32bit_sanity.h"
> +#endif
> +
> +#ifdef REG_WRITE_VERIF
> +#include "lpddr4_ctl_regs_rw_masks.h"
> +#endif
> +#ifdef __cplusplus
> +extern "C" {
Does anybody compile u-boot with c++ compiler?
> +#endif
> +
> +#define PRODUCT_ID (0x1046U)
> +
> +#define LPDDR4_BIT_MASK (0x1U)
> +#define BYTE_MASK (0xffU)
> +#define NIBBLE_MASK (0xfU)
> +
> +#define WORD_SHIFT (32U)
> +#define WORD_MASK (0xffffffffU)
> +#define SLICE_WIDTH (0x100)
> +
> +#define CTL_OFFSET 0
> +#define PI_OFFSET (((u32)1) << 11)
> +#define PHY_OFFSET (((u32)1) << 12)
> +
> +#define CTL_INT_MASK_ALL ((u32)LPDDR4_LOR_BITS - WORD_SHIFT)
> +
> +#define PLL_READY (0x3U)
> +#define IO_CALIB_DONE ((u32)0x1U << 23U)
> +#define IO_CALIB_FIELD ((u32)NIBBLE_MASK << 28U)
> +#define IO_CALIB_STATE ((u32)0xBU << 28U)
> +#define RX_CAL_DONE ((u32)LPDDR4_BIT_MASK << 4U)
> +#define CA_TRAIN_RL (((u32)LPDDR4_BIT_MASK << 5U) | ((u32)LPDDR4_BIT_MASK << 4U))
> +#define WR_LVL_STATE (((u32)NIBBLE_MASK) << 13U)
> +#define GATE_LVL_ERROR_FIELDS (((u32)LPDDR4_BIT_MASK << 7U) | ((u32)LPDDR4_BIT_MASK << 6U))
> +#define READ_LVL_ERROR_FIELDS ((((u32)NIBBLE_MASK) << 28U) | (((u32)BYTE_MASK) << 16U))
> +#define DQ_LVL_STATUS (((u32)LPDDR4_BIT_MASK << 26U) | (((u32)BYTE_MASK) << 18U))
> +
> +#define CDN_TRUE 1U
> +#define CDN_FALSE 0U
Why not just used true / false?
> +
> +void lpddr4_setsettings(lpddr4_ctlregs *ctlregbase, const bool errorfound);
> +volatile u32 *lpddr4_addoffset(volatile u32 *addr, u32 regoffset);
> +u32 lpddr4_pollctlirq(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt irqbit, u32 delay);
> +bool lpddr4_checklvlerrors(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo, bool errfound);
> +void lpddr4_seterrors(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, u8 *errfoundptr);
> +
> +u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd);
> +void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr);
> +u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus);
> +u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset);
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* LPDDR4_H */
> diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.c b/drivers/ram/k3-ddrss/lpddr4_32bit.c
> new file mode 100644
> index 000000000000..5f8abe7b5fca
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/lpddr4_32bit.c
> @@ -0,0 +1,302 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <cdn_errno.h>
> +
> +#include "cps_drv_lpddr4.h"
> +#include "lpddr4_ctl_regs.h"
> +#include "lpddr4_if.h"
> +#include "lpddr4.h"
> +#include "lpddr4_structs_if.h"
> +
> +static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound);
> +
> +u32 lpddr4_enablepiinitiator(const lpddr4_privatedata *pd)
> +{
> + u32 result = 0U;
> + u32 regval = 0U;
> +
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + regval = CPS_FLD_SET(LPDDR4__PI_INIT_LVL_EN__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)));
> + regval = CPS_FLD_SET(LPDDR4__PI_NORMAL_LVL_SEQ__FLD, regval);
> + CPS_REG_WRITE((&(ctlregbase->LPDDR4__PI_INIT_LVL_EN__REG)), regval);
> + return result;
> +}
> +
> +u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask)
> +{
> + u32 result = 0U;
> + u32 lowermask = 0U;
> +
> + result = lpddr4_getctlinterruptmasksf(pd, mask);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + lowermask = (u32)(CPS_FLD_READ(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG))));
> + *mask = (u64)(CPS_FLD_READ(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG))));
> + *mask = (u64)((*mask << WORD_SHIFT) | lowermask);
> + }
> + return result;
> +}
> +
> +u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask)
> +{
> + u32 result;
> + u32 regval = 0;
> + const u64 ui64one = 1ULL;
> + const u32 ui32irqcount = (u32)LPDDR4_INTR_LOR_BITS + 1U;
> +
> + result = lpddr4_setctlinterruptmasksf(pd, mask);
> + if ((result == (u32)CDN_EOK) && (ui32irqcount < 64U)) {
> + if (*mask >= (ui64one << ui32irqcount))
> + result = (u32)CDN_EINVAL;
> + }
> +
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + regval = (u32)(*mask & WORD_MASK);
> + regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_0__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_0__REG)), regval);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_0__REG), regval);
> +
> + regval = (u32)((*mask >> WORD_SHIFT) & WORD_MASK);
> + regval = CPS_FLD_WRITE(LPDDR4__INT_MASK_1__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__INT_MASK_1__REG)), regval);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_MASK_1__REG), regval);
> + }
> + return result;
> +}
> +
> +u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus)
> +{
> + u32 result;
> + u32 ctlirqstatus = 0;
> + u32 fieldshift = 0;
> +
> + result = LPDDR4_INTR_CheckCtlIntSF(pd, intr, irqstatus);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + if ((u32)intr >= (u32)WORD_SHIFT) {
> + ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_1__REG));
> + fieldshift = (u32)intr - ((u32)WORD_SHIFT);
> + } else {
> + ctlirqstatus = CPS_REG_READ(&(ctlregbase->LPDDR4__INT_STATUS_0__REG));
> + fieldshift = (u32)intr;
> + }
> +
> + if (fieldshift < WORD_SHIFT) {
> + if (((ctlirqstatus >> fieldshift) & LPDDR4_BIT_MASK) > 0U)
> + *irqstatus = true;
> + else
> + *irqstatus = false;
> + }
> + }
> + return result;
> +}
> +
> +u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr)
> +{
> + u32 result = 0;
> + u32 regval = 0;
> + u32 localinterrupt = (u32)intr;
> +
> + result = LPDDR4_INTR_AckCtlIntSF(pd, intr);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + if (localinterrupt > WORD_SHIFT) {
> + localinterrupt = (localinterrupt - (u32)WORD_SHIFT);
> + regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_1__REG), regval);
> + } else {
> + regval = ((u32)LPDDR4_BIT_MASK << localinterrupt);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__INT_ACK_0__REG), regval);
> + }
> + }
> +
> + return result;
> +}
> +
> +void lpddr4_checkwrlvlerror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errfoundptr)
> +{
> + u32 regval;
> + u32 errbitmask = 0U;
> + u32 snum;
> + volatile u32 *regaddress;
> +
> + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_WRLVL_ERROR_OBS_0__REG));
> + errbitmask = (LPDDR4_BIT_MASK << 1) | (LPDDR4_BIT_MASK);
> + for (snum = 0U; snum < DSLICE_NUM; snum++) {
> + regval = CPS_REG_READ(regaddress);
> + if ((regval & errbitmask) != 0U) {
> + debuginfo->wrlvlerror = CDN_TRUE;
> + *errfoundptr = true;
> + }
> + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
> + }
> +}
> +
> +static void lpddr4_setrxoffseterror(lpddr4_ctlregs *ctlregbase, lpddr4_debuginfo *debuginfo, bool *errorfound)
> +{
> + volatile u32 *regaddress;
> + u32 snum = 0U;
> + u32 errbitmask = 0U;
> + u32 regval = 0U;
> +
> + if (*errorfound == (bool)false) {
> + regaddress = (volatile u32 *)(&(ctlregbase->LPDDR4__PHY_RX_CAL_LOCK_OBS_0__REG));
> + errbitmask = (RX_CAL_DONE) | (NIBBLE_MASK);
> + for (snum = (u32)0U; snum < DSLICE_NUM; snum++) {
> + regval = CPS_FLD_READ(LPDDR4__PHY_RX_CAL_LOCK_OBS_0__FLD, CPS_REG_READ(regaddress));
> + if ((regval & errbitmask) != RX_CAL_DONE) {
> + debuginfo->rxoffseterror = (u8)true;
> + *errorfound = true;
> + }
> + regaddress = lpddr4_addoffset(regaddress, (u32)SLICE_WIDTH);
> + }
> + }
> +}
> +
> +u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo)
> +{
> + u32 result = 0U;
> + bool errorfound = false;
> +
> + result = lpddr4_getdebuginitinfosf(pd, debuginfo);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + lpddr4_seterrors(ctlregbase, debuginfo, (u8 *)&errorfound);
> + lpddr4_setsettings(ctlregbase, errorfound);
> + lpddr4_setrxoffseterror(ctlregbase, debuginfo, &errorfound);
> + errorfound = (bool)lpddr4_checklvlerrors(pd, debuginfo, errorfound);
> + }
> +
> + if (errorfound == (bool)true)
> + result = (u32)CDN_EPROTO;
> +
> + return result;
> +}
> +
> +u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam)
> +{
> + u32 result = 0U;
> + u32 fldval = 0U;
> +
> + result = lpddr4_geteccenablesf(pd, eccparam);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + fldval = CPS_FLD_READ(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)));
> + switch (fldval) {
> + case 3:
> + *eccparam = LPDDR4_ECC_ERR_DETECT_CORRECT;
> + break;
> + case 2:
> + *eccparam = LPDDR4_ECC_ERR_DETECT;
> + break;
> + case 1:
> + *eccparam = LPDDR4_ECC_ENABLED;
> + break;
> + default:
> + *eccparam = LPDDR4_ECC_DISABLED;
> + break;
> + }
> + }
> + return result;
> +}
> +
> +u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
> +{
> + u32 result = 0U;
> + u32 regval = 0U;
> +
> + result = lpddr4_seteccenablesf(pd, eccparam);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> +
> + regval = CPS_FLD_WRITE(LPDDR4__ECC_ENABLE__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__ECC_ENABLE__REG)), *eccparam);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__ECC_ENABLE__REG), regval);
> + }
> + return result;
> +}
> +
> +u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode)
> +{
> + u32 result = 0U;
> +
> + result = lpddr4_getreducmodesf(pd, mode);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + if (CPS_FLD_READ(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG))) == 0U)
> + *mode = LPDDR4_REDUC_ON;
> + else
> + *mode = LPDDR4_REDUC_OFF;
> + }
> + return result;
> +}
> +u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
> +{
> + u32 result = 0U;
> + u32 regval = 0U;
> +
> + result = lpddr4_setreducmodesf(pd, mode);
> + if (result == (u32)CDN_EOK) {
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + regval = (u32)CPS_FLD_WRITE(LPDDR4__REDUC__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__REDUC__REG)), *mode);
> + CPS_REG_WRITE(&(ctlregbase->LPDDR4__REDUC__REG), regval);
> + }
> + return result;
> +}
> +
> +u32 lpddr4_checkmmrreaderror(const lpddr4_privatedata *pd, u64 *mmrvalue, u8 *mrrstatus)
> +{
> + u32 lowerdata;
> + lpddr4_ctlregs *ctlregbase = (lpddr4_ctlregs *)pd->ctlbase;
> + u32 result = (u32)CDN_EOK;
> +
> + if (lpddr4_pollctlirq(pd, LPDDR4_INTR_MRR_ERROR, 100) == 0U) {
> + *mrrstatus = (u8)CPS_FLD_READ(LPDDR4__MRR_ERROR_STATUS__FLD, CPS_REG_READ(&(ctlregbase->LPDDR4__MRR_ERROR_STATUS__REG)));
> + *mmrvalue = (u64)0;
> + result = (u32)CDN_EIO;
> + } else {
> + *mrrstatus = (u8)0;
> + lowerdata = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_0__REG));
> + *mmrvalue = CPS_REG_READ(&(ctlregbase->LPDDR4__PERIPHERAL_MRR_DATA_1__REG));
> + *mmrvalue = (u64)((*mmrvalue << WORD_SHIFT) | lowerdata);
> + result = lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MR_READ_DONE);
> + }
> + return result;
> +}
> +
> +#ifdef REG_WRITE_VERIF
> +
> +u32 lpddr4_getdslicemask(u32 dslicenum, u32 arrayoffset)
> +{
> + u32 rwmask = 0U;
> +
> + switch (dslicenum) {
> + case 0:
> + if (arrayoffset < DSLICE0_REG_COUNT)
> + rwmask = g_lpddr4_data_slice_0_rw_mask[arrayoffset];
> + break;
> + case 1:
> + if (arrayoffset < DSLICE1_REG_COUNT)
> + rwmask = g_lpddr4_data_slice_1_rw_mask[arrayoffset];
> + break;
> + case 2:
> + if (arrayoffset < DSLICE2_REG_COUNT)
> + rwmask = g_lpddr4_data_slice_2_rw_mask[arrayoffset];
> + break;
> + default:
> + if (arrayoffset < DSLICE3_REG_COUNT)
> + rwmask = g_lpddr4_data_slice_3_rw_mask[arrayoffset];
> + break;
> + }
> + return rwmask;
> +}
> +#endif
> diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit.h b/drivers/ram/k3-ddrss/lpddr4_32bit.h
> new file mode 100644
> index 000000000000..1f7fe658af84
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/lpddr4_32bit.h
> @@ -0,0 +1,30 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef LPDDR4_32BIT_H
> +#define LPDDR4_32BIT_H
> +
> +#define DSLICE_NUM (4U)
> +#define ASLICE_NUM (1U)
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +#define DSLICE0_REG_COUNT (140U)
> +#define DSLICE1_REG_COUNT (140U)
> +#define DSLICE2_REG_COUNT (140U)
> +#define DSLICE3_REG_COUNT (140U)
> +#define ASLICE0_REG_COUNT (52U)
> +#define PHY_CORE_REG_COUNT (140U)
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* LPDDR4_32BIT_H */
> diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c b/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
> new file mode 100644
> index 000000000000..1ce45f1668c6
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/lpddr4_32bit_ctl_regs_rw_masks.c
> @@ -0,0 +1,1548 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#include <cdn_stdtypes.h>
> +#include "lpddr4_ctl_regs_rw_masks.h"
> +
> +u32 g_lpddr4_ddr_controller_rw_mask[] = {
> + 0x00000F01U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x01FFFFFFU,
> + 0x01010100U,
> + 0x03013F01U,
> + 0x1F1F1F03U,
> + 0x00030303U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFF01U,
> + 0x0001FFFFU,
> + 0xFF0F7FFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x7F7F0000U,
> + 0x7F7F7F7FU,
> + 0x00FF1F07U,
> + 0x3FFF01FFU,
> + 0xFF01FFFFU,
> + 0x3FFF01FFU,
> + 0xFF01FFFFU,
> + 0x3FFF01FFU,
> + 0x3F01FFFFU,
> + 0x00FFFFFFU,
> + 0x1F01FFFFU,
> + 0xFFFFFFFFU,
> + 0x1F01FFFFU,
> + 0xFFFFFFFFU,
> + 0x1F01FFFFU,
> + 0x070707FFU,
> + 0xFFFFFF01U,
> + 0x0FFFFFFFU,
> + 0x3F03FF1FU,
> + 0x1F1F1F1FU,
> + 0x0101011FU,
> + 0x1FFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0301FFFFU,
> + 0x0101017FU,
> + 0x07010000U,
> + 0x0003FF3FU,
> + 0x000FFFFFU,
> + 0x000003FFU,
> + 0x000FFFFFU,
> + 0x000003FFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x03FF0101U,
> + 0x03FFFFFFU,
> + 0x03FFFFFFU,
> + 0xFFFFFFFFU,
> + 0x1F1F010FU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x1F1F1FFFU,
> + 0x1F010F1FU,
> + 0x0F1F1F1FU,
> + 0x1F1F1F01U,
> + 0x00010F1FU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFF1F1F1FU,
> + 0x1F1F1F07U,
> + 0xFF1F1F1FU,
> + 0x1F1F1F07U,
> + 0xFF1F1F1FU,
> + 0x1F1F1F07U,
> + 0x07010101U,
> + 0x01010000U,
> + 0x00010101U,
> + 0xFFFFFFFFU,
> + 0x0700FFFFU,
> + 0xFFFFFF07U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0000FFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0000FFFFU,
> + 0x000FFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0000FFFFU,
> + 0x000FFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0000FFFFU,
> + 0x010FFFFFU,
> + 0x00010100U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0001FFFFU,
> + 0x01FFFFFFU,
> + 0x01000107U,
> + 0xFFFFFF03U,
> + 0x00FFFFFFU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x3F0F0F0FU,
> + 0x070FFF01U,
> + 0x0F0F0000U,
> + 0x000FFF07U,
> + 0xFFFF0FFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x01010101U,
> + 0x3F3F0101U,
> + 0x01FF03FFU,
> + 0xFFFF03FFU,
> + 0xFFFF03FFU,
> + 0xFFFF03FFU,
> + 0x00000100U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x00FFFF0FU,
> + 0x07FFFFFFU,
> + 0x01FFFF00U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00010000U,
> + 0x03FF0003U,
> + 0x03FF03FFU,
> + 0xFFFF1F1FU,
> + 0x03FF03FFU,
> + 0x1F1F03FFU,
> + 0x03FFFFFFU,
> + 0x03FF03FFU,
> + 0xFFFF1F1FU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFF00FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFF00FFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x00FFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFF00U,
> + 0x010101FFU,
> + 0x01000000U,
> + 0x01010101U,
> + 0x03030101U,
> + 0x013F0000U,
> + 0x00000001U,
> + 0xFFFFFFFFU,
> + 0x00000007U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x00000007U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0FFF0000U,
> + 0x07030000U,
> + 0x010F0101U,
> + 0x01FFFF01U,
> + 0x00000001U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x7FFF0000U,
> + 0x7FFF7FFFU,
> + 0x7FFF7FFFU,
> + 0x00077FFFU,
> + 0x010FFF00U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x00000007U,
> + 0xFFFFFFFFU,
> + 0x1F1F1F07U,
> + 0x000F1F1FU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0007FFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0000FF00U,
> + 0x00000000U,
> + 0x0FFF0FFFU,
> + 0x0FFF0FFFU,
> + 0x000FFF7FU,
> + 0x0FFF0FFFU,
> + 0x007F0FFFU,
> + 0x0FFF0FFFU,
> + 0x0FFF0FFFU,
> + 0x0000037FU,
> + 0x0FFF0FFFU,
> + 0x01010FFFU,
> + 0x03030303U,
> + 0x07070303U,
> + 0xFFFF0F0FU,
> + 0x0007FFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFF0307U,
> + 0x1F01FFFFU,
> + 0xFFFF1F01U,
> + 0x01010101U,
> + 0x01010101U,
> + 0x011F0301U,
> + 0x01030301U,
> + 0x0003FFFFU,
> + 0x00000000U,
> + 0x0103FFFFU,
> + 0x01010103U,
> + 0x01010101U,
> + 0x01010101U,
> + 0x01010101U,
> + 0x0F0F0F07U,
> + 0x0F0F070FU,
> + 0x011F0F0FU,
> + 0x01000003U,
> + 0x03030301U,
> + 0x00010101U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0xFFFFFFFFU,
> + 0x00001FFFU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x03000000U,
> + 0xFF030303U,
> + 0x0FFF0F0FU,
> + 0x0F0FFF0FU,
> + 0x01010101U,
> + 0x3F3F3F3FU,
> + 0x1F1F3F3FU,
> + 0x1F1F1F1FU,
> + 0x1F1F1F1FU,
> + 0x1F1F1F1FU,
> + 0x1F1F1F1FU,
> + 0x0F1F1F1FU,
> + 0x0F070F07U,
> + 0x00000707U,
> + 0x00000000U,
> + 0x00010000U,
> + 0x013F3F01U,
> + 0x0F010101U,
> + 0x00030101U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0000FFFFU,
> + 0x010F0F01U,
> + 0x01010101U,
> + 0x01010101U,
> + 0x03030101U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x00000100U,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x010FFFFFU,
> + 0x0101030FU,
> + 0x03010101U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0101FFFFU,
> + 0x00000707U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00FFFFFFU,
> + 0x7F7F7F00U,
> + 0x00FF0300U,
> + 0x001FFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x007FFFFFU,
> + 0xFFFFFFFFU,
> + 0x00007F7FU,
> + 0x001FFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x007FFFFFU,
> + 0xFFFFFFFFU,
> + 0x00007F7FU,
> + 0x001FFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x007FFFFFU,
> + 0xFFFFFFFFU,
> + 0x0F0F7F7FU,
> + 0xFF0F0F0FU,
> + 0x000003FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0003FFFFU,
> + 0xFFFFFFFFU,
> + 0x000101FFU,
> + 0xFFFFFFFFU,
> + 0x00FF0000U,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x07000101U,
> + 0x7F7F0707U,
> + 0x7F7F7F7FU,
> + 0x010101FFU,
> + 0x07070701U,
> + 0x0F070707U,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0xFF0F0F0FU,
> + 0xFFFF00FFU,
> + 0x000001FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x01010101U,
> + 0x01010101U,
> + 0x00010101U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000100U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x00000007U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0000000FU
> +};
> +
> +u32 g_lpddr4_pi_rw_mask[] = {
> + 0x00000F01U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00010101U,
> + 0x00FFFFFFU,
> + 0x01010301U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0xFFFFFFFFU,
> + 0x0101011FU,
> + 0x0F011F0FU,
> + 0x00010103U,
> + 0x000FFFFFU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000007U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x01000000U,
> + 0x00010101U,
> + 0x003F3F03U,
> + 0x0101FFFFU,
> + 0x0F010F01U,
> + 0x0000FF00U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0F0F0F1FU,
> + 0x00030000U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0101010FU,
> + 0x01010101U,
> + 0x000F0F01U,
> + 0x000003FFU,
> + 0xFFFFFFFFU,
> + 0x0000FF0FU,
> + 0xFFFFFFFFU,
> + 0x00FFFF00U,
> + 0x0F0FFFFFU,
> + 0x01011F1FU,
> + 0x03000000U,
> + 0x01030F01U,
> + 0x0F010101U,
> + 0x000000FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFF0001U,
> + 0x1F1F3F1FU,
> + 0xFF0F0F01U,
> + 0x7F1F0FFFU,
> + 0x0101FFFFU,
> + 0x00FFFF01U,
> + 0x00000000U,
> + 0x010F0701U,
> + 0x011F1F0FU,
> + 0x00FF0300U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0101FFFFU,
> + 0x01010100U,
> + 0x0F1F0703U,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x000F0F0FU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x0FFFFFFFU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x011F1F00U,
> + 0x03030301U,
> + 0x00FF0103U,
> + 0x013F0001U,
> + 0x00000001U,
> + 0xFFFFFFFFU,
> + 0x0000FF07U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0FFF0000U,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0xFFFFFFFFU,
> + 0x0303070FU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0x3FFFFFFFU,
> + 0x3FFFFFFFU,
> + 0x3FFFFFFFU,
> + 0x3FFFFFFFU,
> + 0x3FFFFFFFU,
> + 0x3FFFFFFFU,
> + 0x3FFFFFFFU,
> + 0x3FFFFFFFU,
> + 0x0101010FU,
> + 0x01010100U,
> + 0x00000001U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFF0101U,
> + 0x000000FFU,
> + 0x03FFFFFFU,
> + 0x01FFFF00U,
> + 0x01000000U,
> + 0x0100000FU,
> + 0x00010F07U,
> + 0x0F00010FU,
> + 0x010F0001U,
> + 0x00010F00U,
> + 0x0F00010FU,
> + 0x010F0001U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x011F0000U,
> + 0x01010103U,
> + 0x01010101U,
> + 0x01010101U,
> + 0x01010101U,
> + 0x01010101U,
> + 0x0001FFFFU,
> + 0x0000001FU,
> + 0x0F011F01U,
> + 0x01010101U,
> + 0xFFFFFF01U,
> + 0x000000FFU,
> + 0x000000FFU,
> + 0x000FFFFFU,
> + 0x0FFF0FFFU,
> + 0x7F7F7F7FU,
> + 0x03FF7F7FU,
> + 0x000FFFFFU,
> + 0x000003FFU,
> + 0x000FFFFFU,
> + 0x000003FFU,
> + 0x0F0FFFFFU,
> + 0x03030F0FU,
> + 0x0003FF03U,
> + 0x03FF03FFU,
> + 0x01FF01FFU,
> + 0x0F0F01FFU,
> + 0x0F0F0F0FU,
> + 0x03030303U,
> + 0x03030303U,
> + 0x03030303U,
> + 0x03030303U,
> + 0x7F7F0303U,
> + 0x7F7F7F7FU,
> + 0x00070707U,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x1F030303U,
> + 0x001F3FFFU,
> + 0x001F3FFFU,
> + 0x1F1F3FFFU,
> + 0x03FF03FFU,
> + 0x03FF1F1FU,
> + 0x1F1F03FFU,
> + 0x03FF03FFU,
> + 0x7F7F7F7FU,
> + 0x0F0F7F7FU,
> + 0xFF1F0F0FU,
> + 0xFF1F0F1FU,
> + 0xFF1F0F1FU,
> + 0x0003FF1FU,
> + 0x03FFFFFFU,
> + 0x03FFFFFFU,
> + 0x003FFFFFU,
> + 0x003F03FFU,
> + 0x003F03FFU,
> + 0x03FF03FFU,
> + 0x7F7F03FFU,
> + 0x0003030FU,
> + 0x03FF03FFU,
> + 0x030F7F7FU,
> + 0x0003FF03U,
> + 0x7F7F03FFU,
> + 0xFF03030FU,
> + 0xFF3FFFFFU,
> + 0xFF01FFFFU,
> + 0xFFFF3F0FU,
> + 0xFFFFFFFFU,
> + 0x0000FF3FU,
> + 0xFF01FFFFU,
> + 0xFFFF3F0FU,
> + 0xFFFFFFFFU,
> + 0x0000FF3FU,
> + 0xFF01FFFFU,
> + 0xFFFF3F0FU,
> + 0x1FFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x001FFFFFU,
> + 0xFFFFFFFFU,
> + 0x001FFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x3F3FFFFFU,
> + 0xFFFFFF3FU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x0000FFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x0000FFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x00FFFFFFU,
> + 0x0FFFFFFFU,
> + 0x0FFF0FFFU,
> + 0x000FFF7FU,
> + 0x0FFF0FFFU,
> + 0x000FFF7FU,
> + 0x0FFF0FFFU,
> + 0x000FFF7FU,
> + 0x0FFF0FFFU,
> + 0xFF0F0F0FU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0FFFFFFFU,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0xFF0F0F0FU,
> + 0x0FFFFFFFU,
> + 0x0F0F0F0FU,
> + 0x000F0F0FU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x000007FFU
> +};
> +
> +u32 g_lpddr4_data_slice_0_rw_mask[] = {
> + 0x000F07FFU,
> + 0x000703FFU,
> + 0x010303FFU,
> + 0x3F3F3F3FU,
> + 0x3F3F3F3FU,
> + 0x01030F3FU,
> + 0x1F1F0301U,
> + 0x1F030F0FU,
> + 0x0101FF03U,
> + 0xFFFFFFFFU,
> + 0x00000000U,
> + 0x0101FF7FU,
> + 0x00003F01U,
> + 0x000F03FFU,
> + 0x070101FFU,
> + 0x000301FFU,
> + 0x00000000U,
> + 0x00000301U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x070F0107U,
> + 0x0F0F0F0FU,
> + 0xFF030001U,
> + 0x00FF0F3FU,
> + 0x0F3F03FFU,
> + 0x1F030F3FU,
> + 0x3FFFFFFFU,
> + 0x0F07FF07U,
> + 0x0000FF0FU,
> + 0x000001FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0001FFFFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x00000001U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x7FFFFFFFU,
> + 0x0000003FU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x010001FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x000001FFU,
> + 0x0003FFFFU,
> + 0x01FF01FFU,
> + 0x00000000U,
> + 0x017F7F01U,
> + 0x07FF0FFFU,
> + 0x03FFFF1FU,
> + 0x01FFFF3FU,
> + 0x07030101U,
> + 0x01010101U,
> + 0x000007FFU,
> + 0x00003FFFU,
> + 0x00001F00U,
> + 0x07FFFF07U,
> + 0x7F03FFFFU,
> + 0xFF01037FU,
> + 0x07FF07FFU,
> + 0x0103FFFFU,
> + 0x1F1F0F3FU,
> + 0x1F1F1F1FU,
> + 0x1F1F1F1FU,
> + 0x003F1F1FU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x000703FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFF0FU,
> + 0x0FFFFFFFU,
> + 0x03FFFF01U,
> + 0x1F1F0103U,
> + 0x3F07FF0FU,
> + 0xFF0FFFFFU,
> + 0x1F0F3F0FU,
> + 0x03FF03FFU,
> + 0x0F010FFFU,
> + 0x000003FFU,
> + 0x3F0103FFU,
> + 0x00030703U,
> + 0x07FF03FFU,
> + 0xFFFF0101U,
> + 0x001F3F7FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x03FF07FFU,
> + 0x0003FF03U,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF070FU,
> + 0x000103FFU,
> + 0x000F03FFU,
> + 0x010F07FFU,
> + 0x000003FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0003033FU
> +};
> +
> +u32 g_lpddr4_data_slice_1_rw_mask[] = {
> + 0x000F07FFU,
> + 0x000703FFU,
> + 0x010303FFU,
> + 0x3F3F3F3FU,
> + 0x3F3F3F3FU,
> + 0x01030F3FU,
> + 0x1F1F0301U,
> + 0x1F030F0FU,
> + 0x0101FF03U,
> + 0xFFFFFFFFU,
> + 0x00000000U,
> + 0x0101FF7FU,
> + 0x00003F01U,
> + 0x000F03FFU,
> + 0x070101FFU,
> + 0x000301FFU,
> + 0x00000000U,
> + 0x00000301U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x070F0107U,
> + 0x0F0F0F0FU,
> + 0xFF030001U,
> + 0x00FF0F3FU,
> + 0x0F3F03FFU,
> + 0x1F030F3FU,
> + 0x3FFFFFFFU,
> + 0x0F07FF07U,
> + 0x0000FF0FU,
> + 0x000001FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0001FFFFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x00000001U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x7FFFFFFFU,
> + 0x0000003FU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x010001FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x000001FFU,
> + 0x0003FFFFU,
> + 0x01FF01FFU,
> + 0x00000000U,
> + 0x017F7F01U,
> + 0x07FF0FFFU,
> + 0x03FFFF1FU,
> + 0x01FFFF3FU,
> + 0x07030101U,
> + 0x01010101U,
> + 0x000007FFU,
> + 0x00003FFFU,
> + 0x00001F00U,
> + 0x07FFFF07U,
> + 0x7F03FFFFU,
> + 0xFF01037FU,
> + 0x07FF07FFU,
> + 0x0103FFFFU,
> + 0x1F1F0F3FU,
> + 0x1F1F1F1FU,
> + 0x1F1F1F1FU,
> + 0x003F1F1FU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x000703FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFF0FU,
> + 0x0FFFFFFFU,
> + 0x03FFFF01U,
> + 0x1F1F0103U,
> + 0x3F07FF0FU,
> + 0xFF0FFFFFU,
> + 0x1F0F3F0FU,
> + 0x03FF03FFU,
> + 0x0F010FFFU,
> + 0x000003FFU,
> + 0x3F0103FFU,
> + 0x00030703U,
> + 0x07FF03FFU,
> + 0xFFFF0101U,
> + 0x001F3F7FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x03FF07FFU,
> + 0x0003FF03U,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF070FU,
> + 0x000103FFU,
> + 0x000F03FFU,
> + 0x010F07FFU,
> + 0x000003FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0003033FU
> +};
> +
> +u32 g_lpddr4_data_slice_2_rw_mask[] = {
> + 0x000F07FFU,
> + 0x000703FFU,
> + 0x010303FFU,
> + 0x3F3F3F3FU,
> + 0x3F3F3F3FU,
> + 0x01030F3FU,
> + 0x1F1F0301U,
> + 0x1F030F0FU,
> + 0x0101FF03U,
> + 0xFFFFFFFFU,
> + 0x00000000U,
> + 0x0101FF7FU,
> + 0x00003F01U,
> + 0x000F03FFU,
> + 0x070101FFU,
> + 0x000301FFU,
> + 0x00000000U,
> + 0x00000301U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x070F0107U,
> + 0x0F0F0F0FU,
> + 0xFF030001U,
> + 0x00FF0F3FU,
> + 0x0F3F03FFU,
> + 0x1F030F3FU,
> + 0x3FFFFFFFU,
> + 0x0F07FF07U,
> + 0x0000FF0FU,
> + 0x000001FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0001FFFFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x00000001U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x7FFFFFFFU,
> + 0x0000003FU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x010001FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x000001FFU,
> + 0x0003FFFFU,
> + 0x01FF01FFU,
> + 0x00000000U,
> + 0x017F7F01U,
> + 0x07FF0FFFU,
> + 0x03FFFF1FU,
> + 0x01FFFF3FU,
> + 0x07030101U,
> + 0x01010101U,
> + 0x000007FFU,
> + 0x00003FFFU,
> + 0x00001F00U,
> + 0x07FFFF07U,
> + 0x7F03FFFFU,
> + 0xFF01037FU,
> + 0x07FF07FFU,
> + 0x0103FFFFU,
> + 0x1F1F0F3FU,
> + 0x1F1F1F1FU,
> + 0x1F1F1F1FU,
> + 0x003F1F1FU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x000703FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFF0FU,
> + 0x0FFFFFFFU,
> + 0x03FFFF01U,
> + 0x1F1F0103U,
> + 0x3F07FF0FU,
> + 0xFF0FFFFFU,
> + 0x1F0F3F0FU,
> + 0x03FF03FFU,
> + 0x0F010FFFU,
> + 0x000003FFU,
> + 0x3F0103FFU,
> + 0x00030703U,
> + 0x07FF03FFU,
> + 0xFFFF0101U,
> + 0x001F3F7FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x03FF07FFU,
> + 0x0003FF03U,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF070FU,
> + 0x000103FFU,
> + 0x000F03FFU,
> + 0x010F07FFU,
> + 0x000003FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0003033FU
> +};
> +
> +u32 g_lpddr4_data_slice_3_rw_mask[] = {
> + 0x000F07FFU,
> + 0x000703FFU,
> + 0x010303FFU,
> + 0x3F3F3F3FU,
> + 0x3F3F3F3FU,
> + 0x01030F3FU,
> + 0x1F1F0301U,
> + 0x1F030F0FU,
> + 0x0101FF03U,
> + 0xFFFFFFFFU,
> + 0x00000000U,
> + 0x0101FF7FU,
> + 0x00003F01U,
> + 0x000F03FFU,
> + 0x070101FFU,
> + 0x000301FFU,
> + 0x00000000U,
> + 0x00000301U,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x070F0107U,
> + 0x0F0F0F0FU,
> + 0xFF030001U,
> + 0x00FF0F3FU,
> + 0x0F3F03FFU,
> + 0x1F030F3FU,
> + 0x3FFFFFFFU,
> + 0x0F07FF07U,
> + 0x0000FF0FU,
> + 0x000001FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0001FFFFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x00000001U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x7FFFFFFFU,
> + 0x0000003FU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x010001FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x01FF01FFU,
> + 0x000001FFU,
> + 0x0003FFFFU,
> + 0x01FF01FFU,
> + 0x00000000U,
> + 0x017F7F01U,
> + 0x07FF0FFFU,
> + 0x03FFFF1FU,
> + 0x01FFFF3FU,
> + 0x07030101U,
> + 0x01010101U,
> + 0x000007FFU,
> + 0x00003FFFU,
> + 0x00001F00U,
> + 0x07FFFF07U,
> + 0x7F03FFFFU,
> + 0xFF01037FU,
> + 0x07FF07FFU,
> + 0x0103FFFFU,
> + 0x1F1F0F3FU,
> + 0x1F1F1F1FU,
> + 0x1F1F1F1FU,
> + 0x003F1F1FU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x000703FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFF0FU,
> + 0x0FFFFFFFU,
> + 0x03FFFF01U,
> + 0x1F1F0103U,
> + 0x3F07FF0FU,
> + 0xFF0FFFFFU,
> + 0x1F0F3F0FU,
> + 0x03FF03FFU,
> + 0x0F010FFFU,
> + 0x000003FFU,
> + 0x3F0103FFU,
> + 0x00030703U,
> + 0x07FF03FFU,
> + 0xFFFF0101U,
> + 0x001F3F7FU,
> + 0xFFFFFFFFU,
> + 0x0000000FU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x03FF07FFU,
> + 0x0003FF03U,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF03FFU,
> + 0x03FF070FU,
> + 0x000103FFU,
> + 0x000F03FFU,
> + 0x010F07FFU,
> + 0x000003FFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0003033FU
> +};
> +
> +u32 g_lpddr4_address_slice_0_rw_mask[] = {
> + 0x000107FFU,
> + 0x00000000U,
> + 0x0F000000U,
> + 0x00000000U,
> + 0x01000707U,
> + 0x011F7F7FU,
> + 0x01000301U,
> + 0x07FFFFFFU,
> + 0x0000003FU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x07FF07FFU,
> + 0x000007FFU,
> + 0x00FFFFFFU,
> + 0x03FFFFFFU,
> + 0x01FF0F03U,
> + 0x07000001U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x00FFFFFFU,
> + 0x3F3F03FFU,
> + 0x3F0F3F3FU,
> + 0xFFFFFF03U,
> + 0x01FFFFFFU,
> + 0x3F03FFFFU,
> + 0x0101FFFFU,
> + 0x07FF3F01U,
> + 0x01FF0000U,
> + 0x01000000U,
> + 0x00000000U,
> + 0x07FF07FFU,
> + 0x1F07FF1FU,
> + 0x001F07FFU,
> + 0x001F07FFU,
> + 0x001F07FFU,
> + 0x001F07FFU,
> + 0x000F07FFU,
> + 0xFF3F07FFU,
> + 0x0103FFFFU,
> + 0x0000000FU,
> + 0x03FF010FU,
> + 0x0000FF01U
> +};
> +
> +u32 g_lpddr4_phy_core_rw_mask[] = {
> + 0x00000003U,
> + 0x1F030101U,
> + 0x1F1F1F1FU,
> + 0x001F1F1FU,
> + 0x011F07FFU,
> + 0x07FF0100U,
> + 0x000107FFU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x0101FF01U,
> + 0x0007FF0FU,
> + 0xFF0F07FFU,
> + 0x01030007U,
> + 0xFFFF0101U,
> + 0xFF3F0103U,
> + 0x010101FFU,
> + 0x0F0F0100U,
> + 0x010F0F01U,
> + 0xFFFF0101U,
> + 0x0001010FU,
> + 0x00000000U,
> + 0x0000FFFFU,
> + 0x00000001U,
> + 0x0F0F0F0FU,
> + 0x0F0F0F0FU,
> + 0x01FF0F0FU,
> + 0x001FFFFFU,
> + 0x0001FFFFU,
> + 0x0007FFFFU,
> + 0x000003FFU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x01000000U,
> + 0x0001FF0FU,
> + 0x000103FFU,
> + 0x0003FFFFU,
> + 0x0001FFFFU,
> + 0x0001FFFFU,
> + 0x0003FFFFU,
> + 0x0003FFFFU,
> + 0x0003FFFFU,
> + 0x0003FFFFU,
> + 0x0003FFFFU,
> + 0x0003FFFFU,
> + 0x1FFF03FFU,
> + 0x00001FFFU,
> + 0xFFFFFFFFU,
> + 0x000007FFU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x7F000000U,
> + 0x01FFFFFFU,
> + 0x00000000U,
> + 0x00000000U,
> + 0x0FFFFF7FU,
> + 0x000FFFFFU,
> + 0x01FFFFFFU,
> + 0x3F7FFFFFU,
> + 0x3F3F1F3FU,
> + 0x1F3F3F1FU,
> + 0x001F3F3FU,
> + 0x07FFFFFFU,
> + 0x03010000U,
> + 0x0F7F01FFU,
> + 0x00000000U,
> + 0x003F0101U,
> + 0x01010000U,
> + 0x00000001U,
> + 0xFFFFFFFFU,
> + 0x031F01FFU,
> + 0x00000003U,
> + 0xFFFFFFFFU,
> + 0x03FFFFFFU,
> + 0x07FF073FU,
> + 0x00000007U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000000U,
> + 0x00000003U,
> + 0x070F0101U,
> + 0x00000000U,
> + 0x0707FF01U,
> + 0x00007F00U,
> + 0x3FFF0000U,
> + 0x3F000000U,
> + 0x000FFF00U,
> + 0x03000FFFU,
> + 0x00000000U,
> + 0x000001FFU,
> + 0x03FF0000U,
> + 0x03000000U,
> + 0x007F0000U,
> + 0x00003F00U,
> + 0x000FFFFFU,
> + 0x000FFFFFU,
> + 0x0000FFFFU,
> + 0xFFFFFFFFU,
> + 0x1F0FFFFFU,
> + 0x0FFFFFFFU,
> + 0x0000FFFFU,
> + 0x00003FFFU,
> + 0x3FFF0000U,
> + 0x00000000U,
> + 0x00003FFFU,
> + 0x0003FFFFU,
> + 0x00003FFFU,
> + 0x00000001U,
> + 0x00011FFFU,
> + 0x0F0F0FFFU,
> + 0x010101FFU,
> + 0x07FF07FFU,
> + 0x07FF07FFU,
> + 0x000007FFU,
> + 0x000007FFU,
> + 0x000007FFU,
> + 0x000007FFU,
> + 0x00000007U,
> + 0x3FFFFFFFU,
> + 0x0003FFFFU,
> + 0x7FFFFFFFU,
> + 0xFFFFFFFFU,
> + 0x3FFFFFFFU,
> + 0x07FFFFFFU,
> + 0xFFFFFFFFU,
> + 0x0003FFFFU,
> + 0x3FFFFFFFU,
> + 0x07FFFFFFU,
> + 0x3FFFFFFFU,
> + 0x07FFFFFFU,
> + 0x3FFFFFFFU,
> + 0x07FFFFFFU,
> + 0x3FFFFFFFU,
> + 0x07FFFFFFU,
> + 0x7FFFFF07U
> +};
> diff --git a/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h b/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
> new file mode 100644
> index 000000000000..2750ef79f398
> --- /dev/null
> +++ b/drivers/ram/k3-ddrss/lpddr4_32bit_sanity.h
> @@ -0,0 +1,223 @@
> +/* SPDX-License-Identifier: BSD-3-Clause */
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +#ifndef LPDDR4_32BIT_SANITY_H
> +#define LPDDR4_32BIT_SANITY_H
> +
> +#include "cdn_errno.h"
> +#include "cdn_stdtypes.h"
> +#include <lpddr4_if.h>
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus);
> +static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr);
> +static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus);
> +static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr);
> +
> +#define LPDDR4_INTR_CheckCtlIntSF lpddr4_intr_sanityfunction1
> +#define LPDDR4_INTR_AckCtlIntSF lpddr4_intr_sanityfunction2
> +#define LPDDR4_INTR_CheckPhyIndepIntSF lpddr4_intr_sanityfunction3
> +#define LPDDR4_INTR_AckPhyIndepIntSF lpddr4_intr_sanityfunction4
> +
> +static inline u32 lpddr4_intr_sanityfunction1(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr, const bool *irqstatus)
> +{
> + u32 ret = 0;
> +
> + if (pd == NULL) {
> + ret = CDN_EINVAL;
> + } else if (irqstatus == NULL) {
> + ret = CDN_EINVAL;
> + } else if (
> + (intr != LPDDR4_INTR_RESET_DONE) &&
> + (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
> + (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
> + (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
> + (intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
> + (intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
> + (intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
> + (intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
> + (intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
> + (intr != LPDDR4_INTR_MC_INIT_DONE) &&
> + (intr != LPDDR4_INTR_LP_DONE) &&
> + (intr != LPDDR4_INTR_BIST_DONE) &&
> + (intr != LPDDR4_INTR_WRAP_ERROR) &&
> + (intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
> + (intr != LPDDR4_INTR_RDLVL_ERROR) &&
> + (intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
> + (intr != LPDDR4_INTR_WRLVL_ERROR) &&
> + (intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
> + (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
> + (intr != LPDDR4_INTR_MRR_ERROR) &&
> + (intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
> + (intr != LPDDR4_INTR_WRLVL_REQ) &&
> + (intr != LPDDR4_INTR_RDLVL_REQ) &&
> + (intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
> + (intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
> + (intr != LPDDR4_INTR_LEVELING_DONE) &&
> + (intr != LPDDR4_INTR_PHY_ERROR) &&
> + (intr != LPDDR4_INTR_MR_READ_DONE) &&
> + (intr != LPDDR4_INTR_TEMP_CHANGE) &&
> + (intr != LPDDR4_INTR_TEMP_ALERT) &&
> + (intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
> + (intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
> + (intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
> + (intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
> + (intr != LPDDR4_INTR_MR_WRITE_DONE) &&
> + (intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
> + (intr != LPDDR4_INTR_DFI_INIT_STATE) &&
> + (intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
> + (intr != LPDDR4_INTR_TDFI_TO) &&
> + (intr != LPDDR4_INTR_DFS_DONE) &&
> + (intr != LPDDR4_INTR_DFS_STATUS) &&
> + (intr != LPDDR4_INTR_REFRESH_STATUS) &&
> + (intr != LPDDR4_INTR_ZQ_STATUS) &&
> + (intr != LPDDR4_INTR_SW_REQ_MODE) &&
> + (intr != LPDDR4_INTR_LOR_BITS)
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> + }
> +
> + return ret;
> +}
> +
> +static inline u32 lpddr4_intr_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_intr_ctlinterrupt intr)
> +{
> + u32 ret = 0;
> +
> + if (pd == NULL) {
> + ret = CDN_EINVAL;
> + } else if (
> + (intr != LPDDR4_INTR_RESET_DONE) &&
> + (intr != LPDDR4_INTR_BUS_ACCESS_ERROR) &&
> + (intr != LPDDR4_INTR_MULTIPLE_BUS_ACCESS_ERROR) &&
> + (intr != LPDDR4_INTR_ECC_MULTIPLE_CORR_ERROR) &&
> + (intr != LPDDR4_INTR_ECC_MULTIPLE_UNCORR_ERROR) &&
> + (intr != LPDDR4_INTR_ECC_WRITEBACK_EXEC_ERROR) &&
> + (intr != LPDDR4_INTR_ECC_SCRUB_DONE) &&
> + (intr != LPDDR4_INTR_ECC_SCRUB_ERROR) &&
> + (intr != LPDDR4_INTR_PORT_COMMAND_ERROR) &&
> + (intr != LPDDR4_INTR_MC_INIT_DONE) &&
> + (intr != LPDDR4_INTR_LP_DONE) &&
> + (intr != LPDDR4_INTR_BIST_DONE) &&
> + (intr != LPDDR4_INTR_WRAP_ERROR) &&
> + (intr != LPDDR4_INTR_INVALID_BURST_ERROR) &&
> + (intr != LPDDR4_INTR_RDLVL_ERROR) &&
> + (intr != LPDDR4_INTR_RDLVL_GATE_ERROR) &&
> + (intr != LPDDR4_INTR_WRLVL_ERROR) &&
> + (intr != LPDDR4_INTR_CA_TRAINING_ERROR) &&
> + (intr != LPDDR4_INTR_DFI_UPDATE_ERROR) &&
> + (intr != LPDDR4_INTR_MRR_ERROR) &&
> + (intr != LPDDR4_INTR_PHY_MASTER_ERROR) &&
> + (intr != LPDDR4_INTR_WRLVL_REQ) &&
> + (intr != LPDDR4_INTR_RDLVL_REQ) &&
> + (intr != LPDDR4_INTR_RDLVL_GATE_REQ) &&
> + (intr != LPDDR4_INTR_CA_TRAINING_REQ) &&
> + (intr != LPDDR4_INTR_LEVELING_DONE) &&
> + (intr != LPDDR4_INTR_PHY_ERROR) &&
> + (intr != LPDDR4_INTR_MR_READ_DONE) &&
> + (intr != LPDDR4_INTR_TEMP_CHANGE) &&
> + (intr != LPDDR4_INTR_TEMP_ALERT) &&
> + (intr != LPDDR4_INTR_SW_DQS_COMPLETE) &&
> + (intr != LPDDR4_INTR_DQS_OSC_BV_UPDATED) &&
> + (intr != LPDDR4_INTR_DQS_OSC_OVERFLOW) &&
> + (intr != LPDDR4_INTR_DQS_OSC_VAR_OUT) &&
> + (intr != LPDDR4_INTR_MR_WRITE_DONE) &&
> + (intr != LPDDR4_INTR_INHIBIT_DRAM_DONE) &&
> + (intr != LPDDR4_INTR_DFI_INIT_STATE) &&
> + (intr != LPDDR4_INTR_DLL_RESYNC_DONE) &&
> + (intr != LPDDR4_INTR_TDFI_TO) &&
> + (intr != LPDDR4_INTR_DFS_DONE) &&
> + (intr != LPDDR4_INTR_DFS_STATUS) &&
> + (intr != LPDDR4_INTR_REFRESH_STATUS) &&
> + (intr != LPDDR4_INTR_ZQ_STATUS) &&
> + (intr != LPDDR4_INTR_SW_REQ_MODE) &&
> + (intr != LPDDR4_INTR_LOR_BITS)
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> + }
> +
> + return ret;
> +}
> +
> +static inline u32 lpddr4_intr_sanityfunction3(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr, const bool *irqstatus)
> +{
> + u32 ret = 0;
> +
> + if (pd == NULL) {
> + ret = CDN_EINVAL;
> + } else if (irqstatus == NULL) {
> + ret = CDN_EINVAL;
> + } else if (
> + (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> + }
> +
> + return ret;
> +}
> +
> +static inline u32 lpddr4_intr_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_intr_phyindepinterrupt intr)
> +{
> + u32 ret = 0;
> +
> + if (pd == NULL) {
> + ret = CDN_EINVAL;
> + } else if (
> + (intr != LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_CONTROL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_CA_PARITY_ERR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_G_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_UPDATE_ERROR_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_WRLVL_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_CALVL_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_WDQLVL_REQ_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_LVL_DONE_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_BIST_DONE_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
> + (intr != LPDDR4_INTR_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> + }
> +
> + return ret;
> +}
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* LPDDR4_32BIT_SANITY_H */
> diff --git a/drivers/ram/k3-ddrss/lpddr4_if.h b/drivers/ram/k3-ddrss/lpddr4_if.h
> index 66ec3c5a27f6..472b28624030 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_if.h
> +++ b/drivers/ram/k3-ddrss/lpddr4_if.h
> @@ -1,578 +1,144 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> - **********************************************************************
> - * WARNING: This file is auto-generated using api-generator utility.
> - * api-generator: 12.02.13bb8d5
> - * Do not edit it manually.
> - **********************************************************************
> - * Cadence Core Driver for LPDDR4.
> - **********************************************************************
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef LPDDR4_IF_H
> #define LPDDR4_IF_H
>
> -#include <linux/types.h>
> +#include "cdn_stdtypes.h"
> +#ifdef CONFIG_K3_AM64_DDRSS
> +#include <lpddr4_16bit_if.h>
> +#else
> +#include <lpddr4_32bit_if.h>
> +#endif
>
> -/** @defgroup ConfigInfo Configuration and Hardware Operation Information
> - * The following definitions specify the driver operation environment that
> - * is defined by hardware configuration or client code. These defines are
> - * located in the header file of the core driver.
> - * @{
> - */
> -
> -/**********************************************************************
> -* Defines
> -**********************************************************************/
> -/** Number of chip-selects */
> -#define LPDDR4_MAX_CS (2U)
> -
> -/** Number of accessible registers for controller. */
> -#define LPDDR4_CTL_REG_COUNT (459U)
> -
> -/** Number of accessible registers for PHY Independent Module. */
> -#define LPDDR4_PHY_INDEP_REG_COUNT (300U)
> -
> -/** Number of accessible registers for PHY. */
> -#define LPDDR4_PHY_REG_COUNT (1423U)
> -
> -/**
> - * @}
> - */
> -
> -/** @defgroup DataStructure Dynamic Data Structures
> - * This section defines the data structures used by the driver to provide
> - * hardware information, modification and dynamic operation of the driver.
> - * These data structures are defined in the header file of the core driver
> - * and utilized by the API.
> - * @{
> - */
> -
> -/**********************************************************************
> -* Forward declarations
> -**********************************************************************/
> typedef struct lpddr4_config_s lpddr4_config;
> typedef struct lpddr4_privatedata_s lpddr4_privatedata;
> typedef struct lpddr4_debuginfo_s lpddr4_debuginfo;
> typedef struct lpddr4_fspmoderegs_s lpddr4_fspmoderegs;
> -typedef struct lpddr4_reginitdata_s lpddr4_reginitdata;
> -
> -/**********************************************************************
> -* Enumerations
> -**********************************************************************/
> -/** This is used to indicate whether the Controller, PHY, or PHY Independent module is addressed. */
> -typedef enum
> -{
> - LPDDR4_CTL_REGS = 0U,
> - LPDDR4_PHY_REGS = 1U,
> - LPDDR4_PHY_INDEP_REGS = 2U
> +
> +typedef enum {
> + LPDDR4_CTL_REGS = 0U,
> + LPDDR4_PHY_REGS = 1U,
> + LPDDR4_PHY_INDEP_REGS = 2U
> } lpddr4_regblock;
>
> -/** Controller status or error interrupts. */
> -typedef enum
> -{
> - LPDDR4_RESET_DONE = 0U,
> - LPDDR4_BUS_ACCESS_ERROR = 1U,
> - LPDDR4_MULTIPLE_BUS_ACCESS_ERROR = 2U,
> - LPDDR4_ECC_MULTIPLE_CORR_ERROR = 3U,
> - LPDDR4_ECC_MULTIPLE_UNCORR_ERROR = 4U,
> - LPDDR4_ECC_WRITEBACK_EXEC_ERROR = 5U,
> - LPDDR4_ECC_SCRUB_DONE = 6U,
> - LPDDR4_ECC_SCRUB_ERROR = 7U,
> - LPDDR4_PORT_COMMAND_ERROR = 8U,
> - LPDDR4_MC_INIT_DONE = 9U,
> - LPDDR4_LP_DONE = 10U,
> - LPDDR4_BIST_DONE = 11U,
> - LPDDR4_WRAP_ERROR = 12U,
> - LPDDR4_INVALID_BURST_ERROR = 13U,
> - LPDDR4_RDLVL_ERROR = 14U,
> - LPDDR4_RDLVL_GATE_ERROR = 15U,
> - LPDDR4_WRLVL_ERROR = 16U,
> - LPDDR4_CA_TRAINING_ERROR = 17U,
> - LPDDR4_DFI_UPDATE_ERROR = 18U,
> - LPDDR4_MRR_ERROR = 19U,
> - LPDDR4_PHY_MASTER_ERROR = 20U,
> - LPDDR4_WRLVL_REQ = 21U,
> - LPDDR4_RDLVL_REQ = 22U,
> - LPDDR4_RDLVL_GATE_REQ = 23U,
> - LPDDR4_CA_TRAINING_REQ = 24U,
> - LPDDR4_LEVELING_DONE = 25U,
> - LPDDR4_PHY_ERROR = 26U,
> - LPDDR4_MR_READ_DONE = 27U,
> - LPDDR4_TEMP_CHANGE = 28U,
> - LPDDR4_TEMP_ALERT = 29U,
> - LPDDR4_SW_DQS_COMPLETE = 30U,
> - LPDDR4_DQS_OSC_BV_UPDATED = 31U,
> - LPDDR4_DQS_OSC_OVERFLOW = 32U,
> - LPDDR4_DQS_OSC_VAR_OUT = 33U,
> - LPDDR4_MR_WRITE_DONE = 34U,
> - LPDDR4_INHIBIT_DRAM_DONE = 35U,
> - LPDDR4_DFI_INIT_STATE = 36U,
> - LPDDR4_DLL_RESYNC_DONE = 37U,
> - LPDDR4_TDFI_TO = 38U,
> - LPDDR4_DFS_DONE = 39U,
> - LPDDR4_DFS_STATUS = 40U,
> - LPDDR4_REFRESH_STATUS = 41U,
> - LPDDR4_ZQ_STATUS = 42U,
> - LPDDR4_SW_REQ_MODE = 43U,
> - LPDDR4_LOR_BITS = 44U
> -} lpddr4_ctlinterrupt;
> -
> -/** PHY Independent Module status or error interrupts. */
> -typedef enum
> -{
> - LPDDR4_PHY_INDEP_INIT_DONE_BIT = 0U,
> - LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT = 1U,
> - LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT = 2U,
> - LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT = 3U,
> - LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT = 4U,
> - LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT = 5U,
> - LPDDR4_PHY_INDEP_CALVL_ERROR_BIT = 6U,
> - LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT = 7U,
> - LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT = 8U,
> - LPDDR4_PHY_INDEP_RDLVL_REQ_BIT = 9U,
> - LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT = 10U,
> - LPDDR4_PHY_INDEP_WRLVL_REQ_BIT = 11U,
> - LPDDR4_PHY_INDEP_CALVL_REQ_BIT = 12U,
> - LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT = 13U,
> - LPDDR4_PHY_INDEP_LVL_DONE_BIT = 14U,
> - LPDDR4_PHY_INDEP_BIST_DONE_BIT = 15U,
> - LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT = 16U,
> - LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT = 17U
> -} lpddr4_phyindepinterrupt;
> -
> -/** List of informations and warnings from driver. */
> -typedef enum
> -{
> - LPDDR4_DRV_NONE = 0U,
> - LPDDR4_DRV_SOC_PLL_UPDATE = 1U
> +typedef enum {
> + LPDDR4_DRV_NONE = 0U,
> + LPDDR4_DRV_SOC_PLL_UPDATE = 1U
> } lpddr4_infotype;
>
> -/** Low power interface wake up timing parameters */
> -typedef enum
> -{
> - LPDDR4_LPI_PD_WAKEUP_FN = 0U,
> - LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
> - LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
> - LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
> - LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
> - LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
> - LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
> +typedef enum {
> + LPDDR4_LPI_PD_WAKEUP_FN = 0U,
> + LPDDR4_LPI_SR_SHORT_WAKEUP_FN = 1U,
> + LPDDR4_LPI_SR_LONG_WAKEUP_FN = 2U,
> + LPDDR4_LPI_SR_LONG_MCCLK_GATE_WAKEUP_FN = 3U,
> + LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN = 4U,
> + LPDDR4_LPI_SRPD_LONG_WAKEUP_FN = 5U,
> + LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN = 6U
> } lpddr4_lpiwakeupparam;
>
> -/** Half Datapath mode setting */
> -typedef enum
> -{
> - LPDDR4_REDUC_ON = 0U,
> - LPDDR4_REDUC_OFF = 1U
> +typedef enum {
> + LPDDR4_REDUC_ON = 0U,
> + LPDDR4_REDUC_OFF = 1U
> } lpddr4_reducmode;
>
> -/** ECC Control parameter setting */
> -typedef enum
> -{
> - LPDDR4_ECC_DISABLED = 0U,
> - LPDDR4_ECC_ENABLED = 1U,
> - LPDDR4_ECC_ERR_DETECT = 2U,
> - LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
> +typedef enum {
> + LPDDR4_ECC_DISABLED = 0U,
> + LPDDR4_ECC_ENABLED = 1U,
> + LPDDR4_ECC_ERR_DETECT = 2U,
> + LPDDR4_ECC_ERR_DETECT_CORRECT = 3U
> } lpddr4_eccenable;
>
> -/** Data Byte Inversion mode setting */
> -typedef enum
> -{
> - LPDDR4_DBI_RD_ON = 0U,
> - LPDDR4_DBI_RD_OFF = 1U,
> - LPDDR4_DBI_WR_ON = 2U,
> - LPDDR4_DBI_WR_OFF = 3U
> +typedef enum {
> + LPDDR4_DBI_RD_ON = 0U,
> + LPDDR4_DBI_RD_OFF = 1U,
> + LPDDR4_DBI_WR_ON = 2U,
> + LPDDR4_DBI_WR_OFF = 3U
> } lpddr4_dbimode;
>
> -/** Controller Frequency Set Point number */
> -typedef enum
> -{
> - LPDDR4_FSP_0 = 0U,
> - LPDDR4_FSP_1 = 1U,
> - LPDDR4_FSP_2 = 2U
> +typedef enum {
> + LPDDR4_FSP_0 = 0U,
> + LPDDR4_FSP_1 = 1U,
> + LPDDR4_FSP_2 = 2U
> } lpddr4_ctlfspnum;
>
> -/**********************************************************************
> -* Callbacks
> -**********************************************************************/
> -/**
> - * Reports informations and warnings that need to be communicated.
> - * Params:
> - * pD - driver state info specific to this instance.
> - * infoType - Type of information.
> - */
> -typedef void (*lpddr4_infocallback)(const lpddr4_privatedata* pd, lpddr4_infotype infotype);
> -
> -/**
> - * Reports interrupts received by the controller.
> - * Params:
> - * pD - driver state info specific to this instance.
> - * ctlInterrupt - Interrupt raised
> - * chipSelect - Chip for which interrupt raised
> - */
> -typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt ctlinterrupt, uint8_t chipselect);
> -
> -/**
> - * Reports interrupts received by the PHY Independent Module.
> - * Params:
> - * privateData - driver state info specific to this instance.
> - * phyIndepInterrupt - Interrupt raised
> - * chipSelect - Chip for which interrupt raised
> - */
> -typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt phyindepinterrupt, uint8_t chipselect);
> +typedef void (*lpddr4_infocallback)(const lpddr4_privatedata *pd, lpddr4_infotype infotype);
>
> -/**
> - * @}
> - */
> +typedef void (*lpddr4_ctlcallback)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt ctlinterrupt, u8 chipselect);
>
> -/** @defgroup DriverFunctionAPI Driver Function API
> - * Prototypes for the driver API functions. The user application can link statically to the
> - * necessary API functions and call them directly.
> - * @{
> - */
> +typedef void (*lpddr4_phyindepcallback)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt phyindepinterrupt, u8 chipselect);
>
> -/**********************************************************************
> -* API methods
> -**********************************************************************/
> +u32 lpddr4_probe(const lpddr4_config *config, u16 *configsize);
>
> -/**
> - * Checks configuration object.
> - * @param[in] config Driver/hardware configuration required.
> - * @param[out] configSize Size of memory allocations required.
> - * @return CDN_EOK on success (requirements structure filled).
> - * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
> - */
> -uint32_t lpddr4_probe(const lpddr4_config* config, uint16_t* configsize);
> -
> -/**
> - * Init function to be called after LPDDR4_probe() to set up the
> - * driver configuration. Memory should be allocated for drv_data
> - * (using the size determined using LPDDR4_probe) before calling this
> - * API. init_settings should be initialised with base addresses for
> - * PHY Indepenent Module, Controller and PHY before calling this
> - * function. If callbacks are required for interrupt handling, these
> - * should also be configured in init_settings.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cfg Specifies driver/hardware configuration.
> - * @return CDN_EOK on success
> - * @return EINVAL if illegal/inconsistent values in cfg.
> - * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
> - */
> -uint32_t lpddr4_init(lpddr4_privatedata* pd, const lpddr4_config* cfg);
> +u32 lpddr4_init(lpddr4_privatedata *pd, const lpddr4_config *cfg);
>
> -/**
> - * Start the driver.
> - * @param[in] pD Driver state info specific to this instance.
> - */
> -uint32_t lpddr4_start(const lpddr4_privatedata* pd);
> -
> -/**
> - * Read a register from the controller, PHY or PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
> - * @param[in] regOffset Register offset
> - * @param[out] regValue Register value read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regOffset if out of range or regValue is NULL
> - */
> -uint32_t lpddr4_readreg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
> -
> -/**
> - * Write a register in the controller, PHY or PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
> - * @param[in] regOffset Register offset
> - * @param[in] regValue Register value to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if regOffset is out of range or regValue is NULL
> - */
> -uint32_t lpddr4_writereg(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
> -
> -/**
> - * Read a memory mode register from DRAM
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
> - * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
> - * @param[out] mmrStatus Status of mode register read(mrr) instruction.
> - * @return CDN_EOK on success.
> - * @return EINVAL if regNumber is out of range or regValue is NULL
> - */
> -uint32_t lpddr4_getmmrregister(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
> -
> -/**
> - * Write a memory mode register in DRAM
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
> - * @param[out] mrwStatus Status of mode register write(mrw) instruction.
> - * @return CDN_EOK on success.
> - * @return EINVAL if regNumber is out of range or regValue is NULL
> - */
> -uint32_t lpddr4_setmmrregister(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
> -
> -/**
> - * Write a set of initialisation values to the controller registers
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] regValues Register values to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> -uint32_t lpddr4_writectlconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
> -
> -/**
> - * Write a set of initialisation values to the PHY registers
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] regValues Register values to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> -uint32_t lpddr4_writephyconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
> -
> -/**
> - * Write a set of initialisation values to the PHY Independent Module
> - * registers
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] regValues Register values to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> -uint32_t lpddr4_writephyindepconfig(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
> -
> -/**
> - * Read values of the controller registers in bulk (Set 'updateCtlReg'
> - * to read) and store in memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] regValues Register values which are read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> -uint32_t lpddr4_readctlconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
> -
> -/**
> - * Read the values of the PHY module registers in bulk (Set
> - * 'updatePhyReg' to read) and store in memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] regValues Register values which are read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> -uint32_t lpddr4_readphyconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
> -
> -/**
> - * Read the values of the PHY Independent module registers in bulk(Set
> - * 'updatePhyIndepReg' to read) and store in memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] regValues Register values which are read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> -uint32_t lpddr4_readphyindepconfig(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
> -
> -/**
> - * Read the current interrupt mask for the controller
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mask Value of interrupt mask
> - * @return CDN_EOK on success.
> - * @return EINVAL if mask pointer is NULL
> - */
> -uint32_t lpddr4_getctlinterruptmask(const lpddr4_privatedata* pd, uint64_t* mask);
> -
> -/**
> - * Sets the interrupt mask for the controller
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mask Value of interrupt mask to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if mask pointer is NULL
> - */
> -uint32_t lpddr4_setctlinterruptmask(const lpddr4_privatedata* pd, const uint64_t* mask);
> -
> -/**
> - * Check whether a specific controller interrupt is active
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be checked
> - * @param[out] irqStatus Status of the interrupt, TRUE if active
> - * @return CDN_EOK on success.
> - * @return EINVAL if intr is not valid
> - */
> -uint32_t lpddr4_checkctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
> -
> -/**
> - * Acknowledge a specific controller interrupt
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be acknowledged
> - * @return CDN_EOK on success.
> - * @return EINVAL if intr is not valid
> - */
> -uint32_t lpddr4_ackctlinterrupt(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
> -
> -/**
> - * Read the current interrupt mask for the PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mask Value of interrupt mask
> - * @return CDN_EOK on success.
> - * @return EINVAL if mask pointer is NULL
> - */
> -uint32_t lpddr4_getphyindepinterruptmask(const lpddr4_privatedata* pd, uint32_t* mask);
> -
> -/**
> - * Sets the interrupt mask for the PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mask Value of interrupt mask to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if mask pointer is NULL
> - */
> -uint32_t lpddr4_setphyindepinterruptmask(const lpddr4_privatedata* pd, const uint32_t* mask);
> -
> -/**
> - * Check whether a specific PHY Independent Module interrupt is active
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be checked
> - * @param[out] irqStatus Status of the interrupt, TRUE if active
> - * @return CDN_EOK on success.
> - * @return EINVAL if intr is not valid
> - */
> -uint32_t lpddr4_checkphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
> -
> -/**
> - * Acknowledge a specific PHY Independent Module interrupt
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be acknowledged
> - * @return CDN_EOK on success.
> - * @return EINVAL if intr is not valid
> - */
> -uint32_t lpddr4_ackphyindepinterrupt(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
> -
> -/**
> - * Retrieve status information after a failed init. The
> - * DebugStructInfo will be filled in with error codes which can be
> - * referenced against the driver documentation for further details.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] debugInfo status
> - * @return CDN_EOK on success.
> - * @return EINVAL if debugInfo is NULL
> - */
> -uint32_t lpddr4_getdebuginitinfo(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
> -
> -/**
> - * Get the current value of Low power Interface wake up time.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] lpiWakeUpParam LPI timing parameter
> - * @param[in] fspNum Frequency copy
> - * @param[out] cycles Timing value(in cycles)
> - * @return CDN_EOK on success.
> - * @return EINVAL if powerMode is NULL
> - */
> -uint32_t lpddr4_getlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
> -
> -/**
> - * Set the current value of Low power Interface wake up time.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] lpiWakeUpParam LPI timing parameter
> - * @param[in] fspNum Frequency copy
> - * @param[in] cycles Timing value(in cycles)
> - * @return CDN_EOK on success.
> - * @return EINVAL if powerMode is NULL
> - */
> -uint32_t lpddr4_setlpiwakeuptime(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
> -
> -/**
> - * Get the current value for ECC auto correction
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] eccParam ECC parameter setting
> - * @return CDN_EOK on success.
> - * @return EINVAL if on_off is NULL
> - */
> -uint32_t lpddr4_geteccenable(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
> -
> -/**
> - * Set the value for ECC auto correction. This API must be called
> - * before startup of memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] eccParam ECC control parameter setting
> - * @return CDN_EOK on success.
> - * @return EINVAL if on_off is NULL
> - */
> -uint32_t lpddr4_seteccenable(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
> -
> -/**
> - * Get the current value for the Half Datapath option
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mode Half Datapath setting
> - * @return CDN_EOK on success.
> - * @return EINVAL if mode is NULL
> - */
> -uint32_t lpddr4_getreducmode(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
> -
> -/**
> - * Set the value for the Half Datapath option. This API must be
> - * called before startup of memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mode Half Datapath setting
> - * @return CDN_EOK on success.
> - * @return EINVAL if mode is NULL
> - */
> -uint32_t lpddr4_setreducmode(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
> -
> -/**
> - * Get the current value for Data Bus Inversion setting. This will be
> - * compared with the current DRAM setting using the MR3 register.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] on_off DBI read value
> - * @return CDN_EOK on success.
> - * @return EINVAL if on_off is NULL
> - */
> -uint32_t lpddr4_getdbireadmode(const lpddr4_privatedata* pd, bool* on_off);
> -
> -/**
> - * Get the current value for Data Bus Inversion setting. This will be
> - * compared with the current DRAM setting using the MR3 register.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] on_off DBI write value
> - * @return CDN_EOK on success.
> - * @return EINVAL if on_off is NULL
> - */
> -uint32_t lpddr4_getdbiwritemode(const lpddr4_privatedata* pd, bool* on_off);
> -
> -/**
> - * Set the mode for Data Bus Inversion. This will also be set in DRAM
> - * using the MR3 controller register. This API must be called before
> - * startup of memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mode status
> - * @return CDN_EOK on success.
> - * @return EINVAL if mode is NULL
> - */
> -uint32_t lpddr4_setdbimode(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
> -
> -/**
> - * Get the current value for the refresh rate (reading Refresh per
> - * command timing).
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] fspNum Frequency set number
> - * @param[out] cycles Refresh rate (in cycles)
> - * @return CDN_EOK on success.
> - * @return EINVAL if rate is NULL
> - */
> -uint32_t lpddr4_getrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
> -
> -/**
> - * Set the refresh rate (writing Refresh per command timing).
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] fspNum Frequency set number
> - * @param[in] cycles Refresh rate (in cycles)
> - * @return CDN_EOK on success.
> - * @return EINVAL if rate is NULL
> - */
> -uint32_t lpddr4_setrefreshrate(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
> -
> -/**
> - * Handle Refreshing per chip select
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] trefInterval status
> - * @return CDN_EOK on success.
> - * @return EINVAL if chipSelect is invalid
> - */
> -uint32_t lpddr4_refreshperchipselect(const lpddr4_privatedata* pd, const uint32_t trefinterval);
> +u32 lpddr4_start(const lpddr4_privatedata *pd);
> +
> +u32 lpddr4_readreg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
> +
> +u32 lpddr4_writereg(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
> +
> +u32 lpddr4_getmmrregister(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
> +
> +u32 lpddr4_setmmrregister(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
> +
> +u32 lpddr4_writectlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> +u32 lpddr4_writephyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> +u32 lpddr4_writephyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> +u32 lpddr4_readctlconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> +u32 lpddr4_readphyconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> +u32 lpddr4_readphyindepconfig(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> +u32 lpddr4_getctlinterruptmask(const lpddr4_privatedata *pd, u64 *mask);
> +
> +u32 lpddr4_setctlinterruptmask(const lpddr4_privatedata *pd, const u64 *mask);
> +
> +u32 lpddr4_checkctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
> +
> +u32 lpddr4_ackctlinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
> +
> +u32 lpddr4_getphyindepinterruptmask(const lpddr4_privatedata *pd, u32 *mask);
> +
> +u32 lpddr4_setphyindepinterruptmask(const lpddr4_privatedata *pd, const u32 *mask);
> +
> +u32 lpddr4_checkphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
> +
> +u32 lpddr4_ackphyindepinterrupt(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
> +
> +u32 lpddr4_getdebuginitinfo(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
> +
> +u32 lpddr4_getlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
> +
> +u32 lpddr4_setlpiwakeuptime(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
> +
> +u32 lpddr4_geteccenable(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
> +
> +u32 lpddr4_seteccenable(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
> +
> +u32 lpddr4_getreducmode(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
> +
> +u32 lpddr4_setreducmode(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
> +
> +u32 lpddr4_getdbireadmode(const lpddr4_privatedata *pd, bool *on_off);
> +
> +u32 lpddr4_getdbiwritemode(const lpddr4_privatedata *pd, bool *on_off);
> +
> +u32 lpddr4_setdbimode(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
> +
> +u32 lpddr4_getrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
> +
> +u32 lpddr4_setrefreshrate(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
> +
> +u32 lpddr4_refreshperchipselect(const lpddr4_privatedata *pd, const u32 trefinterval);
>
> #endif /* LPDDR4_IF_H */
> diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.c b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
> index 35b3db67074d..370242f5bd23 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_obj_if.c
> +++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.c
> @@ -1,54 +1,50 @@
> // SPDX-License-Identifier: BSD-3-Clause
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> - **********************************************************************
> - * WARNING: This file is auto-generated using api-generator utility.
> - * api-generator: 12.02.13bb8d5
> - * Do not edit it manually.
> - **********************************************************************
> - * Cadence Core Driver for LPDDR4.
> - **********************************************************************
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #include "lpddr4_obj_if.h"
>
> -LPDDR4_OBJ *lpddr4_getinstance(void)
> +lpddr4_obj *lpddr4_getinstance(void)
> {
> - static LPDDR4_OBJ driver = {
> - .probe = lpddr4_probe,
> - .init = lpddr4_init,
> - .start = lpddr4_start,
> - .readreg = lpddr4_readreg,
> - .writereg = lpddr4_writereg,
> - .getmmrregister = lpddr4_getmmrregister,
> - .setmmrregister = lpddr4_setmmrregister,
> - .writectlconfig = lpddr4_writectlconfig,
> - .writephyconfig = lpddr4_writephyconfig,
> - .writephyindepconfig = lpddr4_writephyindepconfig,
> - .readctlconfig = lpddr4_readctlconfig,
> - .readphyconfig = lpddr4_readphyconfig,
> - .readphyindepconfig = lpddr4_readphyindepconfig,
> - .getctlinterruptmask = lpddr4_getctlinterruptmask,
> - .setctlinterruptmask = lpddr4_setctlinterruptmask,
> - .checkctlinterrupt = lpddr4_checkctlinterrupt,
> - .ackctlinterrupt = lpddr4_ackctlinterrupt,
> - .getphyindepinterruptmask = lpddr4_getphyindepinterruptmask,
> - .setphyindepinterruptmask = lpddr4_setphyindepinterruptmask,
> - .checkphyindepinterrupt = lpddr4_checkphyindepinterrupt,
> - .ackphyindepinterrupt = lpddr4_ackphyindepinterrupt,
> - .getdebuginitinfo = lpddr4_getdebuginitinfo,
> - .getlpiwakeuptime = lpddr4_getlpiwakeuptime,
> - .setlpiwakeuptime = lpddr4_setlpiwakeuptime,
> - .geteccenable = lpddr4_geteccenable,
> - .seteccenable = lpddr4_seteccenable,
> - .getreducmode = lpddr4_getreducmode,
> - .setreducmode = lpddr4_setreducmode,
> - .getdbireadmode = lpddr4_getdbireadmode,
> - .getdbiwritemode = lpddr4_getdbiwritemode,
> - .setdbimode = lpddr4_setdbimode,
> - .getrefreshrate = lpddr4_getrefreshrate,
> - .setrefreshrate = lpddr4_setrefreshrate,
> - .refreshperchipselect = lpddr4_refreshperchipselect,
> + static lpddr4_obj driver = {
> + .probe = lpddr4_probe,
> + .init = lpddr4_init,
> + .start = lpddr4_start,
> + .readreg = lpddr4_readreg,
> + .writereg = lpddr4_writereg,
> + .getmmrregister = lpddr4_getmmrregister,
> + .setmmrregister = lpddr4_setmmrregister,
> + .writectlconfig = lpddr4_writectlconfig,
> + .writephyconfig = lpddr4_writephyconfig,
> + .writephyindepconfig = lpddr4_writephyindepconfig,
> + .readctlconfig = lpddr4_readctlconfig,
> + .readphyconfig = lpddr4_readphyconfig,
> + .readphyindepconfig = lpddr4_readphyindepconfig,
> + .getctlinterruptmask = lpddr4_getctlinterruptmask,
> + .setctlinterruptmask = lpddr4_setctlinterruptmask,
> + .checkctlinterrupt = lpddr4_checkctlinterrupt,
> + .ackctlinterrupt = lpddr4_ackctlinterrupt,
> + .getphyindepinterruptmask = lpddr4_getphyindepinterruptmask,
> + .setphyindepinterruptmask = lpddr4_setphyindepinterruptmask,
> + .checkphyindepinterrupt = lpddr4_checkphyindepinterrupt,
> + .ackphyindepinterrupt = lpddr4_ackphyindepinterrupt,
> + .getdebuginitinfo = lpddr4_getdebuginitinfo,
> + .getlpiwakeuptime = lpddr4_getlpiwakeuptime,
> + .setlpiwakeuptime = lpddr4_setlpiwakeuptime,
> + .geteccenable = lpddr4_geteccenable,
> + .seteccenable = lpddr4_seteccenable,
> + .getreducmode = lpddr4_getreducmode,
> + .setreducmode = lpddr4_setreducmode,
> + .getdbireadmode = lpddr4_getdbireadmode,
> + .getdbiwritemode = lpddr4_getdbiwritemode,
> + .setdbimode = lpddr4_setdbimode,
> + .getrefreshrate = lpddr4_getrefreshrate,
> + .setrefreshrate = lpddr4_setrefreshrate,
> + .refreshperchipselect = lpddr4_refreshperchipselect,
> };
>
> return &driver;
> diff --git a/drivers/ram/k3-ddrss/lpddr4_obj_if.h b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
> index 33dae6f7edac..d538e61b7478 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_obj_if.h
> +++ b/drivers/ram/k3-ddrss/lpddr4_obj_if.h
> @@ -1,383 +1,86 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> - **********************************************************************
> - * WARNING: This file is auto-generated using api-generator utility.
> - * api-generator: 12.02.13bb8d5
> - * Do not edit it manually.
> - **********************************************************************
> - * Cadence Core Driver for LPDDR4.
> - **********************************************************************
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
> -#ifndef LPDDR4_OBJ_IF_H
> -#define LPDDR4_OBJ_IF_H
> +
> +#ifndef lpddr4_obj_if_h
> +#define lpddr4_obj_if_h
>
> #include "lpddr4_if.h"
>
> -/** @defgroup DriverObject Driver API Object
> - * API listing for the driver. The API is contained in the object as
> - * function pointers in the object structure. As the actual functions
> - * resides in the Driver Object, the client software must first use the
> - * global GetInstance function to obtain the Driver Object Pointer.
> - * The actual APIs then can be invoked using obj->(api_name)() syntax.
> - * These functions are defined in the header file of the core driver
> - * and utilized by the API.
> - * @{
> - */
> +typedef struct lpddr4_obj_s {
> + u32 (*probe)(const lpddr4_config *config, u16 *configsize);
>
> -/**********************************************************************
> -* API methods
> -**********************************************************************/
> -typedef struct lpddr4_obj_s
> -{
> - /**
> - * Checks configuration object.
> - * @param[in] config Driver/hardware configuration required.
> - * @param[out] configSize Size of memory allocations required.
> - * @return CDN_EOK on success (requirements structure filled).
> - * @return ENOTSUP if configuration cannot be supported due to driver/hardware constraints.
> - */
> - uint32_t (*probe)(const lpddr4_config* config, uint16_t* configsize);
> -
> - /**
> - * Init function to be called after LPDDR4_probe() to set up the
> - * driver configuration. Memory should be allocated for drv_data
> - * (using the size determined using LPDDR4_probe) before calling
> - * this API. init_settings should be initialised with base addresses
> - * for PHY Indepenent Module, Controller and PHY before calling this
> - * function. If callbacks are required for interrupt handling, these
> - * should also be configured in init_settings.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cfg Specifies driver/hardware configuration.
> - * @return CDN_EOK on success
> - * @return EINVAL if illegal/inconsistent values in cfg.
> - * @return ENOTSUP if hardware has an inconsistent configuration or doesn't support feature(s) required by 'config' parameters.
> - */
> - uint32_t (*init)(lpddr4_privatedata* pd, const lpddr4_config* cfg);
> -
> - /**
> - * Start the driver.
> - * @param[in] pD Driver state info specific to this instance.
> - */
> - uint32_t (*start)(const lpddr4_privatedata* pd);
> -
> - /**
> - * Read a register from the controller, PHY or PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
> - * @param[in] regOffset Register offset
> - * @param[out] regValue Register value read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regOffset if out of range or regValue is NULL
> - */
> - uint32_t (*readreg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t* regvalue);
> -
> - /**
> - * Write a register in the controller, PHY or PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
> - * @param[in] regOffset Register offset
> - * @param[in] regValue Register value to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if regOffset is out of range or regValue is NULL
> - */
> - uint32_t (*writereg)(const lpddr4_privatedata* pd, lpddr4_regblock cpp, uint32_t regoffset, uint32_t regvalue);
> -
> - /**
> - * Read a memory mode register from DRAM
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] readModeRegVal Value to set in 'read_modereg' parameter.
> - * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
> - * @param[out] mmrStatus Status of mode register read(mrr) instruction.
> - * @return CDN_EOK on success.
> - * @return EINVAL if regNumber is out of range or regValue is NULL
> - */
> - uint32_t (*getmmrregister)(const lpddr4_privatedata* pd, uint32_t readmoderegval, uint64_t* mmrvalue, uint8_t* mmrstatus);
> -
> - /**
> - * Write a memory mode register in DRAM
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] writeModeRegVal Value to set in 'write_modereg' parameter.
> - * @param[out] mrwStatus Status of mode register write(mrw) instruction.
> - * @return CDN_EOK on success.
> - * @return EINVAL if regNumber is out of range or regValue is NULL
> - */
> - uint32_t (*setmmrregister)(const lpddr4_privatedata* pd, uint32_t writemoderegval, uint8_t* mrwstatus);
> -
> - /**
> - * Write a set of initialisation values to the controller registers
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] regValues Register values to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> - uint32_t (*writectlconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
> -
> - /**
> - * Write a set of initialisation values to the PHY registers
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] regValues Register values to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> - uint32_t (*writephyconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
> -
> - /**
> - * Write a set of initialisation values to the PHY Independent Module
> - * registers
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] regValues Register values to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> - uint32_t (*writephyindepconfig)(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
> -
> - /**
> - * Read values of the controller registers in bulk (Set
> - * 'updateCtlReg' to read) and store in memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] regValues Register values which are read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> - uint32_t (*readctlconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
> -
> - /**
> - * Read the values of the PHY module registers in bulk (Set
> - * 'updatePhyReg' to read) and store in memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] regValues Register values which are read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> - uint32_t (*readphyconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
> -
> - /**
> - * Read the values of the PHY Independent module registers in
> - * bulk(Set 'updatePhyIndepReg' to read) and store in memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] regValues Register values which are read
> - * @return CDN_EOK on success.
> - * @return EINVAL if regValues is NULL
> - */
> - uint32_t (*readphyindepconfig)(const lpddr4_privatedata* pd, lpddr4_reginitdata* regvalues);
> -
> - /**
> - * Read the current interrupt mask for the controller
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mask Value of interrupt mask
> - * @return CDN_EOK on success.
> - * @return EINVAL if mask pointer is NULL
> - */
> - uint32_t (*getctlinterruptmask)(const lpddr4_privatedata* pd, uint64_t* mask);
> -
> - /**
> - * Sets the interrupt mask for the controller
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mask Value of interrupt mask to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if mask pointer is NULL
> - */
> - uint32_t (*setctlinterruptmask)(const lpddr4_privatedata* pd, const uint64_t* mask);
> -
> - /**
> - * Check whether a specific controller interrupt is active
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be checked
> - * @param[out] irqStatus Status of the interrupt, TRUE if active
> - * @return CDN_EOK on success.
> - * @return EINVAL if intr is not valid
> - */
> - uint32_t (*checkctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr, bool* irqstatus);
> -
> - /**
> - * Acknowledge a specific controller interrupt
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be acknowledged
> - * @return CDN_EOK on success.
> - * @return EINVAL if intr is not valid
> - */
> - uint32_t (*ackctlinterrupt)(const lpddr4_privatedata* pd, lpddr4_ctlinterrupt intr);
> -
> - /**
> - * Read the current interrupt mask for the PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mask Value of interrupt mask
> - * @return CDN_EOK on success.
> - * @return EINVAL if mask pointer is NULL
> - */
> - uint32_t (*getphyindepinterruptmask)(const lpddr4_privatedata* pd, uint32_t* mask);
> -
> - /**
> - * Sets the interrupt mask for the PHY Independent Module
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mask Value of interrupt mask to be written
> - * @return CDN_EOK on success.
> - * @return EINVAL if mask pointer is NULL
> - */
> - uint32_t (*setphyindepinterruptmask)(const lpddr4_privatedata* pd, const uint32_t* mask);
> -
> - /**
> - * Check whether a specific PHY Independent Module interrupt is
> - * active
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be checked
> - * @param[out] irqStatus Status of the interrupt, TRUE if active
> - * @return CDN_EOK on success.
> - * @return EINVAL if intr is not valid
> - */
> - uint32_t (*checkphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr, bool* irqstatus);
> -
> - /**
> - * Acknowledge a specific PHY Independent Module interrupt
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be acknowledged
> - * @return CDN_EOK on success.
> - * @return EINVAL if intr is not valid
> - */
> - uint32_t (*ackphyindepinterrupt)(const lpddr4_privatedata* pd, lpddr4_phyindepinterrupt intr);
> -
> - /**
> - * Retrieve status information after a failed init. The
> - * DebugStructInfo will be filled in with error codes which can be
> - * referenced against the driver documentation for further details.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] debugInfo status
> - * @return CDN_EOK on success.
> - * @return EINVAL if debugInfo is NULL
> - */
> - uint32_t (*getdebuginitinfo)(const lpddr4_privatedata* pd, lpddr4_debuginfo* debuginfo);
> -
> - /**
> - * Get the current value of Low power Interface wake up time.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] lpiWakeUpParam LPI timing parameter
> - * @param[in] fspNum Frequency copy
> - * @param[out] cycles Timing value(in cycles)
> - * @return CDN_EOK on success.
> - * @return EINVAL if powerMode is NULL
> - */
> - uint32_t (*getlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
> -
> - /**
> - * Set the current value of Low power Interface wake up time.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] lpiWakeUpParam LPI timing parameter
> - * @param[in] fspNum Frequency copy
> - * @param[in] cycles Timing value(in cycles)
> - * @return CDN_EOK on success.
> - * @return EINVAL if powerMode is NULL
> - */
> - uint32_t (*setlpiwakeuptime)(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
> -
> - /**
> - * Get the current value for ECC auto correction
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] eccParam ECC parameter setting
> - * @return CDN_EOK on success.
> - * @return EINVAL if on_off is NULL
> - */
> - uint32_t (*geteccenable)(const lpddr4_privatedata* pd, lpddr4_eccenable* eccparam);
> -
> - /**
> - * Set the value for ECC auto correction. This API must be called
> - * before startup of memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] eccParam ECC control parameter setting
> - * @return CDN_EOK on success.
> - * @return EINVAL if on_off is NULL
> - */
> - uint32_t (*seteccenable)(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
> -
> - /**
> - * Get the current value for the Half Datapath option
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mode Half Datapath setting
> - * @return CDN_EOK on success.
> - * @return EINVAL if mode is NULL
> - */
> - uint32_t (*getreducmode)(const lpddr4_privatedata* pd, lpddr4_reducmode* mode);
> -
> - /**
> - * Set the value for the Half Datapath option. This API must be
> - * called before startup of memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mode Half Datapath setting
> - * @return CDN_EOK on success.
> - * @return EINVAL if mode is NULL
> - */
> - uint32_t (*setreducmode)(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
> -
> - /**
> - * Get the current value for Data Bus Inversion setting. This will
> - * be compared with the current DRAM setting using the MR3
> - * register.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] on_off DBI read value
> - * @return CDN_EOK on success.
> - * @return EINVAL if on_off is NULL
> - */
> - uint32_t (*getdbireadmode)(const lpddr4_privatedata* pd, bool* on_off);
> -
> - /**
> - * Get the current value for Data Bus Inversion setting. This will
> - * be compared with the current DRAM setting using the MR3
> - * register.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] on_off DBI write value
> - * @return CDN_EOK on success.
> - * @return EINVAL if on_off is NULL
> - */
> - uint32_t (*getdbiwritemode)(const lpddr4_privatedata* pd, bool* on_off);
> -
> - /**
> - * Set the mode for Data Bus Inversion. This will also be set in DRAM
> - * using the MR3 controller register. This API must be called
> - * before startup of memory.
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mode status
> - * @return CDN_EOK on success.
> - * @return EINVAL if mode is NULL
> - */
> - uint32_t (*setdbimode)(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
> -
> - /**
> - * Get the current value for the refresh rate (reading Refresh per
> - * command timing).
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] fspNum Frequency set number
> - * @param[out] cycles Refresh rate (in cycles)
> - * @return CDN_EOK on success.
> - * @return EINVAL if rate is NULL
> - */
> - uint32_t (*getrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, uint32_t* cycles);
> -
> - /**
> - * Set the refresh rate (writing Refresh per command timing).
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] fspNum Frequency set number
> - * @param[in] cycles Refresh rate (in cycles)
> - * @return CDN_EOK on success.
> - * @return EINVAL if rate is NULL
> - */
> - uint32_t (*setrefreshrate)(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
> -
> - /**
> - * Handle Refreshing per chip select
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] trefInterval status
> - * @return CDN_EOK on success.
> - * @return EINVAL if chipSelect is invalid
> - */
> - uint32_t (*refreshperchipselect)(const lpddr4_privatedata* pd, const uint32_t trefinterval);
> -
> -} LPDDR4_OBJ;
> -
> -/**
> - * In order to access the LPDDR4 APIs, the upper layer software must call
> - * this global function to obtain the pointer to the driver object.
> - * @return LPDDR4_OBJ* Driver Object Pointer
> - */
> -extern LPDDR4_OBJ *lpddr4_getinstance(void);
> + u32 (*init)(lpddr4_privatedata *pd, const lpddr4_config *cfg);
> +
> + u32 (*start)(const lpddr4_privatedata *pd);
> +
> + u32 (*readreg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 *regvalue);
> +
> + u32 (*writereg)(const lpddr4_privatedata *pd, lpddr4_regblock cpp, u32 regoffset, u32 regvalue);
> +
> + u32 (*getmmrregister)(const lpddr4_privatedata *pd, u32 readmoderegval, u64 *mmrvalue, u8 *mmrstatus);
> +
> + u32 (*setmmrregister)(const lpddr4_privatedata *pd, u32 writemoderegval, u8 *mrwstatus);
> +
> + u32 (*writectlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> + u32 (*writephyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> + u32 (*writephyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> + u32 (*readctlconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> + u32 (*readphyconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> + u32 (*readphyindepconfig)(const lpddr4_privatedata *pd, u32 regvalues[], u16 regnum[], u16 regcount);
> +
> + u32 (*getctlinterruptmask)(const lpddr4_privatedata *pd, u64 *mask);
> +
> + u32 (*setctlinterruptmask)(const lpddr4_privatedata *pd, const u64 *mask);
> +
> + u32 (*checkctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr, bool *irqstatus);
> +
> + u32 (*ackctlinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_ctlinterrupt intr);
> +
> + u32 (*getphyindepinterruptmask)(const lpddr4_privatedata *pd, u32 *mask);
> +
> + u32 (*setphyindepinterruptmask)(const lpddr4_privatedata *pd, const u32 *mask);
> +
> + u32 (*checkphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr, bool *irqstatus);
> +
> + u32 (*ackphyindepinterrupt)(const lpddr4_privatedata *pd, lpddr4_intr_phyindepinterrupt intr);
> +
> + u32 (*getdebuginitinfo)(const lpddr4_privatedata *pd, lpddr4_debuginfo *debuginfo);
> +
> + u32 (*getlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, u32 *cycles);
> +
> + u32 (*setlpiwakeuptime)(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
> +
> + u32 (*geteccenable)(const lpddr4_privatedata *pd, lpddr4_eccenable *eccparam);
> +
> + u32 (*seteccenable)(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
> +
> + u32 (*getreducmode)(const lpddr4_privatedata *pd, lpddr4_reducmode *mode);
> +
> + u32 (*setreducmode)(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
> +
> + u32 (*getdbireadmode)(const lpddr4_privatedata *pd, bool *on_off);
> +
> + u32 (*getdbiwritemode)(const lpddr4_privatedata *pd, bool *on_off);
> +
> + u32 (*setdbimode)(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
> +
> + u32 (*getrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, u32 *tref, u32 *tras_max);
> +
> + u32 (*setrefreshrate)(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
> +
> + u32 (*refreshperchipselect)(const lpddr4_privatedata *pd, const u32 trefinterval);
> +} lpddr4_obj;
> +
> +extern lpddr4_obj *lpddr4_getinstance(void);
>
> -#endif /* LPDDR4_OBJ_IF_H */
> +#endif /* lpddr4_obj_if_h */
> diff --git a/drivers/ram/k3-ddrss/lpddr4_sanity.h b/drivers/ram/k3-ddrss/lpddr4_sanity.h
> index 0f0fc2767c11..2de9023eacec 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_sanity.h
> +++ b/drivers/ram/k3-ddrss/lpddr4_sanity.h
> @@ -1,60 +1,44 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> - **********************************************************************
> - * WARNING: This file is auto-generated using api-generator utility.
> - * api-generator: 12.02.13bb8d5
> - * Do not edit it manually.
> - **********************************************************************
> - * Cadence Core Driver for LPDDR4.
> - **********************************************************************
> - */
> -
> -/**
> - * This file contains sanity API functions. The purpose of sanity functions
> - * is to check input parameters validity. They take the same parameters as
> - * original API functions and return 0 on success or EINVAL on wrong parameter
> - * value(s).
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> #ifndef LPDDR4_SANITY_H
> #define LPDDR4_SANITY_H
>
> -#include <errno.h>
> -#include <linux/types.h>
> +#include "cdn_errno.h"
> +#include "cdn_stdtypes.h"
> #include "lpddr4_if.h"
> -
> -#define CDN_EOK 0U /* no error */
> -
> -static inline uint32_t lpddr4_configsf(const lpddr4_config *obj);
> -static inline uint32_t lpddr4_privatedatasf(const lpddr4_privatedata *obj);
> -static inline uint32_t lpddr4_reginitdatasf(const lpddr4_reginitdata *obj);
> -
> -static inline uint32_t lpddr4_sanityfunction1(const lpddr4_config* config, const uint16_t* configsize);
> -static inline uint32_t lpddr4_sanityfunction2(const lpddr4_privatedata* pd, const lpddr4_config* cfg);
> -static inline uint32_t lpddr4_sanityfunction3(const lpddr4_privatedata* pd);
> -static inline uint32_t lpddr4_sanityfunction4(const lpddr4_privatedata* pd, const lpddr4_regblock cpp, const uint32_t* regvalue);
> -static inline uint32_t lpddr4_sanityfunction5(const lpddr4_privatedata* pd, const lpddr4_regblock cpp);
> -static inline uint32_t lpddr4_sanityfunction6(const lpddr4_privatedata* pd, const uint64_t* mmrvalue, const uint8_t* mmrstatus);
> -static inline uint32_t lpddr4_sanityfunction7(const lpddr4_privatedata* pd, const uint8_t* mrwstatus);
> -static inline uint32_t lpddr4_sanityfunction8(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
> -static inline uint32_t lpddr4_sanityfunction11(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues);
> -static inline uint32_t lpddr4_sanityfunction14(const lpddr4_privatedata* pd, const uint64_t* mask);
> -static inline uint32_t lpddr4_sanityfunction15(const lpddr4_privatedata* pd, const uint64_t* mask);
> -static inline uint32_t lpddr4_sanityfunction16(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr, const bool* irqstatus);
> -static inline uint32_t lpddr4_sanityfunction17(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr);
> -static inline uint32_t lpddr4_sanityfunction18(const lpddr4_privatedata* pd, const uint32_t* mask);
> -static inline uint32_t lpddr4_sanityfunction20(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr, const bool* irqstatus);
> -static inline uint32_t lpddr4_sanityfunction21(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr);
> -static inline uint32_t lpddr4_sanityfunction22(const lpddr4_privatedata* pd, const lpddr4_debuginfo* debuginfo);
> -static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
> -static inline uint32_t lpddr4_sanityfunction25(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
> -static inline uint32_t lpddr4_sanityfunction26(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam);
> -static inline uint32_t lpddr4_sanityfunction27(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
> -static inline uint32_t lpddr4_sanityfunction28(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode);
> -static inline uint32_t lpddr4_sanityfunction29(const lpddr4_privatedata* pd, const bool* on_off);
> -static inline uint32_t lpddr4_sanityfunction31(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode);
> -static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles);
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +static inline u32 lpddr4_configsf(const lpddr4_config *obj);
> +static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj);
> +
> +static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize);
> +static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg);
> +static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd);
> +static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue);
> +static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp);
> +static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus);
> +static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus);
> +static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask);
> +static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask);
> +static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask);
> +static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo);
> +static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles);
> +static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
> +static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam);
> +static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
> +static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode);
> +static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off);
> +static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode);
> +static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
> +static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max);
>
> #define lpddr4_probesf lpddr4_sanityfunction1
> #define lpddr4_initsf lpddr4_sanityfunction2
> @@ -63,813 +47,225 @@ static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, con
> #define lpddr4_writeregsf lpddr4_sanityfunction5
> #define lpddr4_getmmrregistersf lpddr4_sanityfunction6
> #define lpddr4_setmmrregistersf lpddr4_sanityfunction7
> -#define lpddr4_writectlconfigsf lpddr4_sanityfunction8
> -#define lpddr4_writephyconfigsf lpddr4_sanityfunction8
> -#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction8
> -#define lpddr4_readctlconfigsf lpddr4_sanityfunction11
> -#define lpddr4_readphyconfigsf lpddr4_sanityfunction11
> -#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction11
> +#define lpddr4_writectlconfigsf lpddr4_sanityfunction3
> +#define lpddr4_writephyconfigsf lpddr4_sanityfunction3
> +#define lpddr4_writephyindepconfigsf lpddr4_sanityfunction3
> +#define lpddr4_readctlconfigsf lpddr4_sanityfunction3
> +#define lpddr4_readphyconfigsf lpddr4_sanityfunction3
> +#define lpddr4_readphyindepconfigsf lpddr4_sanityfunction3
> #define lpddr4_getctlinterruptmasksf lpddr4_sanityfunction14
> #define lpddr4_setctlinterruptmasksf lpddr4_sanityfunction15
> -#define lpddr4_checkctlinterruptsf lpddr4_sanityfunction16
> -#define lpddr4_ackctlinterruptsf lpddr4_sanityfunction17
> -#define lpddr4_getphyindepinterruptmsf lpddr4_sanityfunction18
> -#define lpddr4_setphyindepinterruptmsf lpddr4_sanityfunction18
> -#define lpddr4_checkphyindepinterrupsf lpddr4_sanityfunction20
> -#define lpddr4_ackphyindepinterruptsf lpddr4_sanityfunction21
> -#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction22
> -#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction23
> -#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction23
> -#define lpddr4_geteccenablesf lpddr4_sanityfunction25
> -#define lpddr4_seteccenablesf lpddr4_sanityfunction26
> -#define lpddr4_getreducmodesf lpddr4_sanityfunction27
> -#define lpddr4_setreducmodesf lpddr4_sanityfunction28
> -#define lpddr4_getdbireadmodesf lpddr4_sanityfunction29
> -#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction29
> -#define lpddr4_setdbimodesf lpddr4_sanityfunction31
> -#define lpddr4_getrefreshratesf lpddr4_sanityfunction32
> -#define lpddr4_setrefreshratesf lpddr4_sanityfunction32
> +#define LPDDR4_GetPhyIndepInterruptMSF lpddr4_sanityfunction16
> +#define LPDDR4_SetPhyIndepInterruptMSF lpddr4_sanityfunction16
Some camelcase macros here, any chance to fix them?
> +#define lpddr4_getdebuginitinfosf lpddr4_sanityfunction18
> +#define lpddr4_getlpiwakeuptimesf lpddr4_sanityfunction19
> +#define lpddr4_setlpiwakeuptimesf lpddr4_sanityfunction19
> +#define lpddr4_geteccenablesf lpddr4_sanityfunction21
> +#define lpddr4_seteccenablesf lpddr4_sanityfunction22
> +#define lpddr4_getreducmodesf lpddr4_sanityfunction23
> +#define lpddr4_setreducmodesf lpddr4_sanityfunction24
> +#define lpddr4_getdbireadmodesf lpddr4_sanityfunction25
> +#define lpddr4_getdbiwritemodesf lpddr4_sanityfunction25
> +#define lpddr4_setdbimodesf lpddr4_sanityfunction27
> +#define lpddr4_getrefreshratesf lpddr4_sanityfunction28
> +#define lpddr4_setrefreshratesf lpddr4_sanityfunction29
> #define lpddr4_refreshperchipselectsf lpddr4_sanityfunction3
>
> -/**
> - * Function to validate struct Config
> - *
> - * @param[in] obj pointer to struct to be verified
> - * @returns 0 for valid
> - * @returns EINVAL for invalid
> - */
> -static inline uint32_t lpddr4_configsf(const lpddr4_config *obj)
> -{
> - uint32_t ret = 0;
> -
> - if (obj == NULL)
> - {
> - ret = EINVAL;
> - }
> -
> - return ret;
> -}
> -
> -/**
> - * Function to validate struct PrivateData
> - *
> - * @param[in] obj pointer to struct to be verified
> - * @returns 0 for valid
> - * @returns EINVAL for invalid
> - */
> -static inline uint32_t lpddr4_privatedatasf(const lpddr4_privatedata *obj)
> +static inline u32 lpddr4_configsf(const lpddr4_config *obj)
> {
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> if (obj == NULL)
> - {
> - ret = EINVAL;
> - }
> + ret = CDN_EINVAL;
>
> return ret;
> }
>
> -/**
> - * Function to validate struct RegInitData
> - *
> - * @param[in] obj pointer to struct to be verified
> - * @returns 0 for valid
> - * @returns EINVAL for invalid
> - */
> -static inline uint32_t lpddr4_reginitdatasf(const lpddr4_reginitdata *obj)
> +static inline u32 lpddr4_privatedatasf(const lpddr4_privatedata *obj)
> {
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> if (obj == NULL)
> - {
> - ret = EINVAL;
> - }
> + ret = CDN_EINVAL;
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] config Driver/hardware configuration required.
> - * @param[out] configSize Size of memory allocations required.
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction1(const lpddr4_config* config, const uint16_t* configsize)
> +static inline u32 lpddr4_sanityfunction1(const lpddr4_config *config, const u16 *configsize)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (configsize == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_configsf(config) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (configsize == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_configsf(config) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cfg Specifies driver/hardware configuration.
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction2(const lpddr4_privatedata* pd, const lpddr4_config* cfg)
> +static inline u32 lpddr4_sanityfunction2(const lpddr4_privatedata *pd, const lpddr4_config *cfg)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_configsf(cfg) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_configsf(cfg) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction3(const lpddr4_privatedata* pd)
> +static inline u32 lpddr4_sanityfunction3(const lpddr4_privatedata *pd)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> + if (lpddr4_privatedatasf(pd) == CDN_EINVAL)
> + ret = CDN_EINVAL;
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
> - * @param[out] regValue Register value read
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction4(const lpddr4_privatedata* pd, const lpddr4_regblock cpp, const uint32_t* regvalue)
> +static inline u32 lpddr4_sanityfunction4(const lpddr4_privatedata *pd, const lpddr4_regblock cpp, const u32 *regvalue)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (regvalue == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> + if (regvalue == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (
> (cpp != LPDDR4_CTL_REGS) &&
> (cpp != LPDDR4_PHY_REGS) &&
> (cpp != LPDDR4_PHY_INDEP_REGS)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] cpp Indicates whether controller, PHY or PHY Independent Module register
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction5(const lpddr4_privatedata* pd, const lpddr4_regblock cpp)
> +static inline u32 lpddr4_sanityfunction5(const lpddr4_privatedata *pd, const lpddr4_regblock cpp)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> + if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (
> (cpp != LPDDR4_CTL_REGS) &&
> (cpp != LPDDR4_PHY_REGS) &&
> (cpp != LPDDR4_PHY_INDEP_REGS)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> - }
> -
> - return ret;
> -}
> -
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mmrValue Value which is read from memory mode register(mmr) for all devices.
> - * @param[out] mmrStatus Status of mode register read(mrr) instruction.
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction6(const lpddr4_privatedata* pd, const uint64_t* mmrvalue, const uint8_t* mmrstatus)
> -{
> - /* Declaring return variable */
> - uint32_t ret = 0;
> -
> - if (mmrvalue == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (mmrstatus == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> - }
> -
> - return ret;
> -}
> -
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mrwStatus Status of mode register write(mrw) instruction.
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction7(const lpddr4_privatedata* pd, const uint8_t* mrwstatus)
> -{
> - /* Declaring return variable */
> - uint32_t ret = 0;
> -
> - if (mrwstatus == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> - }
> -
> - return ret;
> -}
> -
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] regValues Register values to be written
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction8(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues)
> -{
> - /* Declaring return variable */
> - uint32_t ret = 0;
> -
> - if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_reginitdatasf(regvalues) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> - }
> -
> - return ret;
> -}
> -
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] regValues Register values which are read
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction11(const lpddr4_privatedata* pd, const lpddr4_reginitdata* regvalues)
> -{
> - /* Declaring return variable */
> - uint32_t ret = 0;
> -
> - if (regvalues == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> - }
> -
> - return ret;
> -}
> -
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mask Value of interrupt mask
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction14(const lpddr4_privatedata* pd, const uint64_t* mask)
> -{
> - /* Declaring return variable */
> - uint32_t ret = 0;
> -
> - if (mask == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> - }
> -
> - return ret;
> -}
> -
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mask Value of interrupt mask to be written
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction15(const lpddr4_privatedata* pd, const uint64_t* mask)
> -{
> - /* Declaring return variable */
> - uint32_t ret = 0;
> -
> - if (mask == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be checked
> - * @param[out] irqStatus Status of the interrupt, TRUE if active
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction16(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr, const bool* irqstatus)
> +static inline u32 lpddr4_sanityfunction6(const lpddr4_privatedata *pd, const u64 *mmrvalue, const u8 *mmrstatus)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (irqstatus == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> - (intr != LPDDR4_RESET_DONE) &&
> - (intr != LPDDR4_BUS_ACCESS_ERROR) &&
> - (intr != LPDDR4_MULTIPLE_BUS_ACCESS_ERROR) &&
> - (intr != LPDDR4_ECC_MULTIPLE_CORR_ERROR) &&
> - (intr != LPDDR4_ECC_MULTIPLE_UNCORR_ERROR) &&
> - (intr != LPDDR4_ECC_WRITEBACK_EXEC_ERROR) &&
> - (intr != LPDDR4_ECC_SCRUB_DONE) &&
> - (intr != LPDDR4_ECC_SCRUB_ERROR) &&
> - (intr != LPDDR4_PORT_COMMAND_ERROR) &&
> - (intr != LPDDR4_MC_INIT_DONE) &&
> - (intr != LPDDR4_LP_DONE) &&
> - (intr != LPDDR4_BIST_DONE) &&
> - (intr != LPDDR4_WRAP_ERROR) &&
> - (intr != LPDDR4_INVALID_BURST_ERROR) &&
> - (intr != LPDDR4_RDLVL_ERROR) &&
> - (intr != LPDDR4_RDLVL_GATE_ERROR) &&
> - (intr != LPDDR4_WRLVL_ERROR) &&
> - (intr != LPDDR4_CA_TRAINING_ERROR) &&
> - (intr != LPDDR4_DFI_UPDATE_ERROR) &&
> - (intr != LPDDR4_MRR_ERROR) &&
> - (intr != LPDDR4_PHY_MASTER_ERROR) &&
> - (intr != LPDDR4_WRLVL_REQ) &&
> - (intr != LPDDR4_RDLVL_REQ) &&
> - (intr != LPDDR4_RDLVL_GATE_REQ) &&
> - (intr != LPDDR4_CA_TRAINING_REQ) &&
> - (intr != LPDDR4_LEVELING_DONE) &&
> - (intr != LPDDR4_PHY_ERROR) &&
> - (intr != LPDDR4_MR_READ_DONE) &&
> - (intr != LPDDR4_TEMP_CHANGE) &&
> - (intr != LPDDR4_TEMP_ALERT) &&
> - (intr != LPDDR4_SW_DQS_COMPLETE) &&
> - (intr != LPDDR4_DQS_OSC_BV_UPDATED) &&
> - (intr != LPDDR4_DQS_OSC_OVERFLOW) &&
> - (intr != LPDDR4_DQS_OSC_VAR_OUT) &&
> - (intr != LPDDR4_MR_WRITE_DONE) &&
> - (intr != LPDDR4_INHIBIT_DRAM_DONE) &&
> - (intr != LPDDR4_DFI_INIT_STATE) &&
> - (intr != LPDDR4_DLL_RESYNC_DONE) &&
> - (intr != LPDDR4_TDFI_TO) &&
> - (intr != LPDDR4_DFS_DONE) &&
> - (intr != LPDDR4_DFS_STATUS) &&
> - (intr != LPDDR4_REFRESH_STATUS) &&
> - (intr != LPDDR4_ZQ_STATUS) &&
> - (intr != LPDDR4_SW_REQ_MODE) &&
> - (intr != LPDDR4_LOR_BITS)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (mmrvalue == NULL) {
> + ret = CDN_EINVAL;
> + } else if (mmrstatus == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be acknowledged
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction17(const lpddr4_privatedata* pd, const lpddr4_ctlinterrupt intr)
> +static inline u32 lpddr4_sanityfunction7(const lpddr4_privatedata *pd, const u8 *mrwstatus)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> - (intr != LPDDR4_RESET_DONE) &&
> - (intr != LPDDR4_BUS_ACCESS_ERROR) &&
> - (intr != LPDDR4_MULTIPLE_BUS_ACCESS_ERROR) &&
> - (intr != LPDDR4_ECC_MULTIPLE_CORR_ERROR) &&
> - (intr != LPDDR4_ECC_MULTIPLE_UNCORR_ERROR) &&
> - (intr != LPDDR4_ECC_WRITEBACK_EXEC_ERROR) &&
> - (intr != LPDDR4_ECC_SCRUB_DONE) &&
> - (intr != LPDDR4_ECC_SCRUB_ERROR) &&
> - (intr != LPDDR4_PORT_COMMAND_ERROR) &&
> - (intr != LPDDR4_MC_INIT_DONE) &&
> - (intr != LPDDR4_LP_DONE) &&
> - (intr != LPDDR4_BIST_DONE) &&
> - (intr != LPDDR4_WRAP_ERROR) &&
> - (intr != LPDDR4_INVALID_BURST_ERROR) &&
> - (intr != LPDDR4_RDLVL_ERROR) &&
> - (intr != LPDDR4_RDLVL_GATE_ERROR) &&
> - (intr != LPDDR4_WRLVL_ERROR) &&
> - (intr != LPDDR4_CA_TRAINING_ERROR) &&
> - (intr != LPDDR4_DFI_UPDATE_ERROR) &&
> - (intr != LPDDR4_MRR_ERROR) &&
> - (intr != LPDDR4_PHY_MASTER_ERROR) &&
> - (intr != LPDDR4_WRLVL_REQ) &&
> - (intr != LPDDR4_RDLVL_REQ) &&
> - (intr != LPDDR4_RDLVL_GATE_REQ) &&
> - (intr != LPDDR4_CA_TRAINING_REQ) &&
> - (intr != LPDDR4_LEVELING_DONE) &&
> - (intr != LPDDR4_PHY_ERROR) &&
> - (intr != LPDDR4_MR_READ_DONE) &&
> - (intr != LPDDR4_TEMP_CHANGE) &&
> - (intr != LPDDR4_TEMP_ALERT) &&
> - (intr != LPDDR4_SW_DQS_COMPLETE) &&
> - (intr != LPDDR4_DQS_OSC_BV_UPDATED) &&
> - (intr != LPDDR4_DQS_OSC_OVERFLOW) &&
> - (intr != LPDDR4_DQS_OSC_VAR_OUT) &&
> - (intr != LPDDR4_MR_WRITE_DONE) &&
> - (intr != LPDDR4_INHIBIT_DRAM_DONE) &&
> - (intr != LPDDR4_DFI_INIT_STATE) &&
> - (intr != LPDDR4_DLL_RESYNC_DONE) &&
> - (intr != LPDDR4_TDFI_TO) &&
> - (intr != LPDDR4_DFS_DONE) &&
> - (intr != LPDDR4_DFS_STATUS) &&
> - (intr != LPDDR4_REFRESH_STATUS) &&
> - (intr != LPDDR4_ZQ_STATUS) &&
> - (intr != LPDDR4_SW_REQ_MODE) &&
> - (intr != LPDDR4_LOR_BITS)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (mrwstatus == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mask Value of interrupt mask
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction18(const lpddr4_privatedata* pd, const uint32_t* mask)
> +static inline u32 lpddr4_sanityfunction14(const lpddr4_privatedata *pd, const u64 *mask)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (mask == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (mask == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be checked
> - * @param[out] irqStatus Status of the interrupt, TRUE if active
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction20(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr, const bool* irqstatus)
> +static inline u32 lpddr4_sanityfunction15(const lpddr4_privatedata *pd, const u64 *mask)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (irqstatus == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> - (intr != LPDDR4_PHY_INDEP_INIT_DONE_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_CALVL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_RDLVL_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_WRLVL_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_CALVL_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_LVL_DONE_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_BIST_DONE_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (mask == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] intr Interrupt to be acknowledged
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction21(const lpddr4_privatedata* pd, const lpddr4_phyindepinterrupt intr)
> +static inline u32 lpddr4_sanityfunction16(const lpddr4_privatedata *pd, const u32 *mask)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> - (intr != LPDDR4_PHY_INDEP_INIT_DONE_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_CONTROL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_CA_PARITY_ERR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_RDLVL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_WRLVL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_CALVL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_WDQLVL_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_UPDATE_ERROR_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_RDLVL_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_RDLVL_GATE_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_WRLVL_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_CALVL_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_WDQLVL_REQ_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_LVL_DONE_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_BIST_DONE_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_TDFI_INIT_TIME_OUT_BIT) &&
> - (intr != LPDDR4_PHY_INDEP_DLL_LOCK_STATE_CHANGE_BIT)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (mask == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] debugInfo status
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction22(const lpddr4_privatedata* pd, const lpddr4_debuginfo* debuginfo)
> +static inline u32 lpddr4_sanityfunction18(const lpddr4_privatedata *pd, const lpddr4_debuginfo *debuginfo)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (debuginfo == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (debuginfo == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] lpiWakeUpParam LPI timing parameter
> - * @param[in] fspNum Frequency copy
> - * @param[out] cycles Timing value(in cycles)
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, const lpddr4_lpiwakeupparam* lpiwakeupparam, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles)
> +static inline u32 lpddr4_sanityfunction19(const lpddr4_privatedata *pd, const lpddr4_lpiwakeupparam *lpiwakeupparam, const lpddr4_ctlfspnum *fspnum, const u32 *cycles)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> -
> - if (lpiwakeupparam == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (fspnum == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (cycles == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> + u32 ret = 0;
> +
> + if (lpiwakeupparam == NULL) {
> + ret = CDN_EINVAL;
> + } else if (fspnum == NULL) {
> + ret = CDN_EINVAL;
> + } else if (cycles == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (
> (*lpiwakeupparam != LPDDR4_LPI_PD_WAKEUP_FN) &&
> (*lpiwakeupparam != LPDDR4_LPI_SR_SHORT_WAKEUP_FN) &&
> (*lpiwakeupparam != LPDDR4_LPI_SR_LONG_WAKEUP_FN) &&
> @@ -877,289 +273,173 @@ static inline uint32_t lpddr4_sanityfunction23(const lpddr4_privatedata* pd, con
> (*lpiwakeupparam != LPDDR4_LPI_SRPD_SHORT_WAKEUP_FN) &&
> (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_WAKEUP_FN) &&
> (*lpiwakeupparam != LPDDR4_LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_FN)
> - )
> - {
> - ret = EINVAL;
> - }
> - else if (
> + ) {
> + ret = CDN_EINVAL;
> + } else if (
> (*fspnum != LPDDR4_FSP_0) &&
> (*fspnum != LPDDR4_FSP_1) &&
> (*fspnum != LPDDR4_FSP_2)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] eccParam ECC parameter setting
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction25(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam)
> +static inline u32 lpddr4_sanityfunction21(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (eccparam == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (eccparam == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] eccParam ECC control parameter setting
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction26(const lpddr4_privatedata* pd, const lpddr4_eccenable* eccparam)
> +static inline u32 lpddr4_sanityfunction22(const lpddr4_privatedata *pd, const lpddr4_eccenable *eccparam)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (eccparam == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> + if (eccparam == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (
> (*eccparam != LPDDR4_ECC_DISABLED) &&
> (*eccparam != LPDDR4_ECC_ENABLED) &&
> (*eccparam != LPDDR4_ECC_ERR_DETECT) &&
> (*eccparam != LPDDR4_ECC_ERR_DETECT_CORRECT)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] mode Half Datapath setting
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction27(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode)
> +static inline u32 lpddr4_sanityfunction23(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (mode == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (mode == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mode Half Datapath setting
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction28(const lpddr4_privatedata* pd, const lpddr4_reducmode* mode)
> +static inline u32 lpddr4_sanityfunction24(const lpddr4_privatedata *pd, const lpddr4_reducmode *mode)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (mode == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> + if (mode == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (
> (*mode != LPDDR4_REDUC_ON) &&
> (*mode != LPDDR4_REDUC_OFF)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[out] on_off DBI read value
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction29(const lpddr4_privatedata* pd, const bool* on_off)
> +static inline u32 lpddr4_sanityfunction25(const lpddr4_privatedata *pd, const bool *on_off)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (on_off == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + if (on_off == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] mode status
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction31(const lpddr4_privatedata* pd, const lpddr4_dbimode* mode)
> +static inline u32 lpddr4_sanityfunction27(const lpddr4_privatedata *pd, const lpddr4_dbimode *mode)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> + u32 ret = 0;
>
> - if (mode == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> + if (mode == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (
> (*mode != LPDDR4_DBI_RD_ON) &&
> (*mode != LPDDR4_DBI_RD_OFF) &&
> (*mode != LPDDR4_DBI_WR_ON) &&
> (*mode != LPDDR4_DBI_WR_OFF)
> - )
> - {
> - ret = EINVAL;
> - }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> -/**
> - * A common function to check the validity of API functions with
> - * following parameter types
> - * @param[in] pD Driver state info specific to this instance.
> - * @param[in] fspNum Frequency set number
> - * @param[out] cycles Refresh rate (in cycles)
> - * @return 0 success
> - * @return EINVAL invalid parameters
> - */
> -static inline uint32_t lpddr4_sanityfunction32(const lpddr4_privatedata* pd, const lpddr4_ctlfspnum* fspnum, const uint32_t* cycles)
> +static inline u32 lpddr4_sanityfunction28(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
> {
> - /* Declaring return variable */
> - uint32_t ret = 0;
> -
> - if (fspnum == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (cycles == NULL)
> - {
> - ret = EINVAL;
> - }
> - else if (lpddr4_privatedatasf(pd) == EINVAL)
> - {
> - ret = EINVAL;
> - }
> - else if (
> + u32 ret = 0;
> +
> + if (fspnum == NULL) {
> + ret = CDN_EINVAL;
> + } else if (tref == NULL) {
> + ret = CDN_EINVAL;
> + } else if (tras_max == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (
> (*fspnum != LPDDR4_FSP_0) &&
> (*fspnum != LPDDR4_FSP_1) &&
> (*fspnum != LPDDR4_FSP_2)
> - )
> - {
> - ret = EINVAL;
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> }
> - else
> - {
> - /*
> - * All 'if ... else if' constructs shall be terminated with an 'else' statement
> - * (MISRA2012-RULE-15_7-3)
> - */
> +
> + return ret;
> +}
> +
> +static inline u32 lpddr4_sanityfunction29(const lpddr4_privatedata *pd, const lpddr4_ctlfspnum *fspnum, const u32 *tref, const u32 *tras_max)
> +{
> + u32 ret = 0;
> +
> + if (fspnum == NULL) {
> + ret = CDN_EINVAL;
> + } else if (tref == NULL) {
> + ret = CDN_EINVAL;
> + } else if (tras_max == NULL) {
> + ret = CDN_EINVAL;
> + } else if (lpddr4_privatedatasf(pd) == CDN_EINVAL) {
> + ret = CDN_EINVAL;
> + } else if (
> + (*fspnum != LPDDR4_FSP_0) &&
> + (*fspnum != LPDDR4_FSP_1) &&
> + (*fspnum != LPDDR4_FSP_2)
> + ) {
> + ret = CDN_EINVAL;
> + } else {
> }
>
> return ret;
> }
>
> +#ifdef __cplusplus
> +}
> +#endif
> +
> #endif /* LPDDR4_SANITY_H */
> diff --git a/drivers/ram/k3-ddrss/lpddr4_structs_if.h b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
> index dc6dd3570e00..6d2ee47bb5f7 100644
> --- a/drivers/ram/k3-ddrss/lpddr4_structs_if.h
> +++ b/drivers/ram/k3-ddrss/lpddr4_structs_if.h
> @@ -1,121 +1,51 @@
> /* SPDX-License-Identifier: BSD-3-Clause */
> -/**********************************************************************
> - * Copyright (C) 2012-2019 Cadence Design Systems, Inc.
> - **********************************************************************
> - * WARNING: This file is auto-generated using api-generator utility.
> - * api-generator: 12.02.13bb8d5
> - * Do not edit it manually.
> - **********************************************************************
> - * Cadence Core Driver for LPDDR4.
> - **********************************************************************
> +/*
> + * Cadence DDR Driver
> + *
> + * Copyright (C) 2012-2021 Cadence Design Systems, Inc.
> + * Copyright (C) 2018-2021 Texas Instruments Incorporated - https://www.ti.com/
> */
> +
> #ifndef LPDDR4_STRUCTS_IF_H
> #define LPDDR4_STRUCTS_IF_H
>
> -#include <linux/types.h>
> +#include "cdn_stdtypes.h"
> #include "lpddr4_if.h"
>
> -/** @defgroup DataStructure Dynamic Data Structures
> - * This section defines the data structures used by the driver to provide
> - * hardware information, modification and dynamic operation of the driver.
> - * These data structures are defined in the header file of the core driver
> - * and utilized by the API.
> - * @{
> - */
> -
> -/**********************************************************************
> -* Structures and unions
> -**********************************************************************/
> -/**
> - * Configuration of device.
> - * Object of this type is used for probe and init functions.
> - */
> -struct lpddr4_config_s
> -{
> - /** Base address of controller registers */
> - struct lpddr4_ctlregs_s* ctlbase;
> - /** Information/warning handler */
> +struct lpddr4_config_s {
> + struct lpddr4_ctlregs_s *ctlbase;
> lpddr4_infocallback infohandler;
> - /** Controller interrupt handler */
> lpddr4_ctlcallback ctlinterrupthandler;
> - /** PHY Independent Module interrupt handler */
> lpddr4_phyindepcallback phyindepinterrupthandler;
> };
>
> -/**
> - * Structure contains private data for Core Driver that should not be used by
> - * upper layers. This is not a part of API and manipulating of those data may cause
> - * unpredictable behavior of Core Driver.
> - */
> -struct lpddr4_privatedata_s
> -{
> - /** Base address of controller registers */
> - struct lpddr4_ctlregs_s* ctlbase;
> - /** Information/warning handler */
> +struct lpddr4_privatedata_s {
> + struct lpddr4_ctlregs_s *ctlbase;
> lpddr4_infocallback infohandler;
> - /** Controller interrupt handler */
> lpddr4_ctlcallback ctlinterrupthandler;
> - /** PHY Independent Module interrupt handler */
> lpddr4_phyindepcallback phyindepinterrupthandler;
> };
>
> -/** Structure to contain debug information reported by the driver. */
> -struct lpddr4_debuginfo_s
> -{
> - /** PLL Lock error. */
> - bool pllerror;
> - /** I/O calibration error. */
> - bool iocaliberror;
> - /** RX offset error. */
> - bool rxoffseterror;
> - /** CA training error. */
> - bool catraingerror;
> - /** Write levelling error. */
> - bool wrlvlerror;
> - /** Gate Level error. */
> - bool gatelvlerror;
> - /** Read Level error. */
> - bool readlvlerror;
> - /** Write DQ training error. */
> - bool dqtrainingerror;
> -};
> -
> -/** Frequency Set Point mode register values */
> -struct lpddr4_fspmoderegs_s
> -{
> - /** MR1 register data for the FSP. */
> - uint8_t mr1data_fn[LPDDR4_MAX_CS];
> - /** MR2 register data for the FSP. */
> - uint8_t mr2data_fn[LPDDR4_MAX_CS];
> - /** MR3 register data for the FSP. */
> - uint8_t mr3data_fn[LPDDR4_MAX_CS];
> - /** MR11 register data for the FSP. */
> - uint8_t mr11data_fn[LPDDR4_MAX_CS];
> - /** MR12 register data for the FSP. */
> - uint8_t mr12data_fn[LPDDR4_MAX_CS];
> - /** MR13 register data for the FSP. */
> - uint8_t mr13data_fn[LPDDR4_MAX_CS];
> - /** MR14 register data for the FSP. */
> - uint8_t mr14data_fn[LPDDR4_MAX_CS];
> - /** MR22 register data for the selected frequency. */
> - uint8_t mr22data_fn[LPDDR4_MAX_CS];
> +struct lpddr4_debuginfo_s {
> + u8 pllerror;
> + u8 iocaliberror;
> + u8 rxoffseterror;
> + u8 catraingerror;
> + u8 wrlvlerror;
> + u8 gatelvlerror;
> + u8 readlvlerror;
> + u8 dqtrainingerror;
> };
>
> -/** Structure to hold data set to initalise registers. */
> -struct lpddr4_reginitdata_s
> -{
> - /** Register initialisation data for the Controller. */
> - uint32_t denalictlreg[LPDDR4_CTL_REG_COUNT];
> - /** Should be set to true, if the corresponding denaliCtlReg element has been updated. */
> - bool updatectlreg[LPDDR4_CTL_REG_COUNT];
> - /** Register initialisation data for PHY independent module. */
> - uint32_t denaliphyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
> - /** Should be set to true, if the corresponding denaliPhyIndepReg element has been updated. */
> - bool updatephyindepreg[LPDDR4_PHY_INDEP_REG_COUNT];
> - /** Register initialisation data for the PHY. */
> - uint32_t denaliphyreg[LPDDR4_PHY_REG_COUNT];
> - /** Should be set to true, if the corresponding denaliPhyReg element has been updated. */
> - bool updatephyreg[LPDDR4_PHY_REG_COUNT];
> +struct lpddr4_fspmoderegs_s {
> + u8 mr1data_fn[LPDDR4_INTR_MAX_CS];
> + u8 mr2data_fn[LPDDR4_INTR_MAX_CS];
> + u8 mr3data_fn[LPDDR4_INTR_MAX_CS];
> + u8 mr11data_fn[LPDDR4_INTR_MAX_CS];
> + u8 mr12data_fn[LPDDR4_INTR_MAX_CS];
> + u8 mr13data_fn[LPDDR4_INTR_MAX_CS];
> + u8 mr14data_fn[LPDDR4_INTR_MAX_CS];
> + u8 mr22data_fn[LPDDR4_INTR_MAX_CS];
> };
>
> #endif /* LPDDR4_STRUCTS_IF_H */
>
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