[PATCH] riscv: Split SiFive CLINT support between SPL and U-Boot proper
rickchen36 at gmail.com
Tue May 18 04:05:11 CEST 2021
> From: Bin Meng <bmeng.cn at gmail.com>
> Sent: Tuesday, May 11, 2021 8:04 PM
> To: Rick Jian-Zhi Chen(陳建志) <rick at andestech.com>; Sean Anderson <seanga2 at gmail.com>; u-boot at lists.denx.de
> Cc: Anup Patel <anup.patel at wdc.com>; Bin Meng <bmeng.cn at gmail.com>
> Subject: [PATCH] riscv: Split SiFive CLINT support between SPL and U-Boot proper
> At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction.
> This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot.
> To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options.
> Signed-off-by: Bin Meng <bmeng.cn at gmail.com>
> arch/riscv/Kconfig | 9 ++++++++-
> arch/riscv/cpu/fu540/Kconfig | 2 +-
> arch/riscv/cpu/generic/Kconfig | 3 ++-
> arch/riscv/include/asm/global_data.h | 2 +-
> arch/riscv/lib/Makefile | 2 +-
> drivers/timer/Makefile | 2 +-
> 6 files changed, 14 insertions(+), 6 deletions(-)
Reviewed-by: Rick Chen <rick at andestech.com>
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