[PATCH] spi: zynqmp_gqspi: Fix write issue

[Michal Simek]

On 5/25/21 2:36 PM, Ashok Reddy Soma wrote:
> Enable manual start in zynqmp_qspi_fill_gen_fifo().
> Also enable GQSPI_IXR_GFNFULL_MASK and check for it instead of
> GQSPI_IXR_GFEMTY_MASK.
> 
> Add dummy write to genfifo register in chipselect.
> 
> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma at xilinx.com>
> ---
> 
>  drivers/spi/zynqmp_gqspi.c | 18 +++++++++++++++++-
>  1 file changed, 17 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
> index 17780066ae..fc81b07343 100644
> --- a/drivers/spi/zynqmp_gqspi.c
> +++ b/drivers/spi/zynqmp_gqspi.c
> @@ -39,6 +39,7 @@
>  #define GQSPI_IXR_TXFULL_MASK		0x00000008 /* QSPI TX FIFO is full */
>  #define GQSPI_IXR_RXNEMTY_MASK		0x00000010 /* QSPI RX FIFO Not Empty */
>  #define GQSPI_IXR_GFEMTY_MASK		0x00000080 /* QSPI Generic FIFO Empty */
> +#define GQSPI_IXR_GFNFULL_MASK		0x00000200 /* QSPI GENFIFO not full */
>  #define GQSPI_IXR_ALL_MASK		(GQSPI_IXR_TXNFULL_MASK | \
>  					 GQSPI_IXR_RXNEMTY_MASK)
>  
> @@ -238,9 +239,21 @@ static void zynqmp_qspi_fill_gen_fifo(struct zynqmp_qspi_priv *priv,
>  				      u32 gqspi_fifo_reg)
>  {
>  	struct zynqmp_qspi_regs *regs = priv->regs;
> +	u32 config_reg, ier;
>  	int ret = 0;
>  
> -	ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFEMTY_MASK, 1,
> +	config_reg = readl(&regs->confr);
> +	/* Manual start if needed */
> +	config_reg |= GQSPI_STRT_GEN_FIFO;
> +	writel(config_reg, &regs->confr);
> +
> +	/* Enable interrupts */
> +	ier = readl(&regs->ier);
> +	ier |= GQSPI_IXR_GFNFULL_MASK;
> +	writel(ier, &regs->ier);
> +
> +	/* Wait until the fifo is not full to write the new command */
> +	ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_GFNFULL_MASK, 1,
>  				GQSPI_TIMEOUT, 1);
>  	if (ret)
>  		printf("%s Timeout\n", __func__);
> @@ -263,6 +276,9 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
>  
>  	debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
>  
> +	/* Dummy generic FIFO entry */
> +	zynqmp_qspi_fill_gen_fifo(priv, 0);
> +
>  	zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
>  }
>  
> 

Tested-by: Michal Simek <michal.simek at xilinx.com>

I will queue it and should be good to get it to v2021.07.

Thanks,
Michal