"mmc: rockchip_sdhci: add phy and clock config for rk3399" broke spl emmc boot

[Jack Mitchell]

On 05/11/2021 19:03, Alistair Delva wrote:
> Hi Yifeng,
> 
> Since "mmc: rockchip_sdhci: add phy and clock config for rk3399", my
> RockPi 4b device can't boot off of eMMC. It will start tpl/spl and
> then fail:
> 
> U-Boot TPL 2021.10-rc1-gac804143cf-dirty (Aug 11 2021 - 10:02:07)
> Channel 0: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> Channel 1: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> 256B stride
> lpddr4_set_rate: change freq to 400000000 mhz 0, 1
> lpddr4_set_rate: change freq to 800000000 mhz 1, 0
> Trying to boot from BOOTROM
> Returning to boot ROM...
> 
> U-Boot SPL 2021.10-rc1-gac804143cf-dirty (Aug 11 2021 - 10:02:07 +0000)
> Trying to boot from MMC1
> Card did not respond to voltage select! : -110
> spl: mmc init failed with error: -95
> SPL: failed to boot from all boot devices
> ### ERROR ### Please RESET the board ###
> 
> If I revert these changes, all is well:
> 
> commit a63a57e59d864a1ca2b0acb5fadc5c3579c3e79c
> Author: Yifeng Zhao <yifeng.zhao at rock-chips.com>
> Date:   Tue Jun 29 16:24:42 2021 +0800
> 
>    mmc: rockchip_sdhci: Add support for RK3568
> 
> commit ac804143cfd128d144403ef2434344988c3fde9f (refs/bisect/bad)
> Author: Yifeng Zhao <yifeng.zhao at rock-chips.com>
> Date:   Tue Jun 29 16:24:41 2021 +0800
> 
>    mmc: rockchip_sdhci: add phy and clock config for rk3399
> 
> Please let me know if you need help to test this.
> 
> Thanks,
> Alistair.
> 

Hi Alistair,

You need the following patch:

https://patchwork.ozlabs.org/project/uboot/patch/20211101044347.17822-1-yifeng.zhao@rock-chips.com/

Please let me know if this fixes the issue for you as some people still
have outstanding issues with this set of patches when the emmc is run
the HS200/400 modes.

Regards,
Jack.

-- 
Jack Mitchell, Consultant
https://www.tuxable.co.uk