[PATCH u-boot-marvell 03/10] pci: pci_mvebu: Move setup for BAR[0] where other BARs are setup

[Stefan Roese]

On 11/11/21 16:35, Marek Behún wrote:
> From: Pali Rohár <pali at kernel.org>
> 
> Function mvebu_pcie_setup_wins() sets up all other BARs, so move setup of
> BAR[0] to this function to have common code at one place.
> 
> In the past, commit 193a1e9f196b ("pci: pci_mvebu: set BAR0 after memory
> space is set") moved setup of BAR[0] to another location, due to ath10k
> not working in kernel, but the reason why was unknown, but it seems to
> work now, and we think the issue then was cause by the PCIe Root Port
> presenting itself as a Memory Controller and therefore U-Boot's code
> have overwritten the BAR. Since the driver now ignores any write
> operations to PCIe Root Port BARs, this should not be an issue anymore.
> 
> Signed-off-by: Pali Rohár <pali at kernel.org>
> Signed-off-by: Marek Behún <marek.behun at nic.cz>

Reviewed-by: Stefan Roese <sr at denx.de>

Thanks,
Stefan

> ---
>   drivers/pci/pci_mvebu.c | 12 +++++++-----
>   1 file changed, 7 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
> index 278dc2756f..97c7b5604f 100644
> --- a/drivers/pci/pci_mvebu.c
> +++ b/drivers/pci/pci_mvebu.c
> @@ -335,7 +335,9 @@ static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
>   
>   /*
>    * Setup PCIE BARs and Address Decode Wins:
> - * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
> + * BAR[0] -> internal registers
> + * BAR[1] -> covers all DRAM banks
> + * BAR[2] -> disabled
>    * WIN[0-3] -> DRAM bank[0-3]
>    */
>   static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
> @@ -386,6 +388,10 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
>   	writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
>   	writel(((size - 1) & 0xffff0000) | 0x1,
>   	       pcie->base + PCIE_BAR_CTRL_OFF(1));
> +
> +	/* Setup BAR[0] to internal registers. */
> +	writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
> +	writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
>   }
>   
>   static int mvebu_pcie_probe(struct udevice *dev)
> @@ -501,10 +507,6 @@ static int mvebu_pcie_probe(struct udevice *dev)
>   		       pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
>   	hose->region_count = 3;
>   
> -	/* Set BAR0 to internal registers */
> -	writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
> -	writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
> -
>   	/* PCI Bridge support 32-bit I/O and 64-bit prefetch mem addressing */
>   	pcie->cfgcache[(PCI_IO_BASE - 0x10) / 4] =
>   		PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8);
> 

Viele Grüße,
Stefan Roese

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