[PATCH 1/3] stm32mp1: ram: add read valid training support

[Patrick Delaunay]

Add the read data eye training = training for optimal read valid placement
(RVTRN) when the built-in calibration is executed for LPDDR2 and LPDDR3.

This training is supported on the PUBL integrated in the STM32MP15x
DDR subsystem and it is not required for DDR3.

Signed-off-by: Patrick Delaunay <patrick.delaunay at foss.st.com>
---

 drivers/ram/stm32mp1/stm32mp1_ddr.c      | 8 ++++++--
 drivers/ram/stm32mp1/stm32mp1_ddr_regs.h | 1 +
 2 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr.c b/drivers/ram/stm32mp1/stm32mp1_ddr.c
index 0457166b12..1f8422518b 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr.c
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr.c
@@ -826,8 +826,12 @@ start:
  */
 
 /* 10. configure PUBL PIR register to specify which training step to run */
-	/* warning : RVTRN  is not supported by this PUBL */
-		stm32mp1_ddrphy_init(priv->phy, DDRPHYC_PIR_QSTRN);
+		/* RVTRN is excuted only on LPDDR2/LPDDR3 */
+		if (config->c_reg.mstr & DDRCTRL_MSTR_DDR3)
+			pir = DDRPHYC_PIR_QSTRN;
+		else
+			pir = DDRPHYC_PIR_QSTRN | DDRPHYC_PIR_RVTRN;
+		stm32mp1_ddrphy_init(priv->phy, pir);
 
 /* 11. monitor PUB PGSR.IDONE to poll cpmpletion of training sequence */
 		ddrphy_idone_wait(priv->phy);
diff --git a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
index 3c8885a965..ada3087328 100644
--- a/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
+++ b/drivers/ram/stm32mp1/stm32mp1_ddr_regs.h
@@ -309,6 +309,7 @@ struct stm32mp1_ddrphy {
 #define DDRPHYC_PIR_DRAMRST			BIT(5)
 #define DDRPHYC_PIR_DRAMINIT			BIT(6)
 #define DDRPHYC_PIR_QSTRN			BIT(7)
+#define DDRPHYC_PIR_RVTRN			BIT(8)
 #define DDRPHYC_PIR_ICPC			BIT(16)
 #define DDRPHYC_PIR_ZCALBYP			BIT(30)
 #define DDRPHYC_PIR_INITSTEPS_MASK		GENMASK(31, 7)
-- 
2.25.1