[PATCH v2] pci: Work around PCIe link training failures

[Pali Rohár]

On Thursday 18 November 2021 00:03:58 Maciej W. Rozycki wrote:
> At that point the link changes to 5GT/s instantaneously (there's no Link 
> Training reported active, not even momentarily, or Data Link Layer Link 
> Active reported inactive), as shown by the Link Status Register at both 
> ends (and the de-emphasis level does not matter; it works at either value, 
> as reported in the Link Status 2 register, again at both ends).

Here is simplified PCIe LTSSM diagram:
https://www.oreilly.com/library/view/pci-express-system/0321156307/0321156307_ch14lev1sec6.html

Active link is in L0 state and changing link speed is performed via
Recovery state followed by Configuration and back to L0. And there is
important note that LinkUp is reported as 1b also when going into
Configuration state from Recovery state. DLLLA bit in Link Status
register reports 1b when DLCMSM is in DL_Active state. And DL_Active is
changed (to DL_Inactive) only when LinkUp changes to 0b.

So it means that DLLLA bit in Link Status is not changed during
successful link retraining when changing link speed. So your above
observation is correct that DLLLA was not changed. And reason is not so
obvious...

Link Training bit in Link Status register is 1b when link is in
Configuration or Recovery state. It is possible that link speed change
is too fast and you do not observe it (or device return old value,
sampled last time).