[PATCH 1/2] clk: zynqmp: Add support for setting up clock for USB

[Michal Simek]

On 10/29/21 13:13, Michal Simek wrote:
> USB range is not enabled but for setting up frequency it is needed.
> 
> Signed-off-by: Michal Simek <michal.simek at xilinx.com>
> ---
> 
>   drivers/clk/clk_zynqmp.c | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
> index 52fecec7a7a9..ca36df664069 100644
> --- a/drivers/clk/clk_zynqmp.c
> +++ b/drivers/clk/clk_zynqmp.c
> @@ -699,6 +699,7 @@ static ulong zynqmp_clk_set_rate(struct clk *clk, ulong rate)
>   	switch (id) {
>   	case gem0_ref ... gem3_ref:
>   	case qspi_ref ... can1_ref:
> +	case usb0_bus_ref ... usb3_dual_ref:
>   		return zynqmp_clk_set_peripheral_rate(priv, id,
>   						      rate, two_divs);
>   	default:
> 

Applied.
M

-- 
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs