[PATCH v2] pci: Work around PCIe link training failures

[Maciej W. Rozycki]

On Thu, 18 Nov 2021, Maciej W. Rozycki wrote:

> "Use the Data Link Layer Link Active status flag as the primary indicator 
> of successful link speed negotiation, but given that the flag is optional 
> by hardware to implement (the ASM2824 does have it though) [...]"

 NB I did verify the change too by making code ignore the presence of the 
DLLLA bit in the ASM2824, the usual approach in simulating a different 
environment that is not readily available.  Otherwise I would have no 
guarantee that the loop termination conditions are indeed right or what a 
reasonable timeout would be for when there is no DLLLA bit.  If that was 
the case, I'd be offering unverified code (which is sometimes inevitable) 
without mentioning that fact and/or asking for verification, and that 
would be a major fault with any submission.

 I could have mentioned it with my submission that operation without DLLLA 
has been verified, which was clearly an oversight on my side.  OTOH it's 
been routine for me when working with hardware, so it didn't occur to me 
it may not be obvious to someone else (though indeed I've seen submissions 
of varying quality, so things cannot be taken for granted).

  Maciej