Xilinx ZynqMP - ZCU102: SPL not able to use MMC/SD card

[Michal Simek]

Hi,

On 11/30/21 00:01, Daniel Cizinsky wrote:
> On Tue, Nov 09, 2021 at 09:21:41PM +0100, Daniel Cizinsky wrote:
>> Hi!
>>
>> I am trying to switch to as much current vanilla SW as possible on Xilinx
>> ZCU102 evaluation board.  But I am stuck at a very early stage.
>>
>> I've got U-Boot + SPL + Linux kernel & userspace compilled, but even after
>> trying hard I had no success in running SPL to read ATF, not even speaking
>> about the main U-Boot.
> I don't even know whether my e-mail went through to the conference. I just
> wanted to know, if not being able to use SD card on this board using a
> vanilla modern U-Boot SPL is a known bug, or if there are any people
> outthere using it successfully. Probably not, or they are not interested in
> sharing the simple fact.
> 
> With rc3 I'm getting exactly the same errors:
> 
> U-Boot SPL 2022.01-rc3 (Nov 29 2021 - 23:50:47 +0100)
> PMUFW:  v1.1
> Loading new PMUFW cfg obj (2024 bytes)
> Silicon version:        3
> EL Level:       EL3
> Multiboot:      0
> Trying to boot from MMC2
> spl: could not initialize mmc. error: -19
> Trying to boot from MMC1
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-legacy = 0 0
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-mmc-hs = 63 72
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-sd-hs = 63 60
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-uhs-sdr12 = 0 0
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-uhs-sdr25 = 63 60
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-uhs-sdr50 = 0 72
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-uhs-sdr104 = 0 135
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-uhs-ddr50 = 183 48
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-mmc-ddr52 = 54 72
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-mmc-hs200 = 0 135
> arasan_sdhci mmc at ff170000: Using predefined clock phase for clk-phase-mmc-hs400 = 0 0
> arasan_sdhci mmc at ff170000: arasan_sdhci_set_tapdelay, host:mmc at ff170000, mode:0
> CMD_SEND:0
>                  ARG                      0x00000000
>                  MMC_RSP_NONE
> CMD_SEND:8
>                  ARG                      0x000001aa
>                  RET                      -110
> CMD_SEND:55
>                  ARG                      0x00000000
>                  RET                      -110
> CMD_SEND:0
>                  ARG                      0x00000000
>                  MMC_RSP_NONE
> CMD_SEND:1
>                  ARG                      0x00000000
>                  RET                      -110
> Card did not respond to voltage select! : -110
> mmc_init: -95, time 23
> spl: mmc init failed with error: -95
> SPL: Unsupported Boot Device 0
> SPL: failed to boot from all boot devices (err=-6)
> ### ERROR ### Please RESET the board ###
> 

I did try latest yesterday and didn't see any issue. How do you build 
u-boot? And what board version do you have?

Log below.

Thanks,
Michal


U-Boot SPL 2022.01-rc2-00097-g657a869c04e9 (Nov 29 2021 - 14:15:08 +0100)
PMUFW:  v1.1
Loading new PMUFW cfg obj (2032 bytes)
Silicon version:        3
EL Level:       EL3
Chip ID:        zu9eg
Multiboot:      0
Trying to boot from MMC2
spl: could not initialize mmc. error: -19
Trying to boot from MMC1
spl_load_image_fat_os: error reading image u-boot.bin, err - -2
NOTICE:  BL31: Secure code at 0x7e000000
NOTICE:  BL31: Non secure code at 0x8000000
NOTICE:  BL31: v2.4(release):v2.4-594-g82a773bd39b4
NOTICE:  BL31: Built : 07:54:47, Oct 20 2021


U-Boot 2022.01-rc2-00097-g657a869c04e9 (Nov 29 2021 - 14:15:08 +0100)

CPU:   ZynqMP
Silicon: v3
Model: ZynqMP ZCU102 Rev1.0
Board: Xilinx ZynqMP
DRAM:  4 GiB
PMUFW:  v1.1
Xilinx I2C Legacy format at nvmem0:
  Board name:    zcu102
  Board rev:     1.0
  Board SN:      847316301727-67998
  Ethernet mac:  00:0a:35:03:70:f6
EL Level:       EL2
Chip ID:        zu9eg
NAND:  0 MiB
MMC:   mmc at ff170000: 0
Loading Environment from FAT... *** Error - No Valid Environment Area found
*** Warning - bad env area, using default environment

In:    serial
Out:   serial
Err:   serial
Bootmode: LVL_SHFT_SD_MODE1
Reset reason:   SRST
Net:
ZYNQ GEM: ff0e0000, mdio bus ff0e0000, phyaddr 12, interface rgmii-id
eth0: ethernet at ff0e0000
scanning bus for devices...
SATA link 0 timeout.
SATA link 1 timeout.
AHCI 0001.0301 32 slots 2 ports 6 Gbps 0x3 impl SATA mode
flags: 64bit ncq pm clo only pmp fbss pio slum part ccc apst
starting USB...
Bus dwc3 at fe200000: Register 2000440 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus dwc3 at fe200000 for devices... 1 USB Device(s) found
        scanning usb for storage devices... 0 Storage Device(s) found
Hit any key to stop autoboot:  0
ZynqMP>