[PATCH 2/3] phy: marvell: a3700: Fix configuring polarity invert bits

[Stefan Roese]

On 24.09.21 16:11, Pali Rohár wrote:
> phy_txd_inv or phy_rxd_inv needs to be set only in case when
> appropriate polarity is inverted. Otherwise these bits should be
> cleared.
> 
> Same change was included in TF-A project:
> https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9406
> 
> Signed-off-by: Pali Rohár <pali at kernel.org>

Applied to u-boot-marvell/master

Thanks,
Stefan

> ---
>   drivers/phy/marvell/comphy_a3700.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/phy/marvell/comphy_a3700.c b/drivers/phy/marvell/comphy_a3700.c
> index afa1295bbdb8..47a1ebd50238 100644
> --- a/drivers/phy/marvell/comphy_a3700.c
> +++ b/drivers/phy/marvell/comphy_a3700.c
> @@ -230,9 +230,13 @@ static int comphy_pcie_power_up(u32 speed, u32 invert)
>   	 */
>   	if (invert & COMPHY_POLARITY_TXD_INVERT)
>   		reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_txd_inv, 0);
> +	else
> +		reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_txd_inv);
>   
>   	if (invert & COMPHY_POLARITY_RXD_INVERT)
>   		reg_set16(phy_addr(PCIE, SYNC_PATTERN), phy_rxd_inv, 0);
> +	else
> +		reg_set16(phy_addr(PCIE, SYNC_PATTERN), 0, phy_rxd_inv);
>   
>   	/*
>   	 * 11. Release SW reset
> @@ -467,9 +471,13 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 speed, u32 invert)
>   	 */
>   	if (invert & COMPHY_POLARITY_TXD_INVERT)
>   		usb3_reg_set16(SYNC_PATTERN, phy_txd_inv, 0, lane);
> +	else
> +		usb3_reg_set16(SYNC_PATTERN, 0, phy_txd_inv, lane);
>   
>   	if (invert & COMPHY_POLARITY_RXD_INVERT)
>   		usb3_reg_set16(SYNC_PATTERN, phy_rxd_inv, 0, lane);
> +	else
> +		usb3_reg_set16(SYNC_PATTERN, 0, phy_rxd_inv, lane);
>   
>   	/*
>   	 * 10. Set max speed generation to USB3.0 5Gbps
> @@ -839,9 +847,13 @@ static int comphy_sgmii_power_up(u32 lane, u32 speed, u32 invert)
>   	 */
>   	if (invert & COMPHY_POLARITY_TXD_INVERT)
>   		reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_txd_inv, 0);
> +	else
> +		reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_txd_inv);
>   
>   	if (invert & COMPHY_POLARITY_RXD_INVERT)
>   		reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), phy_rxd_inv, 0);
> +	else
> +		reg_set16(sgmiiphy_addr(lane, SYNC_PATTERN), 0, phy_rxd_inv);
>   
>   	/*
>   	 * 19. Set PHY input ports PIN_PU_PLL, PIN_PU_TX and PIN_PU_RX to 1
> 


Viele Grüße,
Stefan

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