[PATCH 06/16] riscv: qemu: Add devicetree files for qemu_riscv32/64
Heinrich Schuchardt
heinrich.schuchardt at canonical.com
Wed Oct 13 06:21:27 CEST 2021
On 10/13/21 03:01, Simon Glass wrote:
> Add these files, generated from qemu, so there is a reference devicetree
> in the U-Boot tree.
>
> Split the existing qemu-virt into two, since we need a different
> devicetree for 32- and 64-bit machines.
>
You only sent patch 6/16 and 15/16 to me. No clue why. Please, send
complete patchsets instead of selected patches which cannot be reviewed
without the context.
Which devices exist depends on the QEMU comannd line.
The files you create here do neither reflect the superset of all QEMU
settings nor the minimum set. They do not include all devices supported
on QEMU by U-Boot either.
You cannot assume that the values in this patch will match values used
by the next invocation of QEMU.
Hence it is totally unclear what this patch might be good for.
Best regards
Heinrich
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> arch/riscv/dts/Makefile | 2 +-
> arch/riscv/dts/qemu-virt.dts | 8 -
> arch/riscv/dts/qemu-virt32.dts | 217 +++++++++++++++++++++++++++
> arch/riscv/dts/qemu-virt64.dts | 217 +++++++++++++++++++++++++++
> configs/qemu-riscv32_defconfig | 1 +
> configs/qemu-riscv32_smode_defconfig | 1 +
> configs/qemu-riscv32_spl_defconfig | 2 +-
> configs/qemu-riscv64_defconfig | 1 +
> configs/qemu-riscv64_smode_defconfig | 1 +
> configs/qemu-riscv64_spl_defconfig | 2 +-
> 10 files changed, 441 insertions(+), 11 deletions(-)
> delete mode 100644 arch/riscv/dts/qemu-virt.dts
> create mode 100644 arch/riscv/dts/qemu-virt32.dts
> create mode 100644 arch/riscv/dts/qemu-virt64.dts
>
> diff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile
> index b6e9166767b..90d3f35e6e3 100644
> --- a/arch/riscv/dts/Makefile
> +++ b/arch/riscv/dts/Makefile
> @@ -2,7 +2,7 @@
>
> dtb-$(CONFIG_TARGET_AX25_AE350) += ae350_32.dtb ae350_64.dtb
> dtb-$(CONFIG_TARGET_MICROCHIP_ICICLE) += microchip-mpfs-icicle-kit.dtb
> -dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt.dtb
> +dtb-$(CONFIG_TARGET_QEMU_VIRT) += qemu-virt32.dtb qemu-virt64.dtb
> dtb-$(CONFIG_TARGET_OPENPITON_RISCV64) += openpiton-riscv64.dtb
> dtb-$(CONFIG_TARGET_SIFIVE_UNLEASHED) += hifive-unleashed-a00.dtb
> dtb-$(CONFIG_TARGET_SIFIVE_UNMATCHED) += hifive-unmatched-a00.dtb
> diff --git a/arch/riscv/dts/qemu-virt.dts b/arch/riscv/dts/qemu-virt.dts
> deleted file mode 100644
> index fecff542b91..00000000000
> --- a/arch/riscv/dts/qemu-virt.dts
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -// SPDX-License-Identifier: GPL-2.0+
> -/*
> - * Copyright (C) 2021, Bin Meng <bmeng.cn at gmail.com>
> - */
> -
> -/dts-v1/;
> -
> -#include "binman.dtsi"
> diff --git a/arch/riscv/dts/qemu-virt32.dts b/arch/riscv/dts/qemu-virt32.dts
> new file mode 100644
> index 00000000000..3c449413523
> --- /dev/null
> +++ b/arch/riscv/dts/qemu-virt32.dts
> @@ -0,0 +1,217 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2021, Bin Meng <bmeng.cn at gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "binman.dtsi"
> +
> +/ {
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + compatible = "riscv-virtio";
> + model = "riscv-virtio,qemu";
> +
> + fw-cfg at 10100000 {
> + dma-coherent;
> + reg = <0x00 0x10100000 0x00 0x18>;
> + compatible = "qemu,fw-cfg-mmio";
> + };
> +
> + flash at 20000000 {
> + bank-width = <0x04>;
> + reg = <0x00 0x20000000 0x00 0x2000000
> + 0x00 0x22000000 0x00 0x2000000>;
> + compatible = "cfi-flash";
> + };
> +
> + chosen {
> + bootargs = [00];
> + stdout-path = "/soc/uart at 10000000";
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x00 0x80000000 0x00 0x8000000>;
> + };
> +
> + cpus {
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + timebase-frequency = <0x989680>;
> +
> + cpu at 0 {
> + phandle = <0x01>;
> + device_type = "cpu";
> + reg = <0x00>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv32imafdcsu";
> + mmu-type = "riscv,sv32";
> +
> + interrupt-controller {
> + #interrupt-cells = <0x01>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + phandle = <0x02>;
> + };
> + };
> +
> + cpu-map {
> +
> + cluster0 {
> +
> + core0 {
> + cpu = <0x01>;
> + };
> + };
> + };
> + };
> +
> + soc {
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + compatible = "simple-bus";
> + ranges;
> +
> + rtc at 101000 {
> + interrupts = <0x0b>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x101000 0x00 0x1000>;
> + compatible = "google,goldfish-rtc";
> + };
> +
> + uart at 10000000 {
> + interrupts = <0x0a>;
> + interrupt-parent = <0x03>;
> + clock-frequency = <0x384000>;
> + reg = <0x00 0x10000000 0x00 0x100>;
> + compatible = "ns16550a";
> + };
> +
> + poweroff {
> + value = <0x5555>;
> + offset = <0x00>;
> + regmap = <0x04>;
> + compatible = "syscon-poweroff";
> + };
> +
> + reboot {
> + value = <0x7777>;
> + offset = <0x00>;
> + regmap = <0x04>;
> + compatible = "syscon-reboot";
> + };
> +
> + test at 100000 {
> + phandle = <0x04>;
> + reg = <0x00 0x100000 0x00 0x1000>;
> + compatible = "sifive,test1\0sifive,test0\0syscon";
> + };
> +
> + pci at 30000000 {
> + interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
> + interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00
> + 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03
> + 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23
> + 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00
> + 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03
> + 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20
> + 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00
> + 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03
> + 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21
> + 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00
> + 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03
> + 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>;
> + ranges = <0x1000000 0x00 0x00 0x00
> + 0x3000000 0x00 0x10000 0x2000000
> + 0x00 0x40000000 0x00 0x40000000
> + 0x00 0x40000000 0x3000000 0x03
> + 0x00 0x03 0x00 0x01
> + 0x00>;
> + reg = <0x00 0x30000000 0x00 0x10000000>;
> + dma-coherent;
> + bus-range = <0x00 0xff>;
> + linux,pci-domain = <0x00>;
> + device_type = "pci";
> + compatible = "pci-host-ecam-generic";
> + #size-cells = <0x02>;
> + #interrupt-cells = <0x01>;
> + #address-cells = <0x03>;
> + };
> +
> + virtio_mmio at 10008000 {
> + interrupts = <0x08>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10008000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10007000 {
> + interrupts = <0x07>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10007000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10006000 {
> + interrupts = <0x06>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10006000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10005000 {
> + interrupts = <0x05>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10005000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10004000 {
> + interrupts = <0x04>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10004000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10003000 {
> + interrupts = <0x03>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10003000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10002000 {
> + interrupts = <0x02>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10002000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10001000 {
> + interrupts = <0x01>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10001000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + plic at c000000 {
> + phandle = <0x03>;
> + riscv,ndev = <0x35>;
> + reg = <0x00 0xc000000 0x00 0x210000>;
> + interrupts-extended = <0x02 0x0b 0x02 0x09>;
> + interrupt-controller;
> + compatible = "sifive,plic-1.0.0\0riscv,plic0";
> + #interrupt-cells = <0x01>;
> + #address-cells = <0x00>;
> + };
> +
> + clint at 2000000 {
> + interrupts-extended = <0x02 0x03 0x02 0x07>;
> + reg = <0x00 0x2000000 0x00 0x10000>;
> + compatible = "sifive,clint0\0riscv,clint0";
> + };
> + };
> +};
> diff --git a/arch/riscv/dts/qemu-virt64.dts b/arch/riscv/dts/qemu-virt64.dts
> new file mode 100644
> index 00000000000..61bc084e280
> --- /dev/null
> +++ b/arch/riscv/dts/qemu-virt64.dts
> @@ -0,0 +1,217 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2021, Bin Meng <bmeng.cn at gmail.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "binman.dtsi"
> +
> +/ {
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + compatible = "riscv-virtio";
> + model = "riscv-virtio,qemu";
> +
> + fw-cfg at 10100000 {
> + dma-coherent;
> + reg = <0x00 0x10100000 0x00 0x18>;
> + compatible = "qemu,fw-cfg-mmio";
> + };
> +
> + flash at 20000000 {
> + bank-width = <0x04>;
> + reg = <0x00 0x20000000 0x00 0x2000000
> + 0x00 0x22000000 0x00 0x2000000>;
> + compatible = "cfi-flash";
> + };
> +
> + chosen {
> + bootargs = [00];
> + stdout-path = "/soc/uart at 10000000";
> + };
> +
> + memory at 80000000 {
> + device_type = "memory";
> + reg = <0x00 0x80000000 0x00 0x8000000>;
> + };
> +
> + cpus {
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> + timebase-frequency = <0x989680>;
> +
> + cpu at 0 {
> + phandle = <0x01>;
> + device_type = "cpu";
> + reg = <0x00>;
> + status = "okay";
> + compatible = "riscv";
> + riscv,isa = "rv64imafdcsu";
> + mmu-type = "riscv,sv48";
> +
> + interrupt-controller {
> + #interrupt-cells = <0x01>;
> + interrupt-controller;
> + compatible = "riscv,cpu-intc";
> + phandle = <0x02>;
> + };
> + };
> +
> + cpu-map {
> +
> + cluster0 {
> +
> + core0 {
> + cpu = <0x01>;
> + };
> + };
> + };
> + };
> +
> + soc {
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + compatible = "simple-bus";
> + ranges;
> +
> + rtc at 101000 {
> + interrupts = <0x0b>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x101000 0x00 0x1000>;
> + compatible = "google,goldfish-rtc";
> + };
> +
> + uart at 10000000 {
> + interrupts = <0x0a>;
> + interrupt-parent = <0x03>;
> + clock-frequency = <0x384000>;
> + reg = <0x00 0x10000000 0x00 0x100>;
> + compatible = "ns16550a";
> + };
> +
> + poweroff {
> + value = <0x5555>;
> + offset = <0x00>;
> + regmap = <0x04>;
> + compatible = "syscon-poweroff";
> + };
> +
> + reboot {
> + value = <0x7777>;
> + offset = <0x00>;
> + regmap = <0x04>;
> + compatible = "syscon-reboot";
> + };
> +
> + test at 100000 {
> + phandle = <0x04>;
> + reg = <0x00 0x100000 0x00 0x1000>;
> + compatible = "sifive,test1\0sifive,test0\0syscon";
> + };
> +
> + pci at 30000000 {
> + interrupt-map-mask = <0x1800 0x00 0x00 0x07>;
> + interrupt-map = <0x00 0x00 0x00 0x01 0x03 0x20 0x00 0x00
> + 0x00 0x02 0x03 0x21 0x00 0x00 0x00 0x03
> + 0x03 0x22 0x00 0x00 0x00 0x04 0x03 0x23
> + 0x800 0x00 0x00 0x01 0x03 0x21 0x800 0x00
> + 0x00 0x02 0x03 0x22 0x800 0x00 0x00 0x03
> + 0x03 0x23 0x800 0x00 0x00 0x04 0x03 0x20
> + 0x1000 0x00 0x00 0x01 0x03 0x22 0x1000 0x00
> + 0x00 0x02 0x03 0x23 0x1000 0x00 0x00 0x03
> + 0x03 0x20 0x1000 0x00 0x00 0x04 0x03 0x21
> + 0x1800 0x00 0x00 0x01 0x03 0x23 0x1800 0x00
> + 0x00 0x02 0x03 0x20 0x1800 0x00 0x00 0x03
> + 0x03 0x21 0x1800 0x00 0x00 0x04 0x03 0x22>;
> + ranges = <0x1000000 0x00 0x00 0x00
> + 0x3000000 0x00 0x10000 0x2000000
> + 0x00 0x40000000 0x00 0x40000000
> + 0x00 0x40000000 0x3000000 0x03
> + 0x00 0x03 0x00 0x01
> + 0x00>;
> + reg = <0x00 0x30000000 0x00 0x10000000>;
> + dma-coherent;
> + bus-range = <0x00 0xff>;
> + linux,pci-domain = <0x00>;
> + device_type = "pci";
> + compatible = "pci-host-ecam-generic";
> + #size-cells = <0x02>;
> + #interrupt-cells = <0x01>;
> + #address-cells = <0x03>;
> + };
> +
> + virtio_mmio at 10008000 {
> + interrupts = <0x08>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10008000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10007000 {
> + interrupts = <0x07>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10007000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10006000 {
> + interrupts = <0x06>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10006000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10005000 {
> + interrupts = <0x05>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10005000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10004000 {
> + interrupts = <0x04>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10004000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10003000 {
> + interrupts = <0x03>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10003000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10002000 {
> + interrupts = <0x02>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10002000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + virtio_mmio at 10001000 {
> + interrupts = <0x01>;
> + interrupt-parent = <0x03>;
> + reg = <0x00 0x10001000 0x00 0x1000>;
> + compatible = "virtio,mmio";
> + };
> +
> + plic at c000000 {
> + phandle = <0x03>;
> + riscv,ndev = <0x35>;
> + reg = <0x00 0xc000000 0x00 0x210000>;
> + interrupts-extended = <0x02 0x0b 0x02 0x09>;
> + interrupt-controller;
> + compatible = "sifive,plic-1.0.0\0riscv,plic0";
> + #interrupt-cells = <0x01>;
> + #address-cells = <0x00>;
> + };
> +
> + clint at 2000000 {
> + interrupts-extended = <0x02 0x03 0x02 0x07>;
> + reg = <0x00 0x2000000 0x00 0x10000>;
> + compatible = "sifive,clint0\0riscv,clint0";
> + };
> + };
> +};
> diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig
> index e77e3ed53a0..54953cd347b 100644
> --- a/configs/qemu-riscv32_defconfig
> +++ b/configs/qemu-riscv32_defconfig
> @@ -2,6 +2,7 @@ CONFIG_RISCV=y
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x20000
> CONFIG_SYS_MALLOC_LEN=0x800000
> +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
> CONFIG_TARGET_QEMU_VIRT=y
> CONFIG_DISTRO_DEFAULTS=y
> CONFIG_SYS_LOAD_ADDR=0x80200000
> diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig
> index 03787416f10..21ee08a643e 100644
> --- a/configs/qemu-riscv32_smode_defconfig
> +++ b/configs/qemu-riscv32_smode_defconfig
> @@ -2,6 +2,7 @@ CONFIG_RISCV=y
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x20000
> CONFIG_SYS_MALLOC_LEN=0x800000
> +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
> CONFIG_TARGET_QEMU_VIRT=y
> CONFIG_RISCV_SMODE=y
> CONFIG_DISTRO_DEFAULTS=y
> diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig
> index b0e655be416..3909c9a15ad 100644
> --- a/configs/qemu-riscv32_spl_defconfig
> +++ b/configs/qemu-riscv32_spl_defconfig
> @@ -2,7 +2,7 @@ CONFIG_RISCV=y
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x20000
> CONFIG_SYS_MALLOC_LEN=0x800000
> -CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
> +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt32"
> CONFIG_SPL=y
> CONFIG_TARGET_QEMU_VIRT=y
> CONFIG_RISCV_SMODE=y
> diff --git a/configs/qemu-riscv64_defconfig b/configs/qemu-riscv64_defconfig
> index 1f8dc2d2053..303ad2d5f39 100644
> --- a/configs/qemu-riscv64_defconfig
> +++ b/configs/qemu-riscv64_defconfig
> @@ -2,6 +2,7 @@ CONFIG_RISCV=y
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x20000
> CONFIG_SYS_MALLOC_LEN=0x800000
> +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
> CONFIG_TARGET_QEMU_VIRT=y
> CONFIG_ARCH_RV64I=y
> CONFIG_DISTRO_DEFAULTS=y
> diff --git a/configs/qemu-riscv64_smode_defconfig b/configs/qemu-riscv64_smode_defconfig
> index bdcec1fdaba..62cdf91699f 100644
> --- a/configs/qemu-riscv64_smode_defconfig
> +++ b/configs/qemu-riscv64_smode_defconfig
> @@ -2,6 +2,7 @@ CONFIG_RISCV=y
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x20000
> CONFIG_SYS_MALLOC_LEN=0x800000
> +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
> CONFIG_TARGET_QEMU_VIRT=y
> CONFIG_ARCH_RV64I=y
> CONFIG_RISCV_SMODE=y
> diff --git a/configs/qemu-riscv64_spl_defconfig b/configs/qemu-riscv64_spl_defconfig
> index 9745c1a586a..34d88da41b0 100644
> --- a/configs/qemu-riscv64_spl_defconfig
> +++ b/configs/qemu-riscv64_spl_defconfig
> @@ -2,7 +2,7 @@ CONFIG_RISCV=y
> CONFIG_NR_DRAM_BANKS=1
> CONFIG_ENV_SIZE=0x20000
> CONFIG_SYS_MALLOC_LEN=0x800000
> -CONFIG_DEFAULT_DEVICE_TREE="qemu-virt"
> +CONFIG_DEFAULT_DEVICE_TREE="qemu-virt64"
> CONFIG_SPL=y
> CONFIG_TARGET_QEMU_VIRT=y
> CONFIG_ARCH_RV64I=y
>
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