[PATCH 11/16] arm: xilinx_versal_virt: Add a devicetree file
Michal Simek
michal.simek at xilinx.com
Wed Oct 13 08:13:34 CEST 2021
On 10/13/21 03:01, Simon Glass wrote:
> Add a devicetree file obtained from qemu for this board. This was obtained
> with:
>
> qemu-system-aarch64 -M xlnx-versal-virt -machine dumpdtb=dtb.dtb
>
> Signed-off-by: Simon Glass <sjg at chromium.org>
> ---
>
> arch/arm/dts/Makefile | 3 +-
> arch/arm/dts/xilinx-versal-virt.dts | 307 +++++++++++++++++++++++++++
> configs/xilinx_versal_virt_defconfig | 1 +
> 3 files changed, 310 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm/dts/xilinx-versal-virt.dts
>
> diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
> index 0fec648dd77..dd6d66af5e6 100644
> --- a/arch/arm/dts/Makefile
> +++ b/arch/arm/dts/Makefile
> @@ -352,7 +352,8 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
> dtb-$(CONFIG_ARCH_VERSAL) += \
> versal-mini.dtb \
> versal-mini-emmc0.dtb \
> - versal-mini-emmc1.dtb
> + versal-mini-emmc1.dtb \
> + xilinx-versal-virt.dtb
> dtb-$(CONFIG_ARCH_ZYNQMP_R5) += \
> zynqmp-r5.dtb
> dtb-$(CONFIG_AM33XX) += \
> diff --git a/arch/arm/dts/xilinx-versal-virt.dts b/arch/arm/dts/xilinx-versal-virt.dts
> new file mode 100644
> index 00000000000..3712af9e7a4
> --- /dev/null
> +++ b/arch/arm/dts/xilinx-versal-virt.dts
> @@ -0,0 +1,307 @@
> +// SPDX-License-Identifier: GPL-2.0+ OR MIT
> +/*
> + * Sample device tree for versal-virt board
> +
> + * Copyright 2021 Google LLC
> + */
> +
> +/dts-v1/;
> +
> +/ {
> + compatible = "xlnx-versal-virt";
> + model = "Xilinx Versal Virtual development board";
> + #address-cells = <0x02>;
> + #size-cells = <0x02>;
> + interrupt-parent = <0x8000>;
> +
> + memory at 0 {
> + reg = <0x00 0x00 0x00 0x8000000>;
> + device_type = "memory";
> + };
> +
> + clk25 {
> + u-boot,dm-pre-reloc;
> + compatible = "fixed-clock";
> + #clock-cells = <0x00>;
> + clock-frequency = <0x17d7840>;
> + phandle = <0x8003>;
> + };
> +
> + clk125 {
> + u-boot,dm-pre-reloc;
> + compatible = "fixed-clock";
> + #clock-cells = <0x00>;
> + clock-frequency = <0x7735940>;
> + phandle = <0x8004>;
> + };
> +
> + cpus {
> + #address-cells = <0x01>;
> + #size-cells = <0x00>;
> +
> + cpu at 0 {
> + compatible = "arm,cortex-a72";
> + device_type = "cpu";
> + reg = <0x00>;
> + };
> +
> + cpu at 1 {
> + compatible = "arm,cortex-a72";
> + device_type = "cpu";
> + reg = <0x01>;
> + };
> + };
> +
> + rtc at f12a0000 {
> + compatible = "xlnx,zynqmp-rtc";
> + reg = <0x00 0xf12a0000 0x00 0x10000>;
> + interrupt-names = "alarm\0sec";
> + interrupts = <0x00 0x8e 0x04 0x00 0x8f 0x04>;
> + };
> +
> + sdhci at f1040000 {
> + compatible = "arasan,sdhci-8.9a";
> + reg = <0x00 0xf1040000 0x00 0x10000>;
> + interrupts = <0x00 0x7e 0x04>;
> + clock-names = "clk_xin\0clk_ahb";
> + clocks = <0x8003 0x8003>;
> + };
> +
> + sdhci at f1050000 {
> + compatible = "arasan,sdhci-8.9a";
> + reg = <0x00 0xf1050000 0x00 0x10000>;
> + interrupts = <0x00 0x80 0x04>;
> + clock-names = "clk_xin\0clk_ahb";
> + clocks = <0x8003 0x8003>;
> + };
> +
> + usb at ff9d0000 {
> + phandle = <0x8005>;
> + #size-cells = <0x02>;
> + #address-cells = <0x02>;
> + ranges;
> + clocks = <0x8003 0x8004>;
> + clock-names = "bus_clk\0ref_clk";
> + reg = <0x00 0xff9d0000 0x00 0x10000>;
> + compatible = "xlnx,versal-dwc3";
> +
> + dwc3 at fe200000 {
> + maximum-speed = "high-speed";
> + phandle = <0x8006>;
> + snps,mask_phy_reset;
> + snps,refclk_fladj;
> + snps,dis_u3_susphy_quirk;
> + snps,dis_u2_susphy_quirk;
> + phy-names = "usb3-phy";
> + dr_mode = "host";
> + #stream-id-cells = <0x01>;
> + snps,quirk-frame-length-adjustment = <0x20>;
> + interrupts = <0x00 0x16 0x04>;
> + interrupt-names = "dwc_usb3";
> + reg = <0x00 0xfe200000 0x00 0x10000>;
> + compatible = "snps,dwc3";
> + };
> + };
> +
> + dma at ffa80000 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x00 0xffa80000 0x00 0x1000>;
> + interrupts = <0x00 0x3c 0x04>;
> + clock-names = "clk_main\0clk_apb";
> + clocks = <0x8003 0x8003>;
> + xlnx,bus-width = <0x40>;
> + };
> +
> + dma at ffa90000 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x00 0xffa90000 0x00 0x1000>;
> + interrupts = <0x00 0x3d 0x04>;
> + clock-names = "clk_main\0clk_apb";
> + clocks = <0x8003 0x8003>;
> + xlnx,bus-width = <0x40>;
> + };
> +
> + dma at ffaa0000 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x00 0xffaa0000 0x00 0x1000>;
> + interrupts = <0x00 0x3e 0x04>;
> + clock-names = "clk_main\0clk_apb";
> + clocks = <0x8003 0x8003>;
> + xlnx,bus-width = <0x40>;
> + };
> +
> + dma at ffab0000 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x00 0xffab0000 0x00 0x1000>;
> + interrupts = <0x00 0x3f 0x04>;
> + clock-names = "clk_main\0clk_apb";
> + clocks = <0x8003 0x8003>;
> + xlnx,bus-width = <0x40>;
> + };
> +
> + dma at ffac0000 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x00 0xffac0000 0x00 0x1000>;
> + interrupts = <0x00 0x40 0x04>;
> + clock-names = "clk_main\0clk_apb";
> + clocks = <0x8003 0x8003>;
> + xlnx,bus-width = <0x40>;
> + };
> +
> + dma at ffad0000 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x00 0xffad0000 0x00 0x1000>;
> + interrupts = <0x00 0x41 0x04>;
> + clock-names = "clk_main\0clk_apb";
> + clocks = <0x8003 0x8003>;
> + xlnx,bus-width = <0x40>;
> + };
> +
> + dma at ffae0000 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x00 0xffae0000 0x00 0x1000>;
> + interrupts = <0x00 0x42 0x04>;
> + clock-names = "clk_main\0clk_apb";
> + clocks = <0x8003 0x8003>;
> + xlnx,bus-width = <0x40>;
> + };
> +
> + dma at ffaf0000 {
> + compatible = "xlnx,zynqmp-dma-1.0";
> + reg = <0x00 0xffaf0000 0x00 0x1000>;
> + interrupts = <0x00 0x43 0x04>;
> + clock-names = "clk_main\0clk_apb";
> + clocks = <0x8003 0x8003>;
> + xlnx,bus-width = <0x40>;
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <0x01 0x0d 0x04 0x01 0x0e 0x04 0x01 0x0b 0x04 0x01 0x0a 0x04>;
> + };
> +
> + gic at f9000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <0x03>;
> + reg = <0x00 0xf9000000 0x00 0x10000 0x00 0xf9080000 0x00 0x80000>;
> + interrupt-controller;
> + interrupts = <0x01 0x09 0x04>;
> + phandle = <0x8000>;
> + };
> +
> + uart at ff000000 {
> + u-boot,dm-pre-reloc;
> + compatible = "arm,pl011\0arm,sbsa-uart";
> + reg = <0x00 0xff000000 0x00 0x1000>;
> + interrupts = <0x00 0x12 0x04>;
> + clock-names = "uartclk\0apb_pclk";
> + clocks = <0x8004 0x8004>;
> + current-speed = <0x1c200>;
> + };
> +
> + uart at ff010000 {
> + u-boot,dm-pre-reloc;
> + compatible = "arm,pl011\0arm,sbsa-uart";
> + reg = <0x00 0xff010000 0x00 0x1000>;
> + interrupts = <0x00 0x13 0x04>;
> + clock-names = "uartclk\0apb_pclk";
> + clocks = <0x8004 0x8004>;
> + current-speed = <0x1c200>;
> + };
> +
> + ethernet at ff0c0000 {
> + #size-cells = <0x00>;
> + #address-cells = <0x01>;
> + compatible = "cdns,zynqmp-gem\0cdns,gem";
> + reg = <0x00 0xff0c0000 0x00 0x1000>;
> + interrupts = <0x00 0x38 0x04 0x00 0x38 0x04>;
> + clock-names = "pclk\0hclk\0tx_clk\0rx_clk";
> + clocks = <0x8003 0x8003 0x8004 0x8004>;
> + phy-handle = <0x8002>;
> + phy-mode = "rgmii-id";
> +
> + fixed-link {
> + speed = <0x3e8>;
> + full-duplex;
> + phandle = <0x8002>;
> + };
> + };
> +
> + ethernet at ff0d0000 {
> + #size-cells = <0x00>;
> + #address-cells = <0x01>;
> + compatible = "cdns,zynqmp-gem\0cdns,gem";
> + reg = <0x00 0xff0d0000 0x00 0x1000>;
> + interrupts = <0x00 0x3a 0x04 0x00 0x3a 0x04>;
> + clock-names = "pclk\0hclk\0tx_clk\0rx_clk";
> + clocks = <0x8003 0x8003 0x8004 0x8004>;
> + phy-handle = <0x8001>;
> + phy-mode = "rgmii-id";
> +
> + fixed-link {
> + speed = <0x3e8>;
> + full-duplex;
> + phandle = <0x8001>;
> + };
> + };
> +
> + virtio_mmio at a0000e00 {
> + compatible = "virtio,mmio";
> + reg = <0x00 0xa0000e00 0x00 0x200>;
> + interrupts = <0x00 0x76 0x01>;
> + dma-coherent;
> + };
> +
> + virtio_mmio at a0000c00 {
> + compatible = "virtio,mmio";
> + reg = <0x00 0xa0000c00 0x00 0x200>;
> + interrupts = <0x00 0x75 0x01>;
> + dma-coherent;
> + };
> +
> + virtio_mmio at a0000a00 {
> + compatible = "virtio,mmio";
> + reg = <0x00 0xa0000a00 0x00 0x200>;
> + interrupts = <0x00 0x74 0x01>;
> + dma-coherent;
> + };
> +
> + virtio_mmio at a0000800 {
> + compatible = "virtio,mmio";
> + reg = <0x00 0xa0000800 0x00 0x200>;
> + interrupts = <0x00 0x73 0x01>;
> + dma-coherent;
> + };
> +
> + virtio_mmio at a0000600 {
> + compatible = "virtio,mmio";
> + reg = <0x00 0xa0000600 0x00 0x200>;
> + interrupts = <0x00 0x72 0x01>;
> + dma-coherent;
> + };
> +
> + virtio_mmio at a0000400 {
> + compatible = "virtio,mmio";
> + reg = <0x00 0xa0000400 0x00 0x200>;
> + interrupts = <0x00 0x71 0x01>;
> + dma-coherent;
> + };
> +
> + virtio_mmio at a0000200 {
> + compatible = "virtio,mmio";
> + reg = <0x00 0xa0000200 0x00 0x200>;
> + interrupts = <0x00 0x70 0x01>;
> + dma-coherent;
> + };
> +
> + virtio_mmio at a0000000 {
> + compatible = "virtio,mmio";
> + reg = <0x00 0xa0000000 0x00 0x200>;
> + interrupts = <0x00 0x6f 0x01>;
> + dma-coherent;
> + };
> +
> + chosen {
> + stdout-path = "/uart at ff000000";
> + };
> +};
> diff --git a/configs/xilinx_versal_virt_defconfig b/configs/xilinx_versal_virt_defconfig
> index 11598623954..f0ec2639a38 100644
> --- a/configs/xilinx_versal_virt_defconfig
> +++ b/configs/xilinx_versal_virt_defconfig
> @@ -7,6 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x100000
> CONFIG_SYS_MEMTEST_START=0x00000000
> CONFIG_SYS_MEMTEST_END=0x00001000
> CONFIG_DM_GPIO=y
> +CONFIG_DEFAULT_DEVICE_TREE="xilinx-versal-virt"
> CONFIG_CMD_FRU=y
> CONFIG_DEFINE_TCM_OCM_MMAP=y
> CONFIG_COUNTER_FREQUENCY=100000000
>
I have also concern about adding these files. When this series is
accepted from high level point of view it would be better to simply use
what we use already which describe standard versal boards. I just didn't
push that files yet.
Thanks,
Michal
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