[PATCH] spi: zynqmp_gqspi: Fix write issue at low frequencies

[Michal Simek]

On 10/19/21 16:13, Ashok Reddy Soma wrote:
> With current implementation we are seeing write issues at low frequencies
> below 15Mhz. Make below changes to fix the issue.
> 
> 1. Remove dummy genfifo entry in zynqmp_qspi_chipselect() which was
>     incorrectly added in the past
> 
> 2. Enable and poll for TX_FIFO_Empty after Tx data is filled in FIFO in
>     zynqmp_qspi_fill_tx_fifo().
> 
> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma at xilinx.com>
> ---
> 
>   drivers/spi/zynqmp_gqspi.c | 11 ++++++++---
>   1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
> index 2db4ae20f1..c772bae3cc 100644
> --- a/drivers/spi/zynqmp_gqspi.c
> +++ b/drivers/spi/zynqmp_gqspi.c
> @@ -37,6 +37,7 @@
>    */
>   #define GQSPI_IXR_TXNFULL_MASK		0x00000004 /* QSPI TX FIFO Overflow */
>   #define GQSPI_IXR_TXFULL_MASK		0x00000008 /* QSPI TX FIFO is full */
> +#define GQSPI_IXR_TXFIFOEMPTY_MASK	0x00000100 /* QSPI TX FIFO is Empty */
>   #define GQSPI_IXR_RXNEMTY_MASK		0x00000010 /* QSPI RX FIFO Not Empty */
>   #define GQSPI_IXR_GFEMTY_MASK		0x00000080 /* QSPI Generic FIFO Empty */
>   #define GQSPI_IXR_GFNFULL_MASK		0x00000200 /* QSPI GENFIFO not full */
> @@ -279,9 +280,6 @@ static void zynqmp_qspi_chipselect(struct zynqmp_qspi_priv *priv, int is_on)
>   
>   	debug("GFIFO_CMD_CS: 0x%x\n", gqspi_fifo_reg);
>   
> -	/* Dummy generic FIFO entry */
> -	zynqmp_qspi_fill_gen_fifo(priv, 0);
> -
>   	zynqmp_qspi_fill_gen_fifo(priv, gqspi_fifo_reg);
>   }
>   
> @@ -470,6 +468,13 @@ static int zynqmp_qspi_fill_tx_fifo(struct zynqmp_qspi_priv *priv, u32 size)
>   		}
>   	}
>   
> +	ret = wait_for_bit_le32(&regs->isr, GQSPI_IXR_TXFIFOEMPTY_MASK, 1,
> +				GQSPI_TIMEOUT, 1);
> +	if (ret) {
> +		printf("%s: Timeout\n", __func__);
> +		return ret;
> +	}
> +
>   	priv->tx_buf += len;
>   	return 0;
>   }
> 

applied.
M