[PATCH 12/20] imx8ulp: clock: Reset DDR controller before clock enable

[Peng Fan (OSS)]

From: Ye Li <ye.li at nxp.com>

The LPAV is not allocated to APD when dual boot, so LPAV won't
reset when APD is reset. We have to explicitly reset the DDR,
otherwise its initialization will fail.

Reviewed-by: Peng Fan <peng.fan at nxp.com>
Signed-off-by: Ye Li <ye.li at nxp.com>
Signed-off-by: Peng Fan <peng.fan at nxp.com>
---
 arch/arm/mach-imx/imx8ulp/clock.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/imx8ulp/clock.c b/arch/arm/mach-imx/imx8ulp/clock.c
index e599e6c4c6..f54fc25763 100644
--- a/arch/arm/mach-imx/imx8ulp/clock.c
+++ b/arch/arm/mach-imx/imx8ulp/clock.c
@@ -97,6 +97,9 @@ void ddrphy_pll_lock(void)
 
 void init_clk_ddr(void)
 {
+	/* disable the ddr pcc */
+	writel(0xc0000000, PCC5_LPDDR4_ADDR);
+
 	/* enable pll4 and ddrclk*/
 	cgc2_pll4_init();
 	cgc2_ddrclk_config(1, 1);
-- 
2.30.0