[PATCH 4/4] arm: bcmbca: add bcm4908 SoC support
William Zhang
william.zhang at broadcom.com
Sat Aug 6 03:34:03 CEST 2022
BCM4908 is a Broadcom B53 based WLAN AP router SoC. It is part of the
BCA (Broadband Carrier Access origin) chipset family so it's added
under ARCH_BCMBCA platform. This initial support includes a bare-bone
implementation and dts with CPU subsystem, memory and Broadcom uart.
This SoC is supported in the linux git repository so the dts and dtsi
files are stripped down version of linux copies with mininum blocks
needed by u-boot.
The u-boot image can be loaded from flash or network to the entry point
address in the memory and boot from there to the console.
Signed-off-by: William Zhang <william.zhang at broadcom.com>
---
MAINTAINERS | 1 +
arch/arm/dts/Makefile | 2 +
arch/arm/dts/bcm4908.dtsi | 127 +++++++++++++++++++++++
arch/arm/dts/bcm94908.dts | 30 ++++++
arch/arm/mach-bcmbca/Kconfig | 8 ++
arch/arm/mach-bcmbca/Makefile | 1 +
arch/arm/mach-bcmbca/bcm4908/Kconfig | 17 +++
arch/arm/mach-bcmbca/bcm4908/Makefile | 5 +
arch/arm/mach-bcmbca/bcm4908/mmu_table.c | 32 ++++++
board/broadcom/bcmbca/Kconfig | 7 ++
configs/bcm94908_defconfig | 23 ++++
include/configs/bcm94908.h | 11 ++
12 files changed, 264 insertions(+)
create mode 100644 arch/arm/dts/bcm4908.dtsi
create mode 100644 arch/arm/dts/bcm94908.dts
create mode 100644 arch/arm/mach-bcmbca/bcm4908/Kconfig
create mode 100644 arch/arm/mach-bcmbca/bcm4908/Makefile
create mode 100644 arch/arm/mach-bcmbca/bcm4908/mmu_table.c
create mode 100644 configs/bcm94908_defconfig
create mode 100644 include/configs/bcm94908.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 70e5cf3f5584..3f250942ced1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -219,6 +219,7 @@ F: board/broadcom/bcmbca/
F: drivers/timer/bcmbca-timer.c
N: bcmbca
N: bcm[9]?47622
+N: bcm[9]?4908
N: bcm[9]?4912
N: bcm[9]?63138
N: bcm[9]?63146
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 266bbc1f4386..9a6582d9c1c8 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1165,6 +1165,8 @@ dtb-$(CONFIG_ARCH_BCMSTB) += bcm7xxx.dtb
dtb-$(CONFIG_BCM47622) += \
bcm947622.dtb
+dtb-$(CONFIG_BCM4908) += \
+ bcm94908.dtb
dtb-$(CONFIG_BCM4912) += \
bcm94912.dtb
dtb-$(CONFIG_BCM63138) += \
diff --git a/arch/arm/dts/bcm4908.dtsi b/arch/arm/dts/bcm4908.dtsi
new file mode 100644
index 000000000000..0be5cfeeffa9
--- /dev/null
+++ b/arch/arm/dts/bcm4908.dtsi
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/dts-v1/;
+
+/ {
+ compatible = "brcm,bcm4908", "brcm,bcmbca";
+
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b53";
+ reg = <0x0>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b53";
+ reg = <0x1>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu2: cpu at 2 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b53";
+ reg = <0x2>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ cpu3: cpu at 3 {
+ device_type = "cpu";
+ compatible = "brcm,brahma-b53";
+ reg = <0x3>;
+ enable-method = "spin-table";
+ cpu-release-addr = <0x0 0xfff8>;
+ next-level-cache = <&l2>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ axi at 81000000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x81000000 0x4000>;
+
+ gic: interrupt-controller at 1000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0x1000 0x1000>,
+ <0x2000 0x2000>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ clocks {
+ periph_clk: periph_clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ clock-output-names = "periph";
+ };
+ };
+
+ bus at ff800000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0xff800000 0x3000>;
+
+ uart0: serial at 640 {
+ compatible = "brcm,bcm6345-uart";
+ reg = <0x640 0x18>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
+ clock-names = "refclk";
+ status = "disabled";
+ };
+
+ };
+};
diff --git a/arch/arm/dts/bcm94908.dts b/arch/arm/dts/bcm94908.dts
new file mode 100644
index 000000000000..fcbd3c430ace
--- /dev/null
+++ b/arch/arm/dts/bcm94908.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+
+/dts-v1/;
+
+#include "bcm4908.dtsi"
+
+/ {
+ model = "Broadcom BCM94908 Reference Board";
+ compatible = "brcm,bcm94908", "brcm,bcm4908", "brcm,bcmbca";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x08000000>;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm/mach-bcmbca/Kconfig b/arch/arm/mach-bcmbca/Kconfig
index a7a3b4b57ceb..eb03ef42b8d2 100644
--- a/arch/arm/mach-bcmbca/Kconfig
+++ b/arch/arm/mach-bcmbca/Kconfig
@@ -12,6 +12,13 @@ config BCM47622
select DM_SERIAL
select PL01X_SERIAL
+config BCM4908
+ bool "Support for Broadcom 4908 Family"
+ select ARM64
+ select SYS_ARCH_TIMER
+ select DM_SERIAL
+ select BCM6345_SERIAL
+
config BCM4912
bool "Support for Broadcom 4912 Family"
select ARM64
@@ -77,6 +84,7 @@ config BCM6878
select PL01X_SERIAL
source "arch/arm/mach-bcmbca/bcm47622/Kconfig"
+source "arch/arm/mach-bcmbca/bcm4908/Kconfig"
source "arch/arm/mach-bcmbca/bcm4912/Kconfig"
source "arch/arm/mach-bcmbca/bcm63138/Kconfig"
source "arch/arm/mach-bcmbca/bcm63146/Kconfig"
diff --git a/arch/arm/mach-bcmbca/Makefile b/arch/arm/mach-bcmbca/Makefile
index a7bf5a616a2a..c8c344ba7271 100644
--- a/arch/arm/mach-bcmbca/Makefile
+++ b/arch/arm/mach-bcmbca/Makefile
@@ -4,6 +4,7 @@
#
obj-$(CONFIG_BCM47622) += bcm47622/
+obj-$(CONFIG_BCM4908) += bcm4908/
obj-$(CONFIG_BCM4912) += bcm4912/
obj-$(CONFIG_BCM63138) += bcm63138/
obj-$(CONFIG_BCM63146) += bcm63146/
diff --git a/arch/arm/mach-bcmbca/bcm4908/Kconfig b/arch/arm/mach-bcmbca/bcm4908/Kconfig
new file mode 100644
index 000000000000..564bc8d2d664
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/Kconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+
+if BCM4908
+
+config TARGET_BCM94908
+ bool "Broadcom 4908 Reference Board"
+ depends on ARCH_BCMBCA
+
+config SYS_SOC
+ default "bcm4908"
+
+source "board/broadcom/bcmbca/Kconfig"
+
+endif
diff --git a/arch/arm/mach-bcmbca/bcm4908/Makefile b/arch/arm/mach-bcmbca/bcm4908/Makefile
new file mode 100644
index 000000000000..62624977034b
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Broadcom Ltd
+#
+obj-y += mmu_table.o
diff --git a/arch/arm/mach-bcmbca/bcm4908/mmu_table.c b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c
new file mode 100644
index 000000000000..5ab04083cc6c
--- /dev/null
+++ b/arch/arm/mach-bcmbca/bcm4908/mmu_table.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 Broadcom Ltd.
+ */
+#include <common.h>
+#include <asm/armv8/mmu.h>
+#include <linux/sizes.h>
+
+static struct mm_region bcm94908_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 1UL * SZ_1G,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ /* SoC peripheral */
+ .virt = 0xff800000UL,
+ .phys = 0xff800000UL,
+ .size = 0x100000,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bcm94908_mem_map;
diff --git a/board/broadcom/bcmbca/Kconfig b/board/broadcom/bcmbca/Kconfig
index 109e7a46c627..c9155fb48e0a 100644
--- a/board/broadcom/bcmbca/Kconfig
+++ b/board/broadcom/bcmbca/Kconfig
@@ -16,6 +16,13 @@ config SYS_CONFIG_NAME
endif
+if TARGET_BCM94908
+
+config SYS_CONFIG_NAME
+ default "bcm94908"
+
+endif
+
if TARGET_BCM94912
config SYS_CONFIG_NAME
diff --git a/configs/bcm94908_defconfig b/configs/bcm94908_defconfig
new file mode 100644
index 000000000000..6dfb8825ca3c
--- /dev/null
+++ b/configs/bcm94908_defconfig
@@ -0,0 +1,23 @@
+CONFIG_ARM=y
+CONFIG_COUNTER_FREQUENCY=50000000
+CONFIG_ARCH_BCMBCA=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_SYS_MALLOC_LEN=0x2000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_BCM4908=y
+CONFIG_TARGET_BCM94908=y
+CONFIG_NR_DRAM_BANKS=2
+CONFIG_DEFAULT_DEVICE_TREE="bcm94908"
+CONFIG_IDENT_STRING=" Broadcom BCM4908"
+CONFIG_SYS_LOAD_ADDR=0x01000000
+CONFIG_ENV_VARS_UBOOT_CONFIG=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2000000
+CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_DISPLAY_BOARDINFO_LATE=y
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_CACHE=y
+CONFIG_OF_EMBED=y
+CONFIG_CLK=y
diff --git a/include/configs/bcm94908.h b/include/configs/bcm94908.h
new file mode 100644
index 000000000000..1346ace4bf6c
--- /dev/null
+++ b/include/configs/bcm94908.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2022 Broadcom Ltd.
+ */
+
+#ifndef __BCM94908_H
+#define __BCM94908_H
+
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+
+#endif
--
2.37.1
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